diff options
Diffstat (limited to 'arch')
42 files changed, 2224 insertions, 892 deletions
diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c index 1e7d48f8fb..b42dac3fbe 100644 --- a/arch/arm/cpu/arm1136/mx31/devices.c +++ b/arch/arm/cpu/arm1136/mx31/devices.c @@ -38,7 +38,22 @@ void mx31_uart1_hw_init(void) } #endif +#ifdef CONFIG_SYS_MX31_UART2 +void mx31_uart2_hw_init(void) +{ + /* setup pins for UART2 */ + mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX); + mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX); + mx31_gpio_mux(MUX_RTS2__UART2_RTS_B); + mx31_gpio_mux(MUX_CTS2__UART2_CTS_B); +} +#endif + #ifdef CONFIG_MXC_SPI +/* + * Note: putting several spi setups here makes no sense as they may differ + * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3) + */ void mx31_spi2_hw_init(void) { /* SPI2 */ diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 78df7b9261..4f27e250bd 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -27,6 +27,8 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> +#define IOMUXGPR (IOMUXC_BASE + 0x008) + static u32 mx31_decode_pll(u32 reg, u32 infreq) { u32 mfi = GET_PLL_MFI(reg); @@ -141,6 +143,19 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) } +void mx31_set_gpr(enum iomux_gp_func gp, char en) +{ + u32 l; + + l = readl(IOMUXGPR); + if (en) + l |= gp; + else + l &= ~gp; + + writel(l, IOMUXGPR); +} + void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) { struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE; diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index 1b9809b2f8..ac4838f034 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -422,12 +422,39 @@ U_BOOT_CMD( "" ); +static char *get_reset_cause(void) +{ + /* read RCSR register from CCM module */ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + u32 cause = readl(&ccm->rcsr) & 0x0F; + + switch (cause) { + case 0x0000: + return "POR"; + case 0x0002: + return "JTAG"; + case 0x0004: + return "RST"; + case 0x0008: + return "WDOG"; + default: + return "unknown reset"; + } +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - printf("CPU: Freescale i.MX35 at %d MHz\n", + u32 srev = get_cpu_rev(); + + printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n", + (srev & 0xF0) >> 4, (srev & 0x0F), get_mcu_main_clk() / 1000000); - /* mxc_dump_clocks(); */ + + printf("Reset cause: %s\n", get_reset_cause()); + return 0; } #endif diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index 0310957f89..98c7e55c40 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -35,6 +35,11 @@ COBJS-$(CONFIG_SOC_DM644X) += dm644x.o COBJS-$(CONFIG_SOC_DM646X) += dm646x.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o +ifdef CONFIG_SPL_BUILD +COBJS-y += spl.o +COBJS-y += dm365_lowlevel.o +endif + SOBJS = reset.o ifndef CONFIG_SKIP_LOWLEVEL_INIT diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 02819f6f74..9ea97853c7 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -146,13 +146,15 @@ static inline unsigned pll_prediv(volatile void *pllbase) return 8; else return pll_div(pllbase, PLLC_PREDIV); +#elif defined(CONFIG_SOC_DM365) + return pll_div(pllbase, PLLC_PREDIV); #endif return 1; } static inline unsigned pll_postdiv(volatile void *pllbase) { -#ifdef CONFIG_SOC_DM355 +#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365) return pll_div(pllbase, PLLC_POSTDIV); #elif defined(CONFIG_SOC_DM6446) if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) @@ -171,9 +173,13 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) #endif /* the PLL might be bypassed */ - if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) { + if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) { base /= pll_prediv(pllbase); +#if defined(CONFIG_SOC_DM365) + base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff); +#else base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff); +#endif base /= pll_postdiv(pllbase); } return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); @@ -184,8 +190,13 @@ int print_cpuinfo(void) /* REVISIT fetch and display CPU ID and revision information * too ... that will matter as more revisions appear. */ +#if defined(CONFIG_SOC_DM365) + printf("Cores: ARM %d MHz", + pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV)); +#else printf("Cores: ARM %d MHz", pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV)); +#endif #ifdef DSP_PLLDIV printf(", DSP %d MHz", @@ -194,8 +205,13 @@ int print_cpuinfo(void) printf("\nDDR: %d MHz\n", /* DDR PHY uses an x2 input clock */ +#if defined(CONFIG_SOC_DM365) + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV) + / 2); +#else pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV) / 2); +#endif return 0; } @@ -205,6 +221,13 @@ unsigned int davinci_arm_clk_get() return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000; } #endif + +#if defined(CONFIG_SOC_DM365) +unsigned int davinci_clk_get(unsigned int div) +{ + return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000; +} +#endif #endif /* CONFIG_DISPLAY_CPUINFO */ #endif /* !CONFIG_SOC_DA8XX */ diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c new file mode 100644 index 0000000000..3772e64cc4 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c @@ -0,0 +1,439 @@ +/* + * SoC-specific lowlevel code for tms320dm365 and similar chips + * Actually used for booting from NAND with nand_spl. + * + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <common.h> +#include <nand.h> +#include <ns16550.h> +#include <post.h> +#include <asm/arch/dm365_lowlevel.h> +#include <asm/arch/hardware.h> + +void dm365_waitloop(unsigned long loopcnt) +{ + unsigned long i; + + for (i = 0; i < loopcnt; i++) + asm(" NOP"); +} + +int dm365_pll1_init(unsigned long pllmult, unsigned long prediv) +{ + unsigned int clksrc = 0x0; + + /* Power up the PLL */ + clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN); + + clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); + setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8); + + /* + * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled + * through MMR + */ + clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC); + + /* Set PLLEN=0 => PLL BYPASS MODE */ + clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); + + dm365_waitloop(150); + + /* PLLRST=1(reset assert) */ + setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); + + dm365_waitloop(300); + + /*Bring PLL out of Reset*/ + clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); + + /* Program the Multiper and Pre-Divider for PLL1 */ + writel(pllmult, &dv_pll0_regs->pllm); + writel(prediv, &dv_pll0_regs->prediv); + + /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */ + writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE | + PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); + /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */ + writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE, + &dv_pll0_regs->secctl); + /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */ + writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl); + /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */ + writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); + + /* Program the PostDiv for PLL1 */ + writel(0x8000, &dv_pll0_regs->postdiv); + + /* Post divider setting for PLL1 */ + writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1); + writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2); + writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3); + writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4); + writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5); + writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6); + writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7); + writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8); + writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9); + + dm365_waitloop(300); + + /* Set the GOSET bit */ + writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */ + + dm365_waitloop(300); + + /* Wait for PLL to LOCK */ + while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK) + == PLL0_LOCK)) + ; + + /* Enable the PLL Bit of PLLCTL*/ + setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); + + return 0; +} + +int dm365_pll2_init(unsigned long pllm, unsigned long prediv) +{ + unsigned int clksrc = 0x0; + + /* Power up the PLL*/ + clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN); + + /* + * Select the Clock Mode as Onchip Oscilator or External Clock on + * MXI pin + * VDB has input on MXI pin + */ + clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9); + setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8); + + /* + * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled + * through MMR + */ + clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC); + + /* Set PLLEN=0 => PLL BYPASS MODE */ + clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); + + dm365_waitloop(50); + + /* PLLRST=1(reset assert) */ + setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST); + + dm365_waitloop(300); + + /* Bring PLL out of Reset */ + clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST); + + /* Program the Multiper and Pre-Divider for PLL2 */ + writel(pllm, &dv_pll1_regs->pllm); + writel(prediv, &dv_pll1_regs->prediv); + + writel(0x8000, &dv_pll1_regs->postdiv); + + /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */ + writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE | + PLLSECCTL_TINITZ, &dv_pll1_regs->secctl); + /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */ + writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE, + &dv_pll1_regs->secctl); + /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */ + writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl); + /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */ + writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl); + + /* Post divider setting for PLL2 */ + writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1); + writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2); + writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3); + writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4); + writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5); + + /* GoCmd for PostDivider to take effect */ + writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd); + + dm365_waitloop(150); + + /* Wait for PLL to LOCK */ + while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK) + == PLL1_LOCK)) + ; + + dm365_waitloop(4100); + + /* Enable the PLL2 */ + setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); + + /* do this after PLL's have been set up */ + writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL, + &dv_sys_module_regs->peri_clkctl); + + return 0; +} + +int dm365_ddr_setup(void) +{ + lpsc_on(DAVINCI_LPSC_DDR_EMIF); + clrbits_le32(&dv_sys_module_regs->vtpiocr, + VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN); + + /* Set bit CLRZ (bit 13) */ + setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ); + + /* Check VTP READY Status */ + while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY)) + ; + + /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */ + setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN); + + /* Set bit LOCK(bit7) */ + setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK); + + /* + * Powerdown VTP as it is locked (bit 6) + * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) + */ + setbits_le32(&dv_sys_module_regs->vtpiocr, + VPTIO_IOPWRDN | VPTIO_PWRDN); + + /* Wait for calibration to complete */ + dm365_waitloop(150); + + /* Set the DDR2 to synreset, then enable it again */ + lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF); + lpsc_on(DAVINCI_LPSC_DDR_EMIF); + + writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); + + /* Program SDRAM Bank Config Register */ + writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK), + &dv_ddr2_regs_ctrl->sdbcr); + writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK), + &dv_ddr2_regs_ctrl->sdbcr); + + /* Program SDRAM Timing Control Register1 */ + writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); + /* Program SDRAM Timing Control Register2 */ + writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); + + writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); + + writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr); + + /* Program SDRAM Refresh Control Register */ + writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr); + + lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF); + lpsc_on(DAVINCI_LPSC_DDR_EMIF); + + return 0; +} + +void dm365_vpss_sync_reset(void) +{ + unsigned int PdNum = 0; + + /* VPSS_CLKMD 1:1 */ + setbits_le32(&dv_sys_module_regs->vpss_clkctl, + VPSS_CLK_CTL_VPSS_CLKMD); + + /* LPSC SyncReset DDR Clock Enable */ + writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) | + PSC_SYNCRESET), &dv_psc_regs->mdctl[47]); + + writel((1 << PdNum), &dv_psc_regs->ptcmd); + + while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0)) + ; + while (!((readl(&dv_psc_regs->mdstat[47]) & PSC_MD_STATE_MSK) == + PSC_SYNCRESET)) + ; +} + +void dm365_por_reset(void) +{ + if (readl(&dv_pll0_regs->rstype) & 3) + dm365_vpss_sync_reset(); +} + +void dm365_psc_init(void) +{ + unsigned char i = 0; + unsigned char lpsc_start; + unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax; + unsigned int PdNum = 0; + + lpscmin = 0; + lpscmax = 2; + + for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) { + if (lpscgroup == 0) { + lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */ + lpsc_end = 28; + } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */ + lpsc_start = 38; + lpsc_end = 47; + } else { + lpsc_start = 50; + lpsc_end = 51; + } + + /* NEXT=0x3, Enable LPSC's */ + for (i = lpsc_start; i <= lpsc_end; i++) + setbits_le32(&dv_psc_regs->mdctl[i], 0x3); + + /* + * Program goctl to start transition sequence for LPSCs + * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power + * Domain 0 Modules + */ + writel((1 << PdNum), &dv_psc_regs->ptcmd); + + /* + * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0 + */ + while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) + == 0)) + ; + + /* Wait for MODSTAT = ENABLE from LPSC's */ + for (i = lpsc_start; i <= lpsc_end; i++) + while (!((readl(&dv_psc_regs->mdstat[i]) & + PSC_MD_STATE_MSK) == 0x3)) + ; + } +} + +static void dm365_emif_init(void) +{ + writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr); + writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr); + + setbits_le32(&davinci_emif_regs->nandfcr, 1); + + writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr); + + return; +} + +void dm365_pinmux_ctl(unsigned long offset, unsigned long mask, + unsigned long value) +{ + clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask); + setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value)); +} + +__attribute__((weak)) +void board_gpio_init(void) +{ + return; +} + +#if defined(CONFIG_POST) +int post_log(char *format, ...) +{ + return 0; +} +#endif + +void dm36x_lowlevel_init(ulong bootflag) +{ + /* + * copied from arch/arm/cpu/arm926ejs/start.S + * + * flush v4 I/D caches + */ + asm("mov r0, #0"); + asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */ + asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + asm("mrc p15, 0, r0, c1, c0, 0"); + /* clear bits 13, 9:8 (--V- --RS) */ + asm("bic r0, r0, #0x00002300"); + /* clear bits 7, 2:0 (B--- -CAM) */ + asm("bic r0, r0, #0x00000087"); + /* set bit 2 (A) Align */ + asm("orr r0, r0, #0x00000002"); + /* set bit 12 (I) I-Cache */ + asm("orr r0, r0, #0x00001000"); + asm("mcr p15, 0, r0, c1, c0, 0"); + + /* Mask all interrupts */ + writel(0x04, &dv_aintc_regs->intctl); + writel(0x0, &dv_aintc_regs->eabase); + writel(0x0, &dv_aintc_regs->eint0); + writel(0x0, &dv_aintc_regs->eint1); + + /* Clear all interrupts */ + writel(0xffffffff, &dv_aintc_regs->fiq0); + writel(0xffffffff, &dv_aintc_regs->fiq1); + writel(0xffffffff, &dv_aintc_regs->irq0); + writel(0xffffffff, &dv_aintc_regs->irq1); + + /* System PSC setup - enable all */ + dm365_psc_init(); + + /* Setup Pinmux */ + dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0); + dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1); + dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2); + dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3); + dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4); + + /* PLL setup */ + dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM, + CONFIG_SYS_DM36x_PLL1_PREDIV); + dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM, + CONFIG_SYS_DM36x_PLL2_PREDIV); + + /* GPIO setup */ + board_gpio_init(); + + NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + + /* + * Fix Power and Emulation Management Register + * see sprufh2.pdf page 38 Table 22 + */ + writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30)); + puts("ddr init\n"); + dm365_ddr_setup(); + + puts("emif init\n"); + dm365_emif_init(); + +#if defined(CONFIG_POST) + /* + * Do memory tests, calls arch_memory_failure_handle() + * if error detected. + */ + memory_post_test(0); +#endif +} diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c index 707fa47e31..3e925181ea 100644 --- a/arch/arm/cpu/arm926ejs/davinci/psc.c +++ b/arch/arm/cpu/arm926ejs/davinci/psc.c @@ -46,7 +46,7 @@ */ /* Works on Always On power domain only (no PD argument) */ -void lpsc_on(unsigned int id) +static void lpsc_transition(unsigned int id, unsigned int state) { dv_reg_p mdstat, mdctl, ptstat, ptcmd; #ifdef CONFIG_SOC_DA8XX @@ -83,10 +83,10 @@ void lpsc_on(unsigned int id) while (readl(ptstat) & 0x01) continue; - if ((readl(mdstat) & PSC_MDSTAT_STATE) == 0x03) - return; /* Already on and enabled */ + if ((readl(mdstat) & PSC_MDSTAT_STATE) == state) + return; /* Already in that state */ - writel(readl(mdctl) | 0x03, mdctl); + writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl); switch (id) { #ifdef CONFIG_SOC_DM644X @@ -114,10 +114,20 @@ void lpsc_on(unsigned int id) while (readl(ptstat) & 0x01) continue; - while ((readl(mdstat) & PSC_MDSTAT_STATE) != 0x03) + while ((readl(mdstat) & PSC_MDSTAT_STATE) != state) continue; } +void lpsc_on(unsigned int id) +{ + lpsc_transition(id, 0x03); +} + +void lpsc_syncreset(unsigned int id) +{ + lpsc_transition(id, 0x01); +} + /* Not all DaVinci chips have a DSP power domain. */ #ifdef CONFIG_SOC_DM644X diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c new file mode 100644 index 0000000000..d9b9398b7e --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <nand.h> +#include <asm/arch/dm365_lowlevel.h> +#include <ns16550.h> + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c); +} + +inline void hang(void) +{ + puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; +} + +void board_init_f(ulong dummy) +{ + dm36x_lowlevel_init(0); + relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE); +} + +void board_init_r(gd_t *id, ulong dummy) +{ + + nand_init(); + puts("Nand boot...\n"); + nand_boot(); +} diff --git a/arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s b/arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s deleted file mode 100644 index e69de29bb2..0000000000 --- a/arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s +++ /dev/null diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 5e30745057..339c5ed6bd 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -126,7 +126,15 @@ _fiq: .globl _TEXT_BASE _TEXT_BASE: +#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ .word CONFIG_SYS_TEXT_BASE +#else +#ifdef CONFIG_SPL_BUILD + .word CONFIG_SPL_TEXT_BASE +#else + .word CONFIG_SYS_TEXT_BASE +#endif +#endif /* * These are defined in the board-specific linker script. @@ -146,6 +154,12 @@ _bss_end_ofs: _end_ofs: .word _end - _start +#ifdef CONFIG_NAND_U_BOOT +.globl _end +_end: + .word __bss_end__ +#endif + #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -186,7 +200,15 @@ reset: /* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: +#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) +#else +#ifdef CONFIG_SPL_BUILD + ldr sp, =(CONFIG_SPL_STACK) +#else ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) +#endif +#endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ ldr r0,=0x00000000 bl board_init_f @@ -211,6 +233,7 @@ stack_setup: mov sp, r4 adr r0, _start + sub r9, r6, r0 /* r9 <- relocation offset */ cmp r0, r6 beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy loop */ @@ -265,12 +288,17 @@ fixnext: #endif clear_bss: -#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_SPL_BUILD + /* No relocation for SPL */ + ldr r0, =__bss_start + ldr r1, =__bss_end__ +#else ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ add r0, r0, r4 add r1, r1, r4 +#endif mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ @@ -278,6 +306,7 @@ clbss_l:str r2, [r0] /* clear loop... */ cmp r0, r1 bne clbss_l +#ifndef CONFIG_SPL_BUILD bl coloured_LED_init bl red_led_on #endif diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 7e37221e03..01f6d759b9 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -180,6 +180,21 @@ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 bne 1b +#else + ldr r1, =0x3FFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + ldr r1, =0x0 + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR7] + + ldr r1, =0x00030000 + str r1, [r0, #CLKCTL_CCGR4] + ldr r1, =0x00FFF030 + str r1, [r0, #CLKCTL_CCGR5] + ldr r1, =0x0F00030F + str r1, [r0, #CLKCTL_CCGR6] #endif /* Switch ARM to step clock */ diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index d37ca0ff5a..2c59d2b36b 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -156,6 +156,8 @@ void preloader_console_init(void) serial_init(); /* serial communications setup */ + gd->have_console = 1; + /* Avoid a second "U-Boot" coming from this string */ u_boot_rev = &u_boot_rev[7]; diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 1e265c689f..09ed6508b9 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -20,13 +20,6 @@ #define _SYS_PROTO_H_ #define BOARD_REV_ID 0x0 -struct { - u32 board_type_v1; - u32 board_type_v2; - u32 mtype; - char *board_string; - char *nand_string; -} board_sysinfo; u32 get_cpu_rev(void); u32 get_sysboot_value(void); diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h index d2094e5303..637f3130ef 100644 --- a/arch/arm/include/asm/arch-armada100/config.h +++ b/arch/arm/include/asm/arch-armada100/config.h @@ -33,6 +33,8 @@ #include <asm/arch/armada100.h> #define CONFIG_ARM926EJS 1 /* Basic Architecture */ +/* default Dcache Line length for armada100 */ +#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ #define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ diff --git a/arch/arm/include/asm/arch-davinci/aintc_defs.h b/arch/arm/include/asm/arch-davinci/aintc_defs.h new file mode 100644 index 0000000000..8f37053209 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/aintc_defs.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DV_AINTC_DEFS_H_ +#define _DV_AINTC_DEFS_H_ + +struct dv_aintc_regs { + unsigned int fiq0; /* 0x00 */ + unsigned int fiq1; /* 0x04 */ + unsigned int irq0; /* 0x08 */ + unsigned int irq1; /* 0x0c */ + unsigned int fiqentry; /* 0x10 */ + unsigned int irqentry; /* 0x14 */ + unsigned int eint0; /* 0x18 */ + unsigned int eint1; /* 0x1c */ + unsigned int intctl; /* 0x20 */ + unsigned int eabase; /* 0x24 */ + unsigned char rsvd0[8]; /* 0x28 */ + unsigned int intpri0; /* 0x30 */ + unsigned int intpri1; /* 0x34 */ + unsigned int intpri2; /* 0x38 */ + unsigned int intpri3; /* 0x3c */ + unsigned int intpri4; /* 0x40 */ + unsigned int intpri5; /* 0x44 */ + unsigned int intpri6; /* 0x48 */ + unsigned int intpri7; /* 0x4c */ +}; + +#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE) + +#endif /* _DV_AINTC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-davinci/da8xx-fb.h b/arch/arm/include/asm/arch-davinci/da8xx-fb.h new file mode 100644 index 0000000000..6d2327c8c0 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/da8xx-fb.h @@ -0,0 +1,126 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2008-2009 MontaVista Software Inc. + * Copyright (C) 2008-2009 Texas Instruments Inc + * + * Based on the LCD driver for TI Avalanche processors written by + * Ajay Singh and Shalom Hai. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option)any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef DA8XX_FB_H +#define DA8XX_FB_H + +enum panel_type { + QVGA = 0 +}; + +enum panel_shade { + MONOCHROME = 0, + COLOR_ACTIVE, + COLOR_PASSIVE, +}; + +enum raster_load_mode { + LOAD_DATA = 1, + LOAD_PALETTE, +}; + +struct display_panel { + enum panel_type panel_type; /* QVGA */ + int max_bpp; + int min_bpp; + enum panel_shade panel_shade; +}; + +struct da8xx_panel { + const char name[25]; /* Full name <vendor>_<model> */ + unsigned short width; + unsigned short height; + int hfp; /* Horizontal front porch */ + int hbp; /* Horizontal back porch */ + int hsw; /* Horizontal Sync Pulse Width */ + int vfp; /* Vertical front porch */ + int vbp; /* Vertical back porch */ + int vsw; /* Vertical Sync Pulse Width */ + unsigned int pxl_clk; /* Pixel clock */ + unsigned char invert_pxl_clk; /* Invert Pixel clock */ +}; + +struct da8xx_lcdc_platform_data { + const char manu_name[10]; + void *controller_data; + const char type[25]; + void (*panel_power_ctrl)(int); +}; + +struct lcd_ctrl_config { + const struct display_panel *p_disp_panel; + + /* AC Bias Pin Frequency */ + int ac_bias; + + /* AC Bias Pin Transitions per Interrupt */ + int ac_bias_intrpt; + + /* DMA burst size */ + int dma_burst_sz; + + /* Bits per pixel */ + int bpp; + + /* FIFO DMA Request Delay */ + int fdd; + + /* TFT Alternative Signal Mapping (Only for active) */ + unsigned char tft_alt_mode; + + /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */ + unsigned char stn_565_mode; + + /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ + unsigned char mono_8bit_mode; + + /* Invert line clock */ + unsigned char invert_line_clock; + + /* Invert frame clock */ + unsigned char invert_frm_clock; + + /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ + unsigned char sync_edge; + + /* Horizontal and Vertical Sync: Control: 0=ignore */ + unsigned char sync_ctrl; + + /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ + unsigned char raster_order; +}; + +struct lcd_sync_arg { + int back_porch; + int front_porch; + int pulse_width; +}; + +void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel); + +#endif /* ifndef DA8XX_FB_H */ + diff --git a/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h b/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h new file mode 100644 index 0000000000..4986e82983 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h @@ -0,0 +1,41 @@ +/* + * SoC-specific lowlevel code for tms320dm365 and similar chips + * + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __DM365_LOWLEVEL_H +#define __DM365_LOWLEVEL_H + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/io.h> + +void dm365_waitloop(unsigned long loopcnt); +int dm365_pll1_init(unsigned long pllmult, unsigned long prediv); +int dm365_pll2_init(unsigned long pllm, unsigned long prediv); +int dm365_ddr_setup(void); +void dm365_por_reset(void); +void dm365_psc_init(void); +void dm365_pinmux_ctl(unsigned long offset, unsigned long mask, + unsigned long value); +void dm36x_lowlevel_init(ulong bootflag); + +#endif /* #ifndef __DM365_LOWLEVEL_H */ diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 431e87bac4..bea14993e6 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -56,6 +56,7 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_DMA_3PTC1_BASE (0x01c10400) #define DAVINCI_UART0_BASE (0x01c20000) #define DAVINCI_UART1_BASE (0x01c20400) +#define DAVINCI_TIMER3_BASE (0x01c20800) #define DAVINCI_I2C_BASE (0x01c21000) #define DAVINCI_TIMER0_BASE (0x01c21400) #define DAVINCI_TIMER1_BASE (0x01c21800) @@ -63,6 +64,7 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_PWM0_BASE (0x01c22000) #define DAVINCI_PWM1_BASE (0x01c22400) #define DAVINCI_PWM2_BASE (0x01c22800) +#define DAVINCI_TIMER4_BASE (0x01c23800) #define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000) #define DAVINCI_PLL_CNTRL0_BASE (0x01c40800) #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) @@ -108,6 +110,9 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_MMC_SD1_BASE 0x01d00000 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000 #define DAVINCI_MMC_SD0_BASE 0x01d11000 +#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000 +#define DAVINCI_SPI0_BASE 0x01c66000 +#define DAVINCI_SPI1_BASE 0x01c66800 #elif defined(CONFIG_SOC_DM646X) #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000 @@ -157,6 +162,7 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000 #define DAVINCI_INTC_BASE 0xfffee000 #define DAVINCI_BOOTCFG_BASE 0x01c14000 +#define DAVINCI_LCD_CNTL_BASE 0x01e13000 #define DAVINCI_L3CBARAM_BASE 0x80000000 #define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18) #define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24) @@ -171,6 +177,10 @@ typedef volatile unsigned int * dv_reg_p; #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) #define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44) +#define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88) +#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c) +#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90) +#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94) #endif /* CONFIG_SOC_DA8XX */ /* Power and Sleep Controller (PSC) Domains */ @@ -292,6 +302,7 @@ typedef volatile unsigned int * dv_reg_p; #endif /* CONFIG_SOC_DA8XX */ void lpsc_on(unsigned int id); +void lpsc_syncreset(unsigned int id); void dsp_on(void); void davinci_enable_uart0(void); @@ -358,6 +369,7 @@ struct davinci_psc_regs { #endif /* CONFIG_SOC_DA8XX */ #define PSC_MDSTAT_STATE 0x3f +#define PSC_MDCTL_NEXT 0x07 #ifndef CONFIG_SOC_DA8XX @@ -434,7 +446,8 @@ struct davinci_syscfg_regs { dv_reg rsvd[13]; dv_reg kick0; dv_reg kick1; - dv_reg rsvd1[56]; + dv_reg rsvd1[53]; + dv_reg mstpri[3]; dv_reg pinmux[20]; dv_reg suspsrc; dv_reg chipsig; @@ -454,7 +467,7 @@ struct davinci_syscfg_regs { #define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16) #define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21) #define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22) -#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) +#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18) #define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) struct davinci_syscfg1_regs { @@ -541,4 +554,14 @@ static inline int get_async3_src(void) #endif /* CONFIG_SOC_DA8XX */ +#if defined(CONFIG_SOC_DM365) +#include <asm/arch/aintc_defs.h> +#include <asm/arch/ddr2_defs.h> +#include <asm/arch/emif_defs.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pll_defs.h> +#include <asm/arch/psc_defs.h> +#include <asm/arch/syscfg_defs.h> +#include <asm/arch/timer_defs.h> +#endif #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h new file mode 100644 index 0000000000..5c309533a2 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/pll_defs.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DV_PLL_DEFS_H_ +#define _DV_PLL_DEFS_H_ + +struct dv_pll_regs { + unsigned int pid; /* 0x00 */ + unsigned char rsvd0[224]; /* 0x04 */ + unsigned int rstype; /* 0xe4 */ + unsigned char rsvd1[24]; /* 0xe8 */ + unsigned int pllctl; /* 0x100 */ + unsigned char rsvd2[4]; /* 0x104 */ + unsigned int secctl; /* 0x108 */ + unsigned int rv; /* 0x10c */ + unsigned int pllm; /* 0x110 */ + unsigned int prediv; /* 0x114 */ + unsigned int plldiv1; /* 0x118 */ + unsigned int plldiv2; /* 0x11c */ + unsigned int plldiv3; /* 0x120 */ + unsigned int oscdiv1; /* 0x124 */ + unsigned int postdiv; /* 0x128 */ + unsigned int bpdiv; /* 0x12c */ + unsigned char rsvd5[8]; /* 0x130 */ + unsigned int pllcmd; /* 0x138 */ + unsigned int pllstat; /* 0x13c */ + unsigned int alnctl; /* 0x140 */ + unsigned int dchange; /* 0x144 */ + unsigned int cken; /* 0x148 */ + unsigned int ckstat; /* 0x14c */ + unsigned int systat; /* 0x150 */ + unsigned char rsvd6[12]; /* 0x154 */ + unsigned int plldiv4; /* 0x160 */ + unsigned int plldiv5; /* 0x164 */ + unsigned int plldiv6; /* 0x168 */ + unsigned int plldiv7; /* 0x16C */ + unsigned int plldiv8; /* 0x170 */ + unsigned int plldiv9; /* 0x174 */ +}; + +#define PLLCTL_PLLEN (1 << 0) +#define PLLCTL_PLLPWRDN (1 << 1) +#define PLLCTL_PLLRST (1 << 3) +#define PLLCTL_PLLENSRC (1 << 5) +#define PLLCTL_RES_9 (1 << 8) + +#define PLLSECCTL_TINITZ (1 << 16) +#define PLLSECCTL_TENABLE (1 << 17) +#define PLLSECCTL_TENABLEDIV (1 << 18) +#define PLLSECCTL_STOPMODE (1 << 22) + +#define PLLCMD_GOSET (1 << 0) + +#define PLL0_LOCK 0x07000000 +#define PLL1_LOCK 0x07000000 + +#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) +#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE) + +#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2)) +#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7)) +#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4)) + +unsigned int davinci_clk_get(unsigned int div); +#endif /* _DV_PLL_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-davinci/psc_defs.h b/arch/arm/include/asm/arch-davinci/psc_defs.h new file mode 100644 index 0000000000..084b015738 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/psc_defs.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DV_PSC_DEFS_H_ +#define _DV_PSC_DEFS_H_ + +/* + * Power/Sleep Ctrl Register structure + * See sprufb3.pdf, Chapter 7 + */ +struct dv_psc_regs { + unsigned int pid; /* 0x000 */ + unsigned char rsvd0[16]; /* 0x004 */ + unsigned char rsvd1[4]; /* 0x014 */ + unsigned int inteval; /* 0x018 */ + unsigned char rsvd2[36]; /* 0x01C */ + unsigned int merrpr0; /* 0x040 */ + unsigned int merrpr1; /* 0x044 */ + unsigned char rsvd3[8]; /* 0x048 */ + unsigned int merrcr0; /* 0x050 */ + unsigned int merrcr1; /* 0x054 */ + unsigned char rsvd4[8]; /* 0x058 */ + unsigned int perrpr; /* 0x060 */ + unsigned char rsvd5[4]; /* 0x064 */ + unsigned int perrcr; /* 0x068 */ + unsigned char rsvd6[4]; /* 0x06C */ + unsigned int epcpr; /* 0x070 */ + unsigned char rsvd7[4]; /* 0x074 */ + unsigned int epccr; /* 0x078 */ + unsigned char rsvd8[144]; /* 0x07C */ + unsigned char rsvd9[20]; /* 0x10C */ + unsigned int ptcmd; /* 0x120 */ + unsigned char rsvd10[4]; /* 0x124 */ + unsigned int ptstat; /* 0x128 */ + unsigned char rsvd11[212]; /* 0x12C */ + unsigned int pdstat0; /* 0x200 */ + unsigned int pdstat1; /* 0x204 */ + unsigned char rsvd12[248]; /* 0x208 */ + unsigned int pdctl0; /* 0x300 */ + unsigned int pdctl1; /* 0x304 */ + unsigned char rsvd13[536]; /* 0x308 */ + unsigned int mckout0; /* 0x520 */ + unsigned int mckout1; /* 0x524 */ + unsigned char rsvd14[728]; /* 0x528 */ + unsigned int mdstat[52]; /* 0x800 */ + unsigned char rsvd15[304]; /* 0x8D0 */ + unsigned int mdctl[52]; /* 0xA00 */ +}; + +/* PSC constants */ +#define EMURSTIE_MASK (0x00000200) + +#define PD0 (0) + +#define PSC_ENABLE (0x3) +#define PSC_DISABLE (0x2) +#define PSC_SYNCRESET (0x1) +#define PSC_SWRSTDISABLE (0x0) + +#define PSC_GOSTAT (1 << 0) +#define PSC_MD_STATE_MSK (0x1f) + +#define PSC_CMD_GO (1 << 0) + +#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE) + +#endif /* _DV_PSC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-davinci/syscfg_defs.h b/arch/arm/include/asm/arch-davinci/syscfg_defs.h new file mode 100644 index 0000000000..05af0200db --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/syscfg_defs.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DV_SYSCFG_DEFS_H_ +#define _DV_SYSCFG_DEFS_H_ + +#ifndef CONFIG_SOC_DA8XX +/* System Control Module register structure for DM365 */ +struct dv_sys_module_regs { + unsigned int pinmux[5]; /* 0x00 */ + unsigned int bootcfg; /* 0x14 */ + unsigned int arm_intmux; /* 0x18 */ + unsigned int edma_evtmux; /* 0x1C */ + unsigned int ddr_slew; /* 0x20 */ + unsigned int clkout; /* 0x24 */ + unsigned int device_id; /* 0x28 */ + unsigned int vdac_config; /* 0x2C */ + unsigned int timer64_ctl; /* 0x30 */ + unsigned int usbbphy_ctl; /* 0x34 */ + unsigned int misc; /* 0x38 */ + unsigned int mstpri[2]; /* 0x3C */ + unsigned int vpss_clkctl; /* 0x44 */ + unsigned int peri_clkctl; /* 0x48 */ + unsigned int deepsleep; /* 0x4C */ + unsigned int dft_enable; /* 0x50 */ + unsigned int debounce[8]; /* 0x54 */ + unsigned int vtpiocr; /* 0x74 */ + unsigned int pupdctl0; /* 0x78 */ + unsigned int pupdctl1; /* 0x7C */ + unsigned int hdimcopbt; /* 0x80 */ + unsigned int pll0_config; /* 0x84 */ + unsigned int pll1_config; /* 0x88 */ +}; + +#define VPTIO_RDY (1 << 15) +#define VPTIO_IOPWRDN (1 << 14) +#define VPTIO_CLRZ (1 << 13) +#define VPTIO_LOCK (1 << 7) +#define VPTIO_PWRDN (1 << 6) + +#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7) + +#define dv_sys_module_regs \ + ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE) + +#endif /* !CONFIG_SOC_DA8XX */ +#endif /* _DV_SYSCFG_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index f17f82d3f4..d1c199825f 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -41,7 +41,8 @@ #include <asm/arch/kirkwood.h> #define CONFIG_ARM926EJS 1 /* Basic Architecture */ - +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* default Dcache Line length for kirkwood */ #define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 2e3bce2c31..253a0e1584 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -37,8 +37,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk); extern u32 imx_get_uartclk(void); extern void mx31_gpio_mux(unsigned long mode); extern void mx31_set_pad(enum iomux_pins pin, u32 config); +extern void mx31_set_gpr(enum iomux_gp_func gp, char en); void mx31_uart1_hw_init(void); +void mx31_uart2_hw_init(void); void mx31_spi2_hw_init(void); void mxc_hw_watchdog_enable(void); void mxc_hw_watchdog_reset(void); diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 552c8214e4..afdaa1ce6c 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -468,6 +468,44 @@ enum iomux_pins { MX31_PIN_CAPTURE = IOMUX_PIN(7, 327), }; +/* + * various IOMUX general purpose functions + */ +enum iomux_gp_func { + MUX_PGP_FIRI = 1 << 0, + MUX_DDR_MODE = 1 << 1, + MUX_PGP_CSPI_BB = 1 << 2, + MUX_PGP_ATA_1 = 1 << 3, + MUX_PGP_ATA_2 = 1 << 4, + MUX_PGP_ATA_3 = 1 << 5, + MUX_PGP_ATA_4 = 1 << 6, + MUX_PGP_ATA_5 = 1 << 7, + MUX_PGP_ATA_6 = 1 << 8, + MUX_PGP_ATA_7 = 1 << 9, + MUX_PGP_ATA_8 = 1 << 10, + MUX_PGP_UH2 = 1 << 11, + MUX_SDCTL_CSD0_SEL = 1 << 12, + MUX_SDCTL_CSD1_SEL = 1 << 13, + MUX_CSPI1_UART3 = 1 << 14, + MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, + MUX_TAMPER_DETECT_EN = 1 << 16, + MUX_PGP_USB_4WIRE = 1 << 17, + MUX_PGP_USB_COMMON = 1 << 18, + MUX_SDHC_MEMSTICK1 = 1 << 19, + MUX_SDHC_MEMSTICK2 = 1 << 20, + MUX_PGP_SPLL_BYP = 1 << 21, + MUX_PGP_UPLL_BYP = 1 << 22, + MUX_PGP_MSHC1_CLK_SEL = 1 << 23, + MUX_PGP_MSHC2_CLK_SEL = 1 << 24, + MUX_CSPI3_UART5_SEL = 1 << 25, + MUX_PGP_ATA_9 = 1 << 26, + MUX_PGP_USB_SUSPEND = 1 << 27, + MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, + MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, + MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, + MUX_CLKO_DDR_MODE = 1 << 31, +}; + /* Bit definitions for RCSR register in CCM */ #define CCM_RCSR_NF16B (1 << 31) #define CCM_RCSR_NFMS (1 << 30) @@ -484,6 +522,17 @@ struct mx31_weim { struct mx31_weim_cscr cscr[6]; }; +/* ESD control registers */ +struct esdc_regs { + u32 ctl0; + u32 cfg0; + u32 ctl1; + u32 cfg1; + u32 misc; + u32 dly[5]; + u32 dlyl; +}; + #endif #define __REG(x) (*((volatile u32 *)(x))) @@ -562,6 +611,8 @@ struct mx31_weim { #define ESDCTL_BL(x) ((x) << 7) #define ESDCTL_PRCT(x) ((x) << 0) +#define ESDCTL_BASE_ADDR 0xB8001000 + /* 13 fields of the upper CS control register */ #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ cnc, wsc, ew, wws, edc) \ @@ -642,12 +693,23 @@ struct mx31_weim { /* Register offsets based on IOMUXC_BASE */ /* 0x00 .. 0x7b */ +#define MUX_CTL_CSPI3_MISO 0x0c +#define MUX_CTL_CSPI3_SCLK 0x0d +#define MUX_CTL_CSPI3_SPI_RDY 0x0e +#define MUX_CTL_CSPI3_MOSI 0x13 + #define MUX_CTL_USBH2_DATA1 0x40 #define MUX_CTL_USBH2_DIR 0x44 #define MUX_CTL_USBH2_STP 0x45 #define MUX_CTL_USBH2_NXT 0x46 #define MUX_CTL_USBH2_DATA0 0x47 #define MUX_CTL_USBH2_CLK 0x4B + +#define MUX_CTL_TXD2 0x70 +#define MUX_CTL_RTS2 0x71 +#define MUX_CTL_CTS2 0x72 +#define MUX_CTL_RXD2 0x77 + #define MUX_CTL_RTS1 0x7c #define MUX_CTL_CTS1 0x7d #define MUX_CTL_DTR_DCE1 0x7e @@ -705,6 +767,11 @@ struct mx31_weim { #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) +#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC) +#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC) +#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC) +#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC) + #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index 0c566f27c2..25c324eb36 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -147,6 +147,19 @@ #define PLL_MFI(x) (((x) & 0xf) << 10) #define PLL_MFN(x) (((x) & 0x3ff) << 0) +#define _PLL_BRM(x) ((x) << 31) +#define _PLL_PD(x) (((x) - 1) << 26) +#define _PLL_MFD(x) (((x) - 1) << 16) +#define _PLL_MFI(x) ((x) << 10) +#define _PLL_MFN(x) (x) +#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ + (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ + _PLL_MFN(mfn)) + +#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) +#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) +#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) + #define CSCR_U(x) (WEIM_CTRL_CS#x + 0) #define CSCR_L(x) (WEIM_CTRL_CS#x + 4) #define CSCR_A(x) (WEIM_CTRL_CS#x + 8) @@ -284,6 +297,23 @@ struct wdog_regs { u16 wmcr; /* Misc Control */ }; +struct esdc_regs { + u32 esdctl0; + u32 esdcfg0; + u32 esdctl1; + u32 esdcfg1; + u32 esdmisc; + u32 reserved[4]; + u32 esdcdly[5]; + u32 esdcdlyl; +}; + +#define ESDC_MISC_RST (1 << 1) +#define ESDC_MISC_MDDR_EN (1 << 2) +#define ESDC_MISC_MDDR_DL_RST (1 << 3) +#define ESDC_MISC_DDR_EN (1 << 8) +#define ESDC_MISC_DDR2_EN (1 << 9) + /* * NFMS bit in RCSR register for pagesize of nandflash */ @@ -293,9 +323,5 @@ struct wdog_regs { #define CCM_RCSR_NF_16BIT_SEL (1 << 14) -extern unsigned int get_board_rev(void); -extern int is_soc_rev(int rev); -extern int sdhc_init(void); - #endif #endif /* __ASM_ARCH_MX35_H */ diff --git a/arch/arm/include/asm/arch-mx35/lowlevel_macro.S b/arch/arm/include/asm/arch-mx35/lowlevel_macro.S new file mode 100644 index 0000000000..05aa951d10 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/lowlevel_macro.S @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * AIPS setup - Only setup MPROTx registers. + * The PACR default values are good. + */ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_MPR_CONFIG + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_OPACR_CONFIG + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + str r1, [r0, #0x50] +.endm + +/* MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max + ldr r0, =MAX_BASE_ADDR + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, =MAX_MPR_CONFIG + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =MAX_SGPCR_CONFIG + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =MAX_MGPCR_CONFIG + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +.endm + +/* M3IF setup */ +.macro init_m3if + /* Configure M3IF registers */ + ldr r1, =M3IF_BASE_ADDR + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + ldr r0, =M3IF_CONFIG + str r0, [r1] /* M3IF control reg */ +.endm + +.macro core_init + mrc 15, 0, r1, c1, c0, 0 + + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #7 + mcr 15, 0, r0, c1, c0, 1 + orr r1, r1, #(1<<11) + + /* Set unaligned access enable */ + orr r1, r1, #(1<<22) + + /* Set low int latency enable */ + orr r1, r1, #(1<<21) + + mcr 15, 0, r1, c1, c0, 0 + + mov r0, #0 + + /* Set branch prediction enable */ + mcr 15, 0, r0, c15, c2, 4 + + mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ + mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + + /* + * initializes very early AIPS + * Then it also initializes Multi-Layer AHB Crossbar Switch, + * M3IF + * Also setup the Peripheral Port Remap register inside the core + */ + ldr r0, =0x40000015 /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 +.endm diff --git a/arch/arm/include/asm/arch-mx35/mx35_pins.h b/arch/arm/include/asm/arch-mx35/mx35_pins.h index 14669ffe6a..3676e330bd 100644 --- a/arch/arm/include/asm/arch-mx35/mx35_pins.h +++ b/arch/arm/include/asm/arch-mx35/mx35_pins.h @@ -349,6 +349,9 @@ typedef enum iomux_pins { MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780), MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784), MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788), + + MX35_PIN_RTS2_UART3_RXD_MUX = _MXC_BUILD_NON_GPIO_PIN(0x1a0, 0x5e4), + MX35_PIN_CTS2_UART3_TXD_MUX = _MXC_BUILD_NON_GPIO_PIN(0x1a4, 0x5e8), } iomux_pin_name_t; #endif diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 8e28f775df..db6a696f49 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -54,79 +54,89 @@ enum { #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) -/* Infineon part of 3430SDP (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 72/6 = 12 - * ACTIMB - * TCKE = 2 - * XSR = 120/6 = 20 - */ -#define INFINEON_TDAL_165 6 -#define INFINEON_TDPL_165 3 -#define INFINEON_TRRD_165 2 -#define INFINEON_TRCD_165 3 -#define INFINEON_TRP_165 3 -#define INFINEON_TRAS_165 7 -#define INFINEON_TRC_165 10 -#define INFINEON_TRFC_165 12 -#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \ - (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \ - (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \ - (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \ - (INFINEON_TDAL_165)) +/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */ +#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ +#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ +#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ +#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ +#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ +#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ +#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ +#define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ + +#define ACTIM_CTRLA(a,b,c,d,e,f,g,h) \ + ACTIM_CTRLA_TRFC(a) | \ + ACTIM_CTRLA_TRC(b) | \ + ACTIM_CTRLA_TRAS(b) | \ + ACTIM_CTRLA_TRP(d) | \ + ACTIM_CTRLA_TRCD(e) | \ + ACTIM_CTRLA_TRRD(f) | \ + ACTIM_CTRLA_TDPL(g) | \ + ACTIM_CTRLA_TDAL(h) + +/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */ +#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ +#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ +#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */ +#define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */ + +#define ACTIM_CTRLB(a,b,c,d) \ + ACTIM_CTRLB_TWTR(a) | \ + ACTIM_CTRLB_TCKE(b) | \ + ACTIM_CTRLB_TXP(b) | \ + ACTIM_CTRLB_TXSR(d) + +/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ +#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ + /* 15/6 + 18/6 = 5.5 -> 6 */ +#define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ +#define INFINEON_TRRD_165 2 /* 12/6 = 2 */ +#define INFINEON_TRCD_165 3 /* 18/6 = 3 */ +#define INFINEON_TRP_165 3 /* 18/6 = 3 */ +#define INFINEON_TRAS_165 7 /* 42/6 = 7 */ +#define INFINEON_TRC_165 10 /* 60/6 = 10 */ +#define INFINEON_TRFC_165 12 /* 72/6 = 12 */ + +#define INFINEON_V_ACTIMA_165 \ + ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \ + INFINEON_TRAS_165, INFINEON_TRP_165, \ + INFINEON_TRCD_165, INFINEON_TRRD_165, \ + INFINEON_TDPL_165, INFINEON_TDAL_165) #define INFINEON_TWTR_165 1 #define INFINEON_TCKE_165 2 #define INFINEON_TXP_165 2 -#define INFINEON_XSR_165 20 -#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \ - (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \ - (INFINEON_TWTR_165 << 16)) - -/* Micron part of 3430 EVM (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 125/6 = 21 - * ACTIMB - * TWTR = 1 - * TCKE = 1 - * TXSR = 138/6 = 23 - * TXP = 25/6 = 4.1 ~5 - */ -#define MICRON_TDAL_165 6 -#define MICRON_TDPL_165 3 -#define MICRON_TRRD_165 2 -#define MICRON_TRCD_165 3 -#define MICRON_TRP_165 3 -#define MICRON_TRAS_165 7 -#define MICRON_TRC_165 10 -#define MICRON_TRFC_165 21 -#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \ - (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \ - (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \ - (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \ - (MICRON_TDAL_165)) +#define INFINEON_XSR_165 20 /* 120/6 = 20 */ + +#define INFINEON_V_ACTIMB_165 \ + ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \ + INFINEON_TXP_165, INFINEON_XSR_165) + +/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */ +#define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */ + /* 15/6 + 18/6 = 5.5 -> 6 */ +#define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ +#define MICRON_TRRD_165 2 /* 12/6 = 2 */ +#define MICRON_TRCD_165 3 /* 18/6 = 3 */ +#define MICRON_TRP_165 3 /* 18/6 = 3 */ +#define MICRON_TRAS_165 7 /* 42/6 = 7 */ +#define MICRON_TRC_165 10 /* 60/6 = 10 */ +#define MICRON_TRFC_165 21 /* 125/6 = 21 */ + +#define MICRON_V_ACTIMA_165 \ + ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \ + MICRON_TRAS_165, MICRON_TRP_165, \ + MICRON_TRCD_165, MICRON_TRRD_165, \ + MICRON_TDPL_165, MICRON_TDAL_165) #define MICRON_TWTR_165 1 #define MICRON_TCKE_165 1 -#define MICRON_XSR_165 23 -#define MICRON_TXP_165 5 -#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \ - (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \ - (MICRON_TWTR_165 << 16)) +#define MICRON_XSR_165 23 /* 138/6 = 23 */ +#define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */ + +#define MICRON_V_ACTIMB_165 \ + ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ + MICRON_TXP_165, MICRON_XSR_165) #define MICRON_RAMTYPE 0x1 #define MICRON_DDRTYPE 0x0 @@ -155,61 +165,48 @@ enum { #define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ (MICRON_SIL << 3) | (MICRON_BL)) -/* - * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 22.5/6 = 3.75 -> 4 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 140/6 = 23.3 -> 24 - * ACTIMB - * TWTR = 2 - * TCKE = 2 - * TXSR = 200/6 = 33.3 -> 34 - * TXP = 1.0 + 1.1 = 2.1 -> 3 - */ -#define NUMONYX_TDAL_165 6 -#define NUMONYX_TDPL_165 3 -#define NUMONYX_TRRD_165 2 -#define NUMONYX_TRCD_165 4 -#define NUMONYX_TRP_165 3 -#define NUMONYX_TRAS_165 7 -#define NUMONYX_TRC_165 10 -#define NUMONYX_TRFC_165 24 -#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \ - (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \ - (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \ - (NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \ - (NUMONYX_TDAL_165)) - -#define NUMONYX_TWTR_165 2 -#define NUMONYX_TCKE_165 2 -#define NUMONYX_TXP_165 3 -#define NUMONYX_XSR_165 34 -#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \ - (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \ - (NUMONYX_TWTR_165 << 16)) +/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ +#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ + /* 15/6 + 18/6 = 5.5 -> 6 */ +#define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ +#define NUMONYX_TRRD_165 2 /* 12/6 = 2 */ +#define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */ +#define NUMONYX_TRP_165 3 /* 18/6 = 3 */ +#define NUMONYX_TRAS_165 7 /* 42/6 = 7 */ +#define NUMONYX_TRC_165 10 /* 60/6 = 10 */ +#define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */ + +#define NUMONYX_V_ACTIMA_165 \ + ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \ + NUMONYX_TRAS_165, NUMONYX_TRP_165, \ + NUMONYX_TRCD_165, NUMONYX_TRRD_165, \ + NUMONYX_TDPL_165, NUMONYX_TDAL_165) + +#define NUMONYX_TWTR_165 2 +#define NUMONYX_TCKE_165 2 +#define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */ +#define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */ + +#define NUMONYX_V_ACTIMB_165 \ + ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ + NUMONYX_TXP_165, NUMONYX_XSR_165) #ifdef CONFIG_OMAP3_INFINEON_DDR -#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 -#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 +#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 +#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 #endif #ifdef CONFIG_OMAP3_MICRON_DDR -#define V_ACTIMA_165 MICRON_V_ACTIMA_165 -#define V_ACTIMB_165 MICRON_V_ACTIMB_165 +#define V_ACTIMA_165 MICRON_V_ACTIMA_165 +#define V_ACTIMB_165 MICRON_V_ACTIMB_165 #define V_MCFG MICRON_V_MCFG #define V_RFR_CTRL MICRON_V_RFR_CTRL #define V_MR MICRON_V_MR #endif #ifdef CONFIG_OMAP3_NUMONYX_DDR -#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 -#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 +#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 +#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 #endif #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h index d10583dec4..e4fce7da92 100644 --- a/arch/arm/include/asm/arch-pantheon/config.h +++ b/arch/arm/include/asm/arch-pantheon/config.h @@ -28,6 +28,8 @@ #include <asm/arch/pantheon.h> #define CONFIG_ARM926EJS 1 /* Basic Architecture */ +/* default Dcache Line length for pantheon */ +#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ #define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ diff --git a/arch/powerpc/cpu/mpc5xxx/i2c.c b/arch/powerpc/cpu/mpc5xxx/i2c.c index f9d293b7ce..b423d2fe34 100644 --- a/arch/powerpc/cpu/mpc5xxx/i2c.c +++ b/arch/powerpc/cpu/mpc5xxx/i2c.c @@ -100,14 +100,11 @@ static int wait_for_bb(void) status = mpc_reg_in(®s->msr); while (timeout-- && (status & I2C_BB)) { -#if 1 - volatile int temp; mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); - temp = mpc_reg_in(®s->mdr); + (void)mpc_reg_in(®s->mdr); mpc_reg_out(®s->mcr, 0, I2C_STA); mpc_reg_out(®s->mcr, 0, 0); mpc_reg_out(®s->mcr, I2C_EN, 0); -#endif udelay(15); status = mpc_reg_in(®s->msr); } diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c index 2fc1180b78..d250c199f8 100644 --- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c +++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c @@ -748,10 +748,9 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf static void dl_transfer_length(td_t * td) { - __u32 tdINFO, tdBE, tdCBP; + __u32 tdBE, tdCBP; urb_priv_t *lurb_priv = &urb_priv; - tdINFO = ohci_cpu_to_le32 (td->hwINFO); tdBE = ohci_cpu_to_le32 (td->hwBE); tdCBP = ohci_cpu_to_le32 (td->hwCBP); diff --git a/arch/powerpc/cpu/mpc8220/fec.c b/arch/powerpc/cpu/mpc8220/fec.c index bcda8a2b27..2053fea571 100644 --- a/arch/powerpc/cpu/mpc8220/fec.c +++ b/arch/powerpc/cpu/mpc8220/fec.c @@ -772,8 +772,8 @@ static int mpc8220_fec_recv (struct eth_device *dev) frame = (NBUF *) pRbd->dataPointer; frame_length = pRbd->dataLength - 4; -#if (0) - { + /* DEBUG code */ + if (_DEBUG) { int i; printf ("recv data hdr:"); @@ -781,7 +781,7 @@ static int mpc8220_fec_recv (struct eth_device *dev) printf ("%x ", *(frame->head + i)); printf ("\n"); } -#endif + /* * Fill the buffer and pass it to upper layers */ diff --git a/arch/powerpc/cpu/mpc8220/i2c.c b/arch/powerpc/cpu/mpc8220/i2c.c index 76ecdf11e2..2f35d20c87 100644 --- a/arch/powerpc/cpu/mpc8220/i2c.c +++ b/arch/powerpc/cpu/mpc8220/i2c.c @@ -105,15 +105,13 @@ static int wait_for_bb (void) status = mpc_reg_in (®s->sr); while (timeout-- && (status & I2C_BB)) { -#if 1 - volatile int temp; mpc_reg_out (®s->cr, I2C_STA, I2C_STA); - temp = mpc_reg_in (®s->dr); + (void)mpc_reg_in (®s->dr); mpc_reg_out (®s->cr, 0, I2C_STA); mpc_reg_out (®s->cr, 0, 0); mpc_reg_out (®s->cr, I2C_EN, 0); -#endif + udelay (1000); status = mpc_reg_in (®s->sr); } diff --git a/arch/powerpc/cpu/mpc8260/i2c.c b/arch/powerpc/cpu/mpc8260/i2c.c index d2bdcc2d82..7382cbadc7 100644 --- a/arch/powerpc/cpu/mpc8260/i2c.c +++ b/arch/powerpc/cpu/mpc8260/i2c.c @@ -31,13 +31,10 @@ #include <asm/cpm_8260.h> #include <i2c.h> -/* define to enable debug messages */ -#undef DEBUG_I2C - DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_I2C_MULTI_BUS) -static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0; +static unsigned int i2c_bus_num __attribute__ ((section(".data"))) = 0; #endif /* CONFIG_I2C_MULTI_BUS */ /* uSec to wait between polls of the i2c */ @@ -51,52 +48,50 @@ static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0; */ #define TOUT_LOOP 5 -/*----------------------------------------------------------------------- +/* * Set default values */ #ifndef CONFIG_SYS_I2C_SPEED #define CONFIG_SYS_I2C_SPEED 50000 #endif -/*----------------------------------------------------------------------- - */ -typedef void (*i2c_ecb_t)(int, int, void *); /* error callback function */ +typedef void (*i2c_ecb_t) (int, int, void *); /* error callback function */ /* This structure keeps track of the bd and buffer space usage. */ typedef struct i2c_state { - int rx_idx; /* index to next free Rx BD */ - int tx_idx; /* index to next free Tx BD */ - void *rxbd; /* pointer to next free Rx BD */ - void *txbd; /* pointer to next free Tx BD */ - int tx_space; /* number of Tx bytes left */ - unsigned char *tx_buf; /* pointer to free Tx area */ - i2c_ecb_t err_cb; /* error callback function */ - void *cb_data; /* private data to be passed */ + int rx_idx; /* index to next free Rx BD */ + int tx_idx; /* index to next free Tx BD */ + void *rxbd; /* pointer to next free Rx BD */ + void *txbd; /* pointer to next free Tx BD */ + int tx_space; /* number of Tx bytes left */ + unsigned char *tx_buf; /* pointer to free Tx area */ + i2c_ecb_t err_cb; /* error callback function */ + void *cb_data; /* private data to be passed */ } i2c_state_t; /* flags for i2c_send() and i2c_receive() */ -#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */ -#define I2CF_START_COND 0x02 /* tx: generate start condition */ -#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */ +#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */ +#define I2CF_START_COND 0x02 /* tx: generate start condition */ +#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */ /* return codes */ -#define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */ -#define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */ -#define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */ -#define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/receive */ -#define I2CERR_IO_ERROR 5 /* had an error during comms */ +#define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */ +#define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */ +#define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */ +#define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/rcv */ +#define I2CERR_IO_ERROR 5 /* had an error during comms */ /* error callback flags */ -#define I2CECB_RX_ERR 0x10 /* this is a receive error */ -#define I2CECB_RX_OV 0x02 /* receive overrun error */ -#define I2CECB_RX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TX_ERR 0x20 /* this is a transmit error */ -#define I2CECB_TX_CL 0x01 /* transmit collision error */ -#define I2CECB_TX_UN 0x02 /* transmit underflow error */ -#define I2CECB_TX_NAK 0x04 /* transmit no ack error */ -#define I2CECB_TX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */ +#define I2CECB_RX_ERR 0x10 /* this is a receive error */ +#define I2CECB_RX_OV 0x02 /* receive overrun error */ +#define I2CECB_RX_MASK 0x0f /* mask for error bits */ +#define I2CECB_TX_ERR 0x20 /* this is a transmit error */ +#define I2CECB_TX_CL 0x01 /* transmit collision error */ +#define I2CECB_TX_UN 0x02 /* transmit underflow error */ +#define I2CECB_TX_NAK 0x04 /* transmit no ack error */ +#define I2CECB_TX_MASK 0x0f /* mask for error bits */ +#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */ #define ERROR_I2C_NONE 0 #define ERROR_I2C_LENGTH 1 @@ -111,13 +106,13 @@ typedef struct i2c_state { #define NUM_TX_BDS 4 #define MAX_TX_SPACE 256 -typedef struct I2C_BD -{ - unsigned short status; - unsigned short length; - unsigned char *addr; +typedef struct I2C_BD { + unsigned short status; + unsigned short length; + unsigned char *addr; } I2C_BD; -#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */ + +#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */ #define BD_I2C_TX_CL 0x0001 /* collision error */ #define BD_I2C_TX_UN 0x0002 /* underflow error */ @@ -126,12 +121,6 @@ typedef struct I2C_BD #define BD_I2C_RX_ERR BD_SC_OV -#ifdef DEBUG_I2C -#define PRINTD(x) printf x -#else -#define PRINTD(x) -#endif - /* * Returns the best value of I2BRG to meet desired clock speed of I2C with * input parameters (clock speed, filter, and predivider value). @@ -140,32 +129,32 @@ typedef struct I2C_BD */ static inline int i2c_roundrate(int hz, int speed, int filter, int modval, - int *brgval, int *totspeed) + int *brgval, int *totspeed) { - int moddiv = 1 << (5-(modval & 3)), brgdiv, div; + int moddiv = 1 << (5 - (modval & 3)), brgdiv, div; - PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n", - hz, speed, filter, modval)); + debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n", + hz, speed, filter, modval); - div = moddiv * speed; - brgdiv = (hz + div - 1) / div; + div = moddiv * speed; + brgdiv = (hz + div - 1) / div; - PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv)); + debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv); - *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter); + *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter); - if ((*brgval < 0) || (*brgval > 255)) { - PRINTD(("\t\trejected brgval=%d\n", *brgval)); - return -1; - } + if ((*brgval < 0) || (*brgval > 255)) { + debug("\t\trejected brgval=%d\n", *brgval); + return -1; + } - brgdiv = 2 * (*brgval + 3 + (2 * filter)); - div = moddiv * brgdiv ; - *totspeed = hz / div; + brgdiv = 2 * (*brgval + 3 + (2 * filter)); + div = moddiv * brgdiv; + *totspeed = hz / div; - PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed)); + debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed); - return 0; + return 0; } /* @@ -173,84 +162,87 @@ i2c_roundrate(int hz, int speed, int filter, int modval, */ static int i2c_setrate(int hz, int speed) { - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; - volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; - int brgval, - modval, /* 0-3 */ - bestspeed_diff = speed, - bestspeed_brgval=0, - bestspeed_modval=0, - bestspeed_filter=0, - totspeed, - filter = 0; /* Use this fixed value */ - - for (modval = 0; modval < 4; modval++) - { - if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0) - { - int diff = speed - totspeed ; - - if ((diff >= 0) && (diff < bestspeed_diff)) - { - bestspeed_diff = diff ; - bestspeed_modval = modval; - bestspeed_brgval = brgval; - bestspeed_filter = filter; + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; + int brgval, + modval, /* 0-3 */ + bestspeed_diff = speed, + bestspeed_brgval = 0, + bestspeed_modval = 0, + bestspeed_filter = 0, + totspeed, + filter = 0; /* Use this fixed value */ + + for (modval = 0; modval < 4; modval++) { + if (i2c_roundrate(hz, speed, filter, modval, &brgval, &totspeed) + == 0) { + int diff = speed - totspeed; + + if ((diff >= 0) && (diff < bestspeed_diff)) { + bestspeed_diff = diff; + bestspeed_modval = modval; + bestspeed_brgval = brgval; + bestspeed_filter = filter; } } } - PRINTD(("[I2C] Best is:\n")); - PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", - hz, speed, - bestspeed_filter, bestspeed_modval, bestspeed_brgval, - bestspeed_diff)); + debug("[I2C] Best is:\n"); + debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", + hz, speed, bestspeed_filter, bestspeed_modval, bestspeed_brgval, + bestspeed_diff); - i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3); - i2c->i2c_i2brg = bestspeed_brgval & 0xff; + i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | + (bestspeed_filter << 3); + i2c->i2c_i2brg = bestspeed_brgval & 0xff; - PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg)); + debug("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, + i2c->i2c_i2brg); - return 1 ; + return 1; } void i2c_init(int speed, int slaveadd) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm; - volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; + volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; volatile iic_t *iip; ulong rbase, tbase; volatile I2C_BD *rxbd, *txbd; uint dpaddr; #ifdef CONFIG_SYS_I2C_INIT_BOARD - /* call board specific i2c bus reset routine before accessing the */ - /* environment, which might be in a chip on that bus. For details */ - /* about this problem see doc/I2C_Edge_Conditions. */ + /* + * call board specific i2c bus reset routine before accessing the + * environment, which might be in a chip on that bus. For details + * about this problem see doc/I2C_Edge_Conditions. + */ i2c_init_board(); #endif - dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])); + dpaddr = *((unsigned short *) (&immap->im_dprambase[PROFF_I2C_BASE])); if (dpaddr == 0) { - /* need to allocate dual port ram */ - dpaddr = m8260_cpm_dpalloc(64 + - (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) + - MAX_TX_SPACE, 64); - *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = dpaddr; + /* need to allocate dual port ram */ + dpaddr = m8260_cpm_dpalloc(64 + + (NUM_RX_BDS * sizeof(I2C_BD)) + + (NUM_TX_BDS * sizeof(I2C_BD)) + + MAX_TX_SPACE, 64); + *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE])) = + dpaddr; } /* * initialise data in dual port ram: * - * dpaddr -> parameter ram (64 bytes) + * dpaddr -> parameter ram (64 bytes) * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes) * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes) * tx buffer (MAX_TX_SPACE bytes) */ iip = (iic_t *)&immap->im_dprambase[dpaddr]; - memset((void*)iip, 0, sizeof(iic_t)); + memset((void *)iip, 0, sizeof(iic_t)); rbase = dpaddr + 64; tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD); @@ -266,8 +258,8 @@ void i2c_init(int speed, int slaveadd) * and current CPU rate (we assume sccr dfbgr field is 0; * divide BRGCLK by 1) */ - PRINTD(("[I2C] Setting rate...\n")); - i2c_setrate (gd->brg_clk, CONFIG_SYS_I2C_SPEED) ; + debug("[I2C] Setting rate...\n"); + i2c_setrate(gd->brg_clk, CONFIG_SYS_I2C_SPEED); /* Set I2C controller in master mode */ i2c->i2c_i2com = 0x01; @@ -275,13 +267,15 @@ void i2c_init(int speed, int slaveadd) /* Initialize Tx/Rx parameters */ iip->iic_rbase = rbase; iip->iic_tbase = tbase; - rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]); - txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]); + rxbd = (I2C_BD *)((unsigned char *) &immap-> + im_dprambase[iip->iic_rbase]); + txbd = (I2C_BD *)((unsigned char *) &immap-> + im_dprambase[iip->iic_tbase]); - PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase)); - PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase)); - PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + debug("[I2C] rbase = %04x\n", iip->iic_rbase); + debug("[I2C] tbase = %04x\n", iip->iic_tbase); + debug("[I2C] rxbd = %08x\n", (int) rxbd); + debug("[I2C] txbd = %08x\n", (int) txbd); /* Set big endian byte order */ iip->iic_tfcr = 0x10; @@ -290,13 +284,12 @@ void i2c_init(int speed, int slaveadd) /* Set maximum receive size. */ iip->iic_mrblr = I2C_RXTX_LEN; - cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE, - CPM_CR_I2C_SBLOCK, - 0x00, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); + cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE, + CPM_CR_I2C_SBLOCK, + 0x00, CPM_CR_INIT_TRX) | CPM_CR_FLG; + do { + __asm__ __volatile__("eieio"); + } while (cp->cp_cpcr & CPM_CR_FLG); /* Clear events and interrupts */ i2c->i2c_i2cer = 0xff; @@ -306,147 +299,136 @@ void i2c_init(int speed, int slaveadd) static void i2c_newio(i2c_state_t *state) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile iic_t *iip; uint dpaddr; - PRINTD(("[I2C] i2c_newio\n")); + debug("[I2C] i2c_newio\n"); - dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])); + dpaddr = *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE])); iip = (iic_t *)&immap->im_dprambase[dpaddr]; state->rx_idx = 0; state->tx_idx = 0; - state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase]; - state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase]; + state->rxbd = (void *)&immap->im_dprambase[iip->iic_rbase]; + state->txbd = (void *)&immap->im_dprambase[iip->iic_tbase]; state->tx_space = MAX_TX_SPACE; - state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD); + state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD); state->err_cb = NULL; state->cb_data = NULL; - PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd)); - PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf)); + debug("[I2C] rxbd = %08x\n", (int)state->rxbd); + debug("[I2C] txbd = %08x\n", (int)state->txbd); + debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf); /* clear the buffer memory */ - memset((char *)state->tx_buf, 0, MAX_TX_SPACE); + memset((char *) state->tx_buf, 0, MAX_TX_SPACE); } static int i2c_send(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, - unsigned short size, - unsigned char *dataout) + unsigned char address, + unsigned char secondary_address, + unsigned int flags, unsigned short size, unsigned char *dataout) { volatile I2C_BD *txbd; - int i,j; + int i, j; - PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n", - address, secondary_address, flags, size)); + debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n", + address, secondary_address, flags, size); /* trying to send message larger than BD */ if (size > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; + return I2CERR_MSG_TOO_LONG; /* no more free bds */ if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size)) - return I2CERR_NO_BUFFERS; + return I2CERR_NO_BUFFERS; txbd = (I2C_BD *)state->txbd; txbd->addr = state->tx_buf; - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); - - if (flags & I2CF_START_COND) - { - PRINTD(("[I2C] Formatting addresses...\n")); - if (flags & I2CF_ENABLE_SECONDARY) - { - txbd->length = size + 2; /* Length of message plus dest addresses */ - txbd->addr[0] = address << 1; - txbd->addr[1] = secondary_address; - i = 2; - } - else - { - txbd->length = size + 1; /* Length of message plus dest address */ - txbd->addr[0] = address << 1; /* Write destination address to BD */ - i = 1; + debug("[I2C] txbd = %08x\n", (int) txbd); + + if (flags & I2CF_START_COND) { + debug("[I2C] Formatting addresses...\n"); + if (flags & I2CF_ENABLE_SECONDARY) { + /* Length of message plus dest addresses */ + txbd->length = size + 2; + txbd->addr[0] = address << 1; + txbd->addr[1] = secondary_address; + i = 2; + } else { + /* Length of message plus dest address */ + txbd->length = size + 1; + /* Write destination address to BD */ + txbd->addr[0] = address << 1; + i = 1; + } + } else { + txbd->length = size; /* Length of message */ + i = 0; } - } - else - { - txbd->length = size; /* Length of message */ - i = 0; - } /* set up txbd */ txbd->status = BD_SC_READY; if (flags & I2CF_START_COND) - txbd->status |= BD_I2C_TX_START; + txbd->status |= BD_I2C_TX_START; if (flags & I2CF_STOP_COND) - txbd->status |= BD_SC_LAST | BD_SC_WRAP; + txbd->status |= BD_SC_LAST | BD_SC_WRAP; /* Copy data to send into buffer */ - PRINTD(("[I2C] copy data...\n")); - for(j = 0; j < size; i++, j++) - txbd->addr[i] = dataout[j]; + debug("[I2C] copy data...\n"); + for (j = 0; j < size; i++, j++) + txbd->addr[i] = dataout[j]; - PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, - txbd->status, - txbd->addr[0], - txbd->addr[1])); + debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]); /* advance state */ state->tx_buf += txbd->length; state->tx_space -= txbd->length; state->tx_idx++; - state->txbd = (void*)(txbd + 1); + state->txbd = (void *) (txbd + 1); return 0; } static int i2c_receive(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, - unsigned short size_to_expect, - unsigned char *datain) + unsigned char address, + unsigned char secondary_address, + unsigned int flags, + unsigned short size_to_expect, unsigned char *datain) { volatile I2C_BD *rxbd, *txbd; - PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags)); + debug("[I2C] i2c_receive %02d %02d %02d\n", address, + secondary_address, flags); /* Expected to receive too much */ if (size_to_expect > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; + return I2CERR_MSG_TOO_LONG; /* no more free bds */ if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS - || state->tx_space < 2) - return I2CERR_NO_BUFFERS; + || state->tx_space < 2) + return I2CERR_NO_BUFFERS; - rxbd = (I2C_BD *)state->rxbd; - txbd = (I2C_BD *)state->txbd; + rxbd = (I2C_BD *) state->rxbd; + txbd = (I2C_BD *) state->txbd; - PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + debug("[I2C] rxbd = %08x\n", (int) rxbd); + debug("[I2C] txbd = %08x\n", (int) txbd); txbd->addr = state->tx_buf; /* set up TXBD for destination address */ - if (flags & I2CF_ENABLE_SECONDARY) - { + if (flags & I2CF_ENABLE_SECONDARY) { txbd->length = 2; - txbd->addr[0] = address << 1; /* Write data */ - txbd->addr[1] = secondary_address; /* Internal address */ + txbd->addr[0] = address << 1; /* Write data */ + txbd->addr[1] = secondary_address; /* Internal address */ txbd->status = BD_SC_READY; - } - else - { + } else { txbd->length = 1 + size_to_expect; txbd->addr[0] = (address << 1) | 0x01; txbd->status = BD_SC_READY; @@ -459,30 +441,23 @@ int i2c_receive(i2c_state_t *state, rxbd->addr = datain; txbd->status |= BD_I2C_TX_START; - if (flags & I2CF_STOP_COND) - { + if (flags & I2CF_STOP_COND) { txbd->status |= BD_SC_LAST | BD_SC_WRAP; rxbd->status |= BD_SC_WRAP; } - PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, - txbd->status, - txbd->addr[0], - txbd->addr[1])); - PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - rxbd->length, - rxbd->status, - rxbd->addr[0], - rxbd->addr[1])); + debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]); + debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + rxbd->length, rxbd->status, rxbd->addr[0], rxbd->addr[1]); /* advance state */ state->tx_buf += txbd->length; state->tx_space -= txbd->length; state->tx_idx++; - state->txbd = (void*)(txbd + 1); + state->txbd = (void *) (txbd + 1); state->rx_idx++; - state->rxbd = (void*)(rxbd + 1); + state->rxbd = (void *) (rxbd + 1); return 0; } @@ -491,27 +466,27 @@ int i2c_receive(i2c_state_t *state, static int i2c_doio(i2c_state_t *state) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile iic_t *iip; - volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; + volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; volatile I2C_BD *txbd, *rxbd; - int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0; + int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0; uint dpaddr; - PRINTD(("[I2C] i2c_doio\n")); + debug("[I2C] i2c_doio\n"); if (state->tx_idx <= 0 && state->rx_idx <= 0) { - PRINTD(("[I2C] No I/O is queued\n")); + debug("[I2C] No I/O is queued\n"); return I2CERR_QUEUE_EMPTY; } - dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])); + dpaddr = *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE])); iip = (iic_t *)&immap->im_dprambase[dpaddr]; iip->iic_rbptr = iip->iic_rbase; iip->iic_tbptr = iip->iic_tbase; /* Enable I2C */ - PRINTD(("[I2C] Enabling I2C...\n")); + debug("[I2C] Enabling I2C...\n"); i2c->i2c_i2mod |= 0x01; /* Begin transmission */ @@ -519,90 +494,100 @@ int i2c_doio(i2c_state_t *state) /* Loop until transmit & receive completed */ - if ((n = state->tx_idx) > 0) { + n = state->tx_idx; + + if (n > 0) { - txbd = ((I2C_BD*)state->txbd) - n; + txbd = ((I2C_BD *) state->txbd) - n; for (i = 0; i < n; i++) { txtimeo += TOUT_LOOP * txbd->length; txbd++; } - txbd--; /* wait until last in list is done */ + txbd--; /* wait until last in list is done */ - PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd)); + debug("[I2C] Transmitting...(txbd=0x%08lx)\n", + (ulong) txbd); udelay(START_DELAY_US); /* give it time to start */ - while((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) { + while ((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) { udelay(DELAY_US); if (ctrlc()) - return (-1); - __asm__ __volatile__ ("eieio"); + return -1; + __asm__ __volatile__("eieio"); } } - if (txcnt < txtimeo && (n = state->rx_idx) > 0) { + n = state->rx_idx; - rxbd = ((I2C_BD*)state->rxbd) - n; + if (txcnt < txtimeo && n > 0) { + + rxbd = ((I2C_BD *) state->rxbd) - n; for (i = 0; i < n; i++) { rxtimeo += TOUT_LOOP * rxbd->length; rxbd++; } - rxbd--; /* wait until last in list is done */ + rxbd--; /* wait until last in list is done */ - PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd)); + debug("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong) rxbd); udelay(START_DELAY_US); /* give it time to start */ - while((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) { + while ((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) { udelay(DELAY_US); if (ctrlc()) - return (-1); - __asm__ __volatile__ ("eieio"); + return -1; + __asm__ __volatile__("eieio"); } } /* Turn off I2C */ i2c->i2c_i2mod &= ~0x01; - if ((n = state->tx_idx) > 0) { + n = state->tx_idx; + + if (n > 0) { for (i = 0; i < n; i++) { - txbd = ((I2C_BD*)state->txbd) - (n - i); - if ((b = txbd->status & BD_I2C_TX_ERR) != 0) { + txbd = ((I2C_BD *) state->txbd) - (n - i); + b = txbd->status & BD_I2C_TX_ERR; + if (b != 0) { if (state->err_cb != NULL) - (*state->err_cb)(I2CECB_TX_ERR|b, i, - state->cb_data); + (*state->err_cb) (I2CECB_TX_ERR | b, + i, state->cb_data); if (rc == 0) rc = I2CERR_IO_ERROR; } } } - if ((n = state->rx_idx) > 0) { + n = state->rx_idx; + + if (n > 0) { for (i = 0; i < n; i++) { - rxbd = ((I2C_BD*)state->rxbd) - (n - i); - if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) { + rxbd = ((I2C_BD *) state->rxbd) - (n - i); + b = rxbd->status & BD_I2C_RX_ERR; + if (b != 0) { if (state->err_cb != NULL) - (*state->err_cb)(I2CECB_RX_ERR|b, i, - state->cb_data); + (*state->err_cb) (I2CECB_RX_ERR | b, + i, state->cb_data); if (rc == 0) rc = I2CERR_IO_ERROR; } } } - if ((txtimeo > 0 && txcnt >= txtimeo) || \ + if ((txtimeo > 0 && txcnt >= txtimeo) || (rxtimeo > 0 && rxcnt >= rxtimeo)) { if (state->err_cb != NULL) - (*state->err_cb)(I2CECB_TIMEOUT, -1, state->cb_data); + (*state->err_cb) (I2CECB_TIMEOUT, -1, state->cb_data); if (rc == 0) rc = I2CERR_TIMEOUT; } - return (rc); + return rc; } -static void -i2c_probe_callback(int flags, int xnum, void *data) +static void i2c_probe_callback(int flags, int xnum, void *data) { /* * the only acceptable errors are a transmit NAK or a receive @@ -610,14 +595,13 @@ i2c_probe_callback(int flags, int xnum, void *data) * means the device must have responded to the slave address * even though the transfer failed */ - if (flags == (I2CECB_TX_ERR|I2CECB_TX_NAK)) - *(int *)data |= 1; - if (flags == (I2CECB_RX_ERR|I2CECB_RX_OV)) - *(int *)data |= 2; + if (flags == (I2CECB_TX_ERR | I2CECB_TX_NAK)) + *(int *) data |= 1; + if (flags == (I2CECB_RX_ERR | I2CECB_RX_OV)) + *(int *) data |= 2; } -int -i2c_probe(uchar chip) +int i2c_probe(uchar chip) { i2c_state_t state; int rc, err_flag; @@ -629,31 +613,31 @@ i2c_probe(uchar chip) state.cb_data = (void *) &err_flag; err_flag = 0; - rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf); + rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1, + buf); if (rc != 0) - return (rc); /* probe failed */ + return rc; /* probe failed */ rc = i2c_doio(&state); if (rc == 0) - return (0); /* device exists - read succeeded */ + return 0; /* device exists - read succeeded */ if (rc == I2CERR_TIMEOUT) - return (-1); /* device does not exist - timeout */ + return -1; /* device does not exist - timeout */ if (rc != I2CERR_IO_ERROR || err_flag == 0) - return (rc); /* probe failed */ + return rc; /* probe failed */ if (err_flag & 1) - return (-1); /* device does not exist - had transmit NAK */ + return -1; /* device does not exist - had transmit NAK */ - return (0); /* device exists - had receive overrun */ + return 0; /* device exists - had receive overrun */ } -int -i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { i2c_state_t state; uchar xaddr[4]; @@ -661,27 +645,28 @@ i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) xaddr[0] = (addr >> 24) & 0xFF; xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address - * and the extra bits end up in the "chip address" bit slots. - * This makes a 24WC08 (1Kbyte) chip look like four 256 byte - * chips. - * - * Note that we consider the length of the address field to still - * be one byte because the extra address bits are hidden in the - * chip address. - */ + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address + * and the extra bits end up in the "chip address" bit slots. + * This makes a 24WC08 (1Kbyte) chip look like four 256 byte + * chips. + * + * Note that we consider the length of the address field to still + * be one byte because the extra address bits are hidden in the + * chip address. + */ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif i2c_newio(&state); - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); + rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, + &xaddr[4 - alen]); if (rc != 0) { printf("i2c_read: i2c_send failed (%d)\n", rc); return 1; @@ -701,8 +686,7 @@ i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) return 0; } -int -i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { i2c_state_t state; uchar xaddr[4]; @@ -710,27 +694,28 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) xaddr[0] = (addr >> 24) & 0xFF; xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address - * and the extra bits end up in the "chip address" bit slots. - * This makes a 24WC08 (1Kbyte) chip look like four 256 byte - * chips. - * - * Note that we consider the length of the address field to still - * be one byte because the extra address bits are hidden in the - * chip address. - */ + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address + * and the extra bits end up in the "chip address" bit slots. + * This makes a 24WC08 (1Kbyte) chip look like four 256 byte + * chips. + * + * Note that we consider the length of the address field to still + * be one byte because the extra address bits are hidden in the + * chip address. + */ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif i2c_newio(&state); - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); + rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, + &xaddr[4 - alen]); if (rc != 0) { printf("i2c_write: first i2c_send failed (%d)\n", rc); return 1; @@ -765,7 +750,7 @@ int i2c_set_bus_num(unsigned int bus) if (bus < CONFIG_SYS_MAX_I2C_BUS) { i2c_bus_num = bus; } else { - int ret; + int ret; ret = i2x_mux_select_mux(bus); if (ret == 0) @@ -781,5 +766,5 @@ int i2c_set_bus_num(unsigned int bus) return 0; } -#endif /* CONFIG_I2C_MULTI_BUS */ -#endif /* CONFIG_HARD_I2C */ +#endif /* CONFIG_I2C_MULTI_BUS */ +#endif /* CONFIG_HARD_I2C */ diff --git a/arch/powerpc/cpu/mpc8260/speed.c b/arch/powerpc/cpu/mpc8260/speed.c index 0e1c2b0659..bb50dee960 100644 --- a/arch/powerpc/cpu/mpc8260/speed.c +++ b/arch/powerpc/cpu/mpc8260/speed.c @@ -110,7 +110,7 @@ int get_clocks (void) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; ulong clkin; ulong sccr, dfbrg; - ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf; + ulong scmr, corecnf, plldf, pllmf; corecnf_t *cp; #if !defined(CONFIG_8260_CLKIN) @@ -130,9 +130,6 @@ int get_clocks (void) corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; cp = &corecnf_tab[corecnf]; - busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; - cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; - /* HiP7, HiP7 Rev01, HiP7 RevA */ if ((get_pvr () == PVR_8260_HIP7) || (get_pvr () == PVR_8260_HIP7R1) || @@ -144,12 +141,6 @@ int get_clocks (void) plldf = (scmr & SCMR_PLLDF) ? 1 : 0; gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); } -#if 0 - if (gd->vco_out / (busdf + 1) != clkin) { - /* aaarrrggghhh!!! */ - return (1); - } -#endif gd->cpm_clk = gd->vco_out / 2; gd->bus_clk = clkin; diff --git a/arch/powerpc/cpu/mpc8260/spi.c b/arch/powerpc/cpu/mpc8260/spi.c index f5d2ac35a6..dc98ea73f2 100644 --- a/arch/powerpc/cpu/mpc8260/spi.c +++ b/arch/powerpc/cpu/mpc8260/spi.c @@ -276,11 +276,9 @@ void spi_init_r (void) { volatile spi_t *spi; volatile immap_t *immr; - volatile cpm8260_t *cp; volatile cbd_t *tbdf, *rbdf; immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8260_t *) &immr->im_cpm; spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; @@ -358,7 +356,6 @@ ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len) ssize_t spi_xfer (size_t count) { volatile immap_t *immr; - volatile cpm8260_t *cp; volatile spi_t *spi; cbd_t *tbdf, *rbdf; int tm; @@ -366,7 +363,6 @@ ssize_t spi_xfer (size_t count) DPRINT (("*** spi_xfer entered ***\n")); immr = (immap_t *) CONFIG_SYS_IMMR; - cp = (cpm8260_t *) &immr->im_cpm; spi = (spi_t *)&immr->im_dprambase[PROFF_SPI]; diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 142cfa5b98..5cbf9a688e 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -40,6 +40,7 @@ #include <commproc.h> #include <netdev.h> #include <asm/cache.h> +#include <linux/compiler.h> #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> @@ -185,7 +186,7 @@ static int check_CPU (long clock, uint pvr, uint immr) uint k, m; char buf[32]; char pre = 'X'; - char *mid = "xx"; + __maybe_unused char *mid = "xx"; char *suf; /* the highest 16 bits should be 0x0050 for a 8xx */ diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index a2d2bd6d8d..f2a2c3a736 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -378,35 +378,39 @@ static void fec_pin_init(int fecidx) { bd_t *bd = gd->bd; volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile fec_t *fecp; - - /* - * only two FECs please - */ - if ((unsigned int)fecidx >= 2) - hang(); - - if (fecidx == 0) - fecp = &immr->im_cpm.cp_fec1; - else - fecp = &immr->im_cpm.cp_fec2; /* * Set MII speed to 2.5 MHz or slightly below. - * * According to the MPC860T (Rev. D) Fast ethernet controller user - * * manual (6.2.14), - * * the MII management interface clock must be less than or equal - * * to 2.5 MHz. - * * This MDC frequency is equal to system clock / (2 * MII_SPEED). - * * Then MII_SPEED = system_clock / 2 * 2,5 MHz. + * + * According to the MPC860T (Rev. D) Fast ethernet controller user + * manual (6.2.14), + * the MII management interface clock must be less than or equal + * to 2.5 MHz. + * This MDC frequency is equal to system clock / (2 * MII_SPEED). + * Then MII_SPEED = system_clock / 2 * 2,5 MHz. * * All MII configuration is done via FEC1 registers: */ immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; #if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) - /* our PHYs are the limit at 2.5 MHz */ - fecp->fec_mii_speed <<= 1; + { + volatile fec_t *fecp; + + /* + * only two FECs please + */ + if ((unsigned int)fecidx >= 2) + hang(); + + if (fecidx == 0) + fecp = &immr->im_cpm.cp_fec1; + else + fecp = &immr->im_cpm.cp_fec2; + + /* our PHYs are the limit at 2.5 MHz */ + fecp->fec_mii_speed <<= 1; + } #endif #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) @@ -1010,11 +1014,10 @@ int fec8xx_miiphy_read(const char *devname, unsigned char addr, int fec8xx_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) { - short rdreg; /* register working value */ #ifdef MII_DEBUG printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); #endif - rdreg = mii_send(mk_mii_write(addr, reg, value)); + (void)mii_send(mk_mii_write(addr, reg, value)); #ifdef MII_DEBUG printf ("0x%04x\n", value); diff --git a/arch/powerpc/cpu/mpc8xx/i2c.c b/arch/powerpc/cpu/mpc8xx/i2c.c index 1ca51fddef..3e5ea3a0a2 100644 --- a/arch/powerpc/cpu/mpc8xx/i2c.c +++ b/arch/powerpc/cpu/mpc8xx/i2c.c @@ -39,9 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* define to enable debug messages */ -#undef DEBUG_I2C - /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */ #define TOUT_LOOP 1000000 @@ -50,13 +47,13 @@ DECLARE_GLOBAL_DATA_PTR; #define MAX_TX_SPACE 256 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ -typedef struct I2C_BD -{ - unsigned short status; - unsigned short length; - unsigned char *addr; +typedef struct I2C_BD { + unsigned short status; + unsigned short length; + unsigned char *addr; } I2C_BD; -#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */ + +#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */ #define BD_I2C_TX_CL 0x0001 /* collision error */ #define BD_I2C_TX_UN 0x0002 /* underflow error */ @@ -65,47 +62,41 @@ typedef struct I2C_BD #define BD_I2C_RX_ERR BD_SC_OV -typedef void (*i2c_ecb_t)(int, int); /* error callback function */ +typedef void (*i2c_ecb_t) (int, int); /* error callback function */ /* This structure keeps track of the bd and buffer space usage. */ typedef struct i2c_state { - int rx_idx; /* index to next free Rx BD */ - int tx_idx; /* index to next free Tx BD */ - void *rxbd; /* pointer to next free Rx BD */ - void *txbd; /* pointer to next free Tx BD */ - int tx_space; /* number of Tx bytes left */ - unsigned char *tx_buf; /* pointer to free Tx area */ - i2c_ecb_t err_cb; /* error callback function */ + int rx_idx; /* index to next free Rx BD */ + int tx_idx; /* index to next free Tx BD */ + void *rxbd; /* pointer to next free Rx BD */ + void *txbd; /* pointer to next free Tx BD */ + int tx_space; /* number of Tx bytes left */ + unsigned char *tx_buf; /* pointer to free Tx area */ + i2c_ecb_t err_cb; /* error callback function */ } i2c_state_t; /* flags for i2c_send() and i2c_receive() */ -#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */ -#define I2CF_START_COND 0x02 /* tx: generate start condition */ -#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */ +#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */ +#define I2CF_START_COND 0x02 /* tx: generate start condition */ +#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */ /* return codes */ -#define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */ -#define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */ -#define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */ -#define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */ +#define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */ +#define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */ +#define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */ +#define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */ /* error callback flags */ -#define I2CECB_RX_ERR 0x10 /* this is a receive error */ -#define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */ -#define I2CECB_RX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TX_ERR 0x20 /* this is a transmit error */ -#define I2CECB_TX_CL 0x01 /* transmit collision error */ -#define I2CECB_TX_UN 0x02 /* transmit underflow error */ -#define I2CECB_TX_NAK 0x04 /* transmit no ack error */ -#define I2CECB_TX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */ - -#ifdef DEBUG_I2C -#define PRINTD(x) printf x -#else -#define PRINTD(x) -#endif +#define I2CECB_RX_ERR 0x10 /* this is a receive error */ +#define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */ +#define I2CECB_RX_MASK 0x0f /* mask for error bits */ +#define I2CECB_TX_ERR 0x20 /* this is a transmit error */ +#define I2CECB_TX_CL 0x01 /* transmit collision error */ +#define I2CECB_TX_UN 0x02 /* transmit underflow error */ +#define I2CECB_TX_NAK 0x04 /* transmit no ack error */ +#define I2CECB_TX_MASK 0x0f /* mask for error bits */ +#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */ /* * Returns the best value of I2BRG to meet desired clock speed of I2C with @@ -115,53 +106,53 @@ typedef struct i2c_state { */ static inline int i2c_roundrate(int hz, int speed, int filter, int modval, - int *brgval, int *totspeed) + int *brgval, int *totspeed) { - int moddiv = 1 << (5-(modval & 3)), brgdiv, div; + int moddiv = 1 << (5 - (modval & 3)), brgdiv, div; - PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n", - hz, speed, filter, modval)); + debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n", + hz, speed, filter, modval); - div = moddiv * speed; - brgdiv = (hz + div - 1) / div; + div = moddiv * speed; + brgdiv = (hz + div - 1) / div; - PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv)); + debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv); - *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter); + *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter); - if ((*brgval < 0) || (*brgval > 255)) { - PRINTD(("\t\trejected brgval=%d\n", *brgval)); - return -1; - } + if ((*brgval < 0) || (*brgval > 255)) { + debug("\t\trejected brgval=%d\n", *brgval); + return -1; + } - brgdiv = 2 * (*brgval + 3 + (2 * filter)); - div = moddiv * brgdiv ; - *totspeed = hz / div; + brgdiv = 2 * (*brgval + 3 + (2 * filter)); + div = moddiv * brgdiv; + *totspeed = hz / div; - PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed)); + debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed); - return 0; + return 0; } /* * Sets the I2C clock predivider and divider to meet required clock speed. */ -static int -i2c_setrate (int hz, int speed) +static int i2c_setrate(int hz, int speed) { - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c; - int brgval, - modval, /* 0-3 */ - bestspeed_diff = speed, - bestspeed_brgval = 0, - bestspeed_modval = 0, - bestspeed_filter = 0, - totspeed, - filter = 0; /* Use this fixed value */ + int brgval, + modval, /* 0-3 */ + bestspeed_diff = speed, + bestspeed_brgval = 0, + bestspeed_modval = 0, + bestspeed_filter = 0, + totspeed, + filter = 0; /* Use this fixed value */ for (modval = 0; modval < 4; modval++) { - if (i2c_roundrate(hz,speed,filter,modval,&brgval,&totspeed) == 0) { + if (i2c_roundrate + (hz, speed, filter, modval, &brgval, &totspeed) == 0) { int diff = speed - totspeed; if ((diff >= 0) && (diff < bestspeed_diff)) { @@ -173,30 +164,31 @@ i2c_setrate (int hz, int speed) } } - PRINTD (("[I2C] Best is:\n")); - PRINTD (("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", + debug("[I2C] Best is:\n"); + debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", hz, speed, bestspeed_filter, bestspeed_modval, bestspeed_brgval, - bestspeed_diff)); + bestspeed_diff); - i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3); + i2c->i2c_i2mod |= + ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3); i2c->i2c_i2brg = bestspeed_brgval & 0xff; - PRINTD (("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, - i2c->i2c_i2brg)); + debug("[I2C] i2mod=%08x i2brg=%08x\n", + i2c->i2c_i2mod, + i2c->i2c_i2brg); return 1; } -void -i2c_init(int speed, int slaveaddr) +void i2c_init(int speed, int slaveaddr) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; - volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; + volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; ulong rbase, tbase; volatile I2C_BD *rxbd, *txbd; @@ -219,10 +211,10 @@ i2c_init(int speed, int slaveaddr) #ifdef CONFIG_SYS_ALLOC_DPRAM dpaddr = iip->iic_rbase; if (dpaddr == 0) { - /* need to allocate dual port ram */ - dpaddr = dpram_alloc_align( - (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) + - MAX_TX_SPACE, 8); + /* need to allocate dual port ram */ + dpaddr = dpram_alloc_align((NUM_RX_BDS * sizeof(I2C_BD)) + + (NUM_TX_BDS * sizeof(I2C_BD)) + + MAX_TX_SPACE, 8); } #else dpaddr = CPM_I2C_BASE; @@ -255,25 +247,25 @@ i2c_init(int speed, int slaveaddr) * and current CPU rate (we assume sccr dfbgr field is 0; * divide BRGCLK by 1) */ - PRINTD(("[I2C] Setting rate...\n")); - i2c_setrate (gd->cpu_clk, CONFIG_SYS_I2C_SPEED) ; + debug("[I2C] Setting rate...\n"); + i2c_setrate(gd->cpu_clk, CONFIG_SYS_I2C_SPEED); /* Set I2C controller in master mode */ i2c->i2c_i2com = 0x01; /* Set SDMA bus arbitration level to 5 (SDCR) */ - immap->im_siu_conf.sc_sdcr = 0x0001 ; + immap->im_siu_conf.sc_sdcr = 0x0001; /* Initialize Tx/Rx parameters */ iip->iic_rbase = rbase; iip->iic_tbase = tbase; - rxbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_rbase]); - txbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_tbase]); + rxbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_rbase]); + txbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_tbase]); - PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase)); - PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase)); - PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + debug("[I2C] rbase = %04x\n", iip->iic_rbase); + debug("[I2C] tbase = %04x\n", iip->iic_tbase); + debug("[I2C] rxbd = %08x\n", (int)rxbd); + debug("[I2C] txbd = %08x\n", (int)txbd); /* Set big endian byte order */ iip->iic_tfcr = 0x10; @@ -286,14 +278,14 @@ i2c_init(int speed, int slaveaddr) /* * Initialize required parameters if using microcode patch. */ - iip->iic_rbptr = iip->iic_rbase; - iip->iic_tbptr = iip->iic_tbase; + iip->iic_rbptr = iip->iic_rbase; + iip->iic_tbptr = iip->iic_tbase; iip->iic_rstate = 0; iip->iic_tstate = 0; #else cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG; do { - __asm__ __volatile__ ("eieio"); + __asm__ __volatile__("eieio"); } while (cp->cp_cpcr & CPM_CR_FLG); #endif @@ -302,29 +294,28 @@ i2c_init(int speed, int slaveaddr) i2c->i2c_i2cmr = 0x00; } -static void -i2c_newio(i2c_state_t *state) +static void i2c_newio(i2c_state_t *state) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - PRINTD(("[I2C] i2c_newio\n")); + debug("[I2C] i2c_newio\n"); #ifdef CONFIG_SYS_I2C_UCODE_PATCH iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; #endif state->rx_idx = 0; state->tx_idx = 0; - state->rxbd = (void*)&cp->cp_dpmem[iip->iic_rbase]; - state->txbd = (void*)&cp->cp_dpmem[iip->iic_tbase]; + state->rxbd = (void *)&cp->cp_dpmem[iip->iic_rbase]; + state->txbd = (void *)&cp->cp_dpmem[iip->iic_tbase]; state->tx_space = MAX_TX_SPACE; - state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD); + state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD); state->err_cb = NULL; - PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd)); - PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf)); + debug("[I2C] rxbd = %08x\n", (int)state->rxbd); + debug("[I2C] txbd = %08x\n", (int)state->txbd); + debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf); /* clear the buffer memory */ memset((char *)state->tx_buf, 0, MAX_TX_SPACE); @@ -334,69 +325,71 @@ static int i2c_send(i2c_state_t *state, unsigned char address, unsigned char secondary_address, - unsigned int flags, - unsigned short size, - unsigned char *dataout) + unsigned int flags, unsigned short size, unsigned char *dataout) { volatile I2C_BD *txbd; - int i,j; + int i, j; - PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n", - address, secondary_address, flags, size)); + debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n", + address, secondary_address, flags, size); /* trying to send message larger than BD */ if (size > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; + return I2CERR_MSG_TOO_LONG; /* no more free bds */ if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size)) - return I2CERR_NO_BUFFERS; + return I2CERR_NO_BUFFERS; - txbd = (I2C_BD *)state->txbd; + txbd = (I2C_BD *) state->txbd; txbd->addr = state->tx_buf; - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + debug("[I2C] txbd = %08x\n", (int)txbd); if (flags & I2CF_START_COND) { - PRINTD(("[I2C] Formatting addresses...\n")); + debug("[I2C] Formatting addresses...\n"); if (flags & I2CF_ENABLE_SECONDARY) { - txbd->length = size + 2; /* Length of msg + dest addr */ + /* Length of msg + dest addr */ + txbd->length = size + 2; + txbd->addr[0] = address << 1; txbd->addr[1] = secondary_address; i = 2; } else { - txbd->length = size + 1; /* Length of msg + dest addr */ - txbd->addr[0] = address << 1; /* Write dest addr to BD */ + /* Length of msg + dest addr */ + txbd->length = size + 1; + /* Write dest addr to BD */ + txbd->addr[0] = address << 1; i = 1; } } else { - txbd->length = size; /* Length of message */ + txbd->length = size; /* Length of message */ i = 0; } /* set up txbd */ txbd->status = BD_SC_READY; if (flags & I2CF_START_COND) - txbd->status |= BD_I2C_TX_START; + txbd->status |= BD_I2C_TX_START; if (flags & I2CF_STOP_COND) - txbd->status |= BD_SC_LAST | BD_SC_WRAP; + txbd->status |= BD_SC_LAST | BD_SC_WRAP; /* Copy data to send into buffer */ - PRINTD(("[I2C] copy data...\n")); + debug("[I2C] copy data...\n"); for(j = 0; j < size; i++, j++) - txbd->addr[i] = dataout[j]; + txbd->addr[i] = dataout[j]; - PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, - txbd->status, - txbd->addr[0], - txbd->addr[1])); + debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + txbd->length, + txbd->status, + txbd->addr[0], + txbd->addr[1]); /* advance state */ state->tx_buf += txbd->length; state->tx_space -= txbd->length; state->tx_idx++; - state->txbd = (void*)(txbd + 1); + state->txbd = (void *) (txbd + 1); return 0; } @@ -406,35 +399,35 @@ i2c_receive(i2c_state_t *state, unsigned char address, unsigned char secondary_address, unsigned int flags, - unsigned short size_to_expect, - unsigned char *datain) + unsigned short size_to_expect, unsigned char *datain) { volatile I2C_BD *rxbd, *txbd; - PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags)); + debug("[I2C] i2c_receive %02d %02d %02d\n", + address, secondary_address, flags); /* Expected to receive too much */ if (size_to_expect > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; + return I2CERR_MSG_TOO_LONG; /* no more free bds */ if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS - || state->tx_space < 2) - return I2CERR_NO_BUFFERS; + || state->tx_space < 2) + return I2CERR_NO_BUFFERS; - rxbd = (I2C_BD *)state->rxbd; - txbd = (I2C_BD *)state->txbd; + rxbd = (I2C_BD *) state->rxbd; + txbd = (I2C_BD *) state->txbd; - PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd)); - PRINTD(("[I2C] txbd = %08x\n", (int)txbd)); + debug("[I2C] rxbd = %08x\n", (int)rxbd); + debug("[I2C] txbd = %08x\n", (int)txbd); txbd->addr = state->tx_buf; /* set up TXBD for destination address */ if (flags & I2CF_ENABLE_SECONDARY) { txbd->length = 2; - txbd->addr[0] = address << 1; /* Write data */ - txbd->addr[1] = secondary_address; /* Internal address */ + txbd->addr[0] = address << 1; /* Write data */ + txbd->addr[1] = secondary_address; /* Internal address */ txbd->status = BD_SC_READY; } else { txbd->length = 1 + size_to_expect; @@ -454,24 +447,24 @@ i2c_receive(i2c_state_t *state, rxbd->status |= BD_SC_WRAP; } - PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, - txbd->status, - txbd->addr[0], - txbd->addr[1])); - PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - rxbd->length, - rxbd->status, - rxbd->addr[0], - rxbd->addr[1])); + debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + txbd->length, + txbd->status, + txbd->addr[0], + txbd->addr[1]); + debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", + rxbd->length, + rxbd->status, + rxbd->addr[0], + rxbd->addr[1]); /* advance state */ state->tx_buf += txbd->length; state->tx_space -= txbd->length; state->tx_idx++; - state->txbd = (void*)(txbd + 1); + state->txbd = (void *) (txbd + 1); state->rx_idx++; - state->rxbd = (void*)(rxbd + 1); + state->rxbd = (void *) (rxbd + 1); return 0; } @@ -479,21 +472,21 @@ i2c_receive(i2c_state_t *state, static int i2c_doio(i2c_state_t *state) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; - volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; + volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; volatile I2C_BD *txbd, *rxbd; volatile int j = 0; - PRINTD(("[I2C] i2c_doio\n")); + debug("[I2C] i2c_doio\n"); #ifdef CONFIG_SYS_I2C_UCODE_PATCH iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; #endif if (state->tx_idx <= 0 && state->rx_idx <= 0) { - PRINTD(("[I2C] No I/O is queued\n")); + debug("[I2C] No I/O is queued\n"); return I2CERR_QUEUE_EMPTY; } @@ -501,7 +494,7 @@ static int i2c_doio(i2c_state_t *state) iip->iic_tbptr = iip->iic_tbase; /* Enable I2C */ - PRINTD(("[I2C] Enabling I2C...\n")); + debug("[I2C] Enabling I2C...\n"); i2c->i2c_i2mod |= 0x01; /* Begin transmission */ @@ -511,23 +504,29 @@ static int i2c_doio(i2c_state_t *state) if (state->tx_idx > 0) { txbd = ((I2C_BD*)state->txbd) - 1; - PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd)); - while((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) { - if (ctrlc()) { + + debug("[I2C] Transmitting...(txbd=0x%08lx)\n", + (ulong)txbd); + + while ((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) { + if (ctrlc()) return (-1); - } - __asm__ __volatile__ ("eieio"); + + __asm__ __volatile__("eieio"); } } if ((state->rx_idx > 0) && (j < TOUT_LOOP)) { rxbd = ((I2C_BD*)state->rxbd) - 1; - PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd)); - while((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) { - if (ctrlc()) { + + debug("[I2C] Receiving...(rxbd=0x%08lx)\n", + (ulong)rxbd); + + while ((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) { + if (ctrlc()) return (-1); - } - __asm__ __volatile__ ("eieio"); + + __asm__ __volatile__("eieio"); } } @@ -544,22 +543,24 @@ static int i2c_doio(i2c_state_t *state) if ((n = state->tx_idx) > 0) { for (i = 0; i < n; i++) { - txbd = ((I2C_BD*)state->txbd) - (n - i); + txbd = ((I2C_BD *) state->txbd) - (n - i); if ((b = txbd->status & BD_I2C_TX_ERR) != 0) - (*state->err_cb)(I2CECB_TX_ERR|b, i); + (*state->err_cb) (I2CECB_TX_ERR | b, + i); } } if ((n = state->rx_idx) > 0) { for (i = 0; i < n; i++) { - rxbd = ((I2C_BD*)state->rxbd) - (n - i); + rxbd = ((I2C_BD *) state->rxbd) - (n - i); if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) - (*state->err_cb)(I2CECB_RX_ERR|b, i); + (*state->err_cb) (I2CECB_RX_ERR | b, + i); } } if (j >= TOUT_LOOP) - (*state->err_cb)(I2CECB_TIMEOUT, 0); + (*state->err_cb) (I2CECB_TIMEOUT, 0); } return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0; @@ -567,8 +568,7 @@ static int i2c_doio(i2c_state_t *state) static int had_tx_nak; -static void -i2c_test_callback(int flags, int xnum) +static void i2c_test_callback(int flags, int xnum) { if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK)) had_tx_nak = 1; @@ -587,7 +587,8 @@ int i2c_probe(uchar chip) state.err_cb = i2c_test_callback; had_tx_nak = 0; - rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf); + rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1, + buf); if (rc != 0) return (rc); @@ -612,8 +613,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) xaddr[0] = (addr >> 24) & 0xFF; xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* @@ -626,12 +627,13 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) * be one byte because the extra address bits are hidden in the * chip address. */ - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif i2c_newio(&state); - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); + rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, + &xaddr[4 - alen]); if (rc != 0) { printf("i2c_read: i2c_send failed (%d)\n", rc); return 1; @@ -659,8 +661,8 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) xaddr[0] = (addr >> 24) & 0xFF; xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* @@ -673,12 +675,13 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) * be one byte because the extra address bits are hidden in the * chip address. */ - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif i2c_newio(&state); - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]); + rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, + &xaddr[4 - alen]); if (rc != 0) { printf("i2c_write: first i2c_send failed (%d)\n", rc); return 1; @@ -698,4 +701,4 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) return 0; } -#endif /* CONFIG_HARD_I2C */ +#endif /* CONFIG_HARD_I2C */ diff --git a/arch/powerpc/cpu/mpc8xx/spi.c b/arch/powerpc/cpu/mpc8xx/spi.c index b2ac23e5ea..db34852d60 100644 --- a/arch/powerpc/cpu/mpc8xx/spi.c +++ b/arch/powerpc/cpu/mpc8xx/spi.c @@ -139,14 +139,10 @@ void spi_init_f (void) volatile spi_t *spi; volatile immap_t *immr; - volatile cpic8xx_t *cpi; volatile cpm8xx_t *cp; - volatile iop8xx_t *iop; volatile cbd_t *tbdf, *rbdf; immr = (immap_t *) CONFIG_SYS_IMMR; - cpi = (cpic8xx_t *)&immr->im_cpic; - iop = (iop8xx_t *) &immr->im_ioport; cp = (cpm8xx_t *) &immr->im_cpm; #ifdef CONFIG_SYS_SPI_UCODE_PATCH diff --git a/arch/powerpc/lib/bat_rw.c b/arch/powerpc/lib/bat_rw.c index c48c240151..113c293c03 100644 --- a/arch/powerpc/lib/bat_rw.c +++ b/arch/powerpc/lib/bat_rw.c @@ -26,6 +26,7 @@ #include <asm/processor.h> #include <asm/mmu.h> #include <asm/io.h> +#include <linux/compiler.h> #ifdef CONFIG_ADDR_MAP #include <addr_map.h> @@ -35,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) { - int batn = -1; + __maybe_unused int batn = -1; sync(); diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 3a1b3756e1..ff5888e4cc 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2010 + * (C) Copyright 2000-2011 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -88,7 +88,7 @@ #endif #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE -extern int update_flash_size (int flash_size); +extern int update_flash_size(int flash_size); #endif #if defined(CONFIG_SC3) @@ -96,7 +96,7 @@ extern void sc3_read_eeprom(void); #endif #if defined(CONFIG_CMD_DOC) -void doc_init (void); +void doc_init(void); #endif #if defined(CONFIG_HARD_I2C) || \ defined(CONFIG_SOFT_I2C) @@ -130,9 +130,8 @@ ulong monitor_flash_len; #include <bedbug/type.h> #endif -/************************************************************************ - * Utilities * - ************************************************************************ +/* + * Utilities */ /* @@ -147,16 +146,16 @@ ulong monitor_flash_len; * argument, and returns an integer return code, where 0 means * "continue" and != 0 means "fatal error, hang the system". */ -typedef int (init_fnc_t) (void); +typedef int (init_fnc_t)(void); -/************************************************************************ - * Init Utilities * - ************************************************************************ +/* + * Init Utilities + * * Some of this code should be moved into the core functions, * but let's get it working (again) first... */ -static int init_baudrate (void) +static int init_baudrate(void) { gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); return 0; @@ -168,7 +167,9 @@ void __board_add_ram_info(int use_default) { /* please define platform specific board_add_ram_info() */ } -void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info"))); + +void board_add_ram_info(int) + __attribute__ ((weak, alias("__board_add_ram_info"))); int __board_flash_wp_on(void) { @@ -179,80 +180,86 @@ int __board_flash_wp_on(void) */ return 0; } -int board_flash_wp_on(void) __attribute__((weak, alias("__board_flash_wp_on"))); + +int board_flash_wp_on(void) + __attribute__ ((weak, alias("__board_flash_wp_on"))); void __cpu_secondary_init_r(void) { } + void cpu_secondary_init_r(void) -__attribute__((weak, alias("__cpu_secondary_init_r"))); + __attribute__ ((weak, alias("__cpu_secondary_init_r"))); -static int init_func_ram (void) +static int init_func_ram(void) { #ifdef CONFIG_BOARD_TYPES int board_type = gd->board_type; #else int board_type = 0; /* use dummy arg */ #endif - puts ("DRAM: "); + puts("DRAM: "); - if ((gd->ram_size = initdram (board_type)) > 0) { - print_size (gd->ram_size, ""); + gd->ram_size = initdram(board_type); + + if (gd->ram_size > 0) { + print_size(gd->ram_size, ""); board_add_ram_info(0); putc('\n'); - return (0); + return 0; } - puts (failed); - return (1); + puts(failed); + return 1; } /***********************************************************************/ #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) -static int init_func_i2c (void) +static int init_func_i2c(void) { - puts ("I2C: "); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - puts ("ready\n"); - return (0); + puts("I2C: "); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + puts("ready\n"); + return 0; } #endif #if defined(CONFIG_HARD_SPI) -static int init_func_spi (void) +static int init_func_spi(void) { - puts ("SPI: "); - spi_init (); - puts ("ready\n"); - return (0); + puts("SPI: "); + spi_init(); + puts("ready\n"); + return 0; } #endif /***********************************************************************/ #if defined(CONFIG_WATCHDOG) -static int init_func_watchdog_init (void) +static int init_func_watchdog_init(void) { - puts (" Watchdog enabled\n"); - WATCHDOG_RESET (); - return (0); + puts(" Watchdog enabled\n"); + WATCHDOG_RESET(); + return 0; } -# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init, -static int init_func_watchdog_reset (void) +#define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init, + +static int init_func_watchdog_reset(void) { - WATCHDOG_RESET (); - return (0); + WATCHDOG_RESET(); + return 0; } -# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset, + +#define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset, #else -# define INIT_FUNC_WATCHDOG_INIT /* undef */ -# define INIT_FUNC_WATCHDOG_RESET /* undef */ +#define INIT_FUNC_WATCHDOG_INIT /* undef */ +#define INIT_FUNC_WATCHDOG_RESET /* undef */ #endif /* CONFIG_WATCHDOG */ -/************************************************************************ - * Initialization sequence * - ************************************************************************ +/* + * Initialization sequence */ init_fnc_t *init_sequence[] = { @@ -280,8 +287,10 @@ init_fnc_t *init_sequence[] = { #endif env_init, #if defined(CONFIG_8xx_CPUCLK_DEFAULT) - get_clocks_866, /* get CPU and bus clocks according to the environment variable */ - sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */ + /* get CPU and bus clocks according to the environment variable */ + get_clocks_866, + /* adjust sdram refresh rate according to the new clock */ + sdram_adjust_866, init_timebase, #endif init_baudrate, @@ -317,14 +326,12 @@ init_fnc_t *init_sequence[] = { #ifdef CONFIG_POST post_init_f, #endif - INIT_FUNC_WATCHDOG_RESET - init_func_ram, + INIT_FUNC_WATCHDOG_RESET init_func_ram, #if defined(CONFIG_SYS_DRAM_TEST) testdram, #endif /* CONFIG_SYS_DRAM_TEST */ INIT_FUNC_WATCHDOG_RESET - - NULL, /* Terminate this list */ + NULL, /* Terminate this list */ }; ulong get_effective_memsize(void) @@ -334,12 +341,11 @@ ulong get_effective_memsize(void) #else /* limit stack to what we can reasonable map */ return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size); + CONFIG_MAX_MEM_MAPPED : gd->ram_size); #endif } -/************************************************************************ - * +/* * This is the first part of the initialization sequence that is * implemented in C, but still running from ROM. * @@ -350,8 +356,6 @@ ulong get_effective_memsize(void) * * Be aware of the restrictions: global data is read-only, BSS is not * initialized, and stack space is limited to a few kB. - * - ************************************************************************ */ #ifdef CONFIG_LOGBUFFER @@ -361,13 +365,14 @@ unsigned long logbuffer_base(void) } #endif -void board_init_f (ulong bootflag) +void board_init_f(ulong bootflag) { bd_t *bd; ulong len, addr, addr_sp; ulong *s; gd_t *id; init_fnc_t **init_fnc_ptr; + #ifdef CONFIG_PRAM ulong reg; #endif @@ -375,20 +380,18 @@ void board_init_f (ulong bootflag) /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); + __asm__ __volatile__("":::"memory"); #if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ !defined(CONFIG_MPC86xx) /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); + memset((void *) gd, 0, sizeof(gd_t)); #endif - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - if ((*init_fnc_ptr) () != 0) { - hang (); - } - } + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) + if ((*init_fnc_ptr) () != 0) + hang(); #ifdef CONFIG_POST post_bootmode_init(); @@ -432,7 +435,7 @@ void board_init_f (ulong bootflag) */ if (addr > determine_mp_bootpg()) { addr = determine_mp_bootpg(); - debug ("Reserving MP boot page to %08lx\n", addr); + debug("Reserving MP boot page to %08lx\n", addr); } #endif @@ -440,7 +443,8 @@ void board_init_f (ulong bootflag) #ifndef CONFIG_ALT_LB_ADDR /* reserve kernel log buffer */ addr -= (LOGBUFF_RESERVE); - debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); + debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, + addr); #endif #endif @@ -449,27 +453,27 @@ void board_init_f (ulong bootflag) * reserve protected RAM */ reg = getenv_ulong("pram", 10, CONFIG_PRAM); - addr -= (reg << 10); /* size is in kB */ + addr -= (reg << 10); /* size is in kB */ debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr); #endif /* CONFIG_PRAM */ /* round down to next 4 kB limit */ addr &= ~(4096 - 1); - debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); + debug("Top of RAM usable for U-Boot at: %08lx\n", addr); #ifdef CONFIG_LCD #ifdef CONFIG_FB_ADDR gd->fb_base = CONFIG_FB_ADDR; #else /* reserve memory for LCD display (always full pages) */ - addr = lcd_setmem (addr); + addr = lcd_setmem(addr); gd->fb_base = addr; #endif /* CONFIG_FB_ADDR */ #endif /* CONFIG_LCD */ #if defined(CONFIG_VIDEO) && defined(CONFIG_8xx) /* reserve memory for video display (always full pages) */ - addr = video_setmem (addr); + addr = video_setmem(addr); gd->fb_base = addr; #endif /* CONFIG_VIDEO */ @@ -484,29 +488,29 @@ void board_init_f (ulong bootflag) addr &= ~(65536 - 1); #endif - debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); + debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); /* * reserve memory for malloc() arena */ addr_sp = addr - TOTAL_MALLOC_LEN; - debug ("Reserving %dk for malloc() at: %08lx\n", - TOTAL_MALLOC_LEN >> 10, addr_sp); + debug("Reserving %dk for malloc() at: %08lx\n", + TOTAL_MALLOC_LEN >> 10, addr_sp); /* * (permanently) allocate a Board Info struct * and a permanent copy of the "global" data */ - addr_sp -= sizeof (bd_t); + addr_sp -= sizeof(bd_t); bd = (bd_t *) addr_sp; memset(bd, 0, sizeof(bd_t)); gd->bd = bd; - debug ("Reserving %zu Bytes for Board Info at: %08lx\n", - sizeof (bd_t), addr_sp); - addr_sp -= sizeof (gd_t); + debug("Reserving %zu Bytes for Board Info at: %08lx\n", + sizeof(bd_t), addr_sp); + addr_sp -= sizeof(gd_t); id = (gd_t *) addr_sp; - debug ("Reserving %zu Bytes for Global Data at: %08lx\n", - sizeof (gd_t), addr_sp); + debug("Reserving %zu Bytes for Global Data at: %08lx\n", + sizeof(gd_t), addr_sp); /* * Finally, we set up a new (bigger) stack. @@ -516,22 +520,22 @@ void board_init_f (ulong bootflag) */ addr_sp -= 16; addr_sp &= ~0xF; - s = (ulong *)addr_sp; + s = (ulong *) addr_sp; *s-- = 0; *s-- = 0; - addr_sp = (ulong)s; - debug ("Stack Pointer at: %08lx\n", addr_sp); + addr_sp = (ulong) s; + debug("Stack Pointer at: %08lx\n", addr_sp); /* * Save local variables to board info struct */ - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */ - bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ + bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ + bd->bi_memsize = gd->ram_size; /* size in bytes */ #ifdef CONFIG_SYS_SRAM_BASE - bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM memory */ - bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM memory */ + bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ + bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ #endif #if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ @@ -546,33 +550,34 @@ void board_init_f (ulong bootflag) #endif #if defined(CONFIG_MPC8220) bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ - bd->bi_inpfreq = gd->inp_clk; - bd->bi_pcifreq = gd->pci_clk; - bd->bi_vcofreq = gd->vco_clk; - bd->bi_pevfreq = gd->pev_clk; - bd->bi_flbfreq = gd->flb_clk; + bd->bi_inpfreq = gd->inp_clk; + bd->bi_pcifreq = gd->pci_clk; + bd->bi_vcofreq = gd->vco_clk; + bd->bi_pevfreq = gd->pev_clk; + bd->bi_flbfreq = gd->flb_clk; /* store bootparam to sram (backward compatible), here? */ { - u32 *sram = (u32 *)CONFIG_SYS_SRAM_BASE; + u32 *sram = (u32 *) CONFIG_SYS_SRAM_BASE; + *sram++ = gd->ram_size; *sram++ = gd->bus_clk; *sram++ = gd->inp_clk; *sram++ = gd->cpu_clk; *sram++ = gd->vco_clk; *sram++ = gd->flb_clk; - *sram++ = 0xb8c3ba11; /* boot signature */ + *sram++ = 0xb8c3ba11; /* boot signature */ } #endif - WATCHDOG_RESET (); + WATCHDOG_RESET(); bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ #if defined(CONFIG_CPM2) bd->bi_cpmfreq = gd->cpm_clk; bd->bi_brgfreq = gd->brg_clk; bd->bi_sccfreq = gd->scc_clk; - bd->bi_vco = gd->vco_out; + bd->bi_vco = gd->vco_out; #endif /* CONFIG_CPM2 */ #if defined(CONFIG_MPC512X) bd->bi_ipsfreq = gd->ips_clk; @@ -584,50 +589,46 @@ void board_init_f (ulong bootflag) bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CONFIG_SYS_EXTBDINFO - strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); - strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version)); + strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); + strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, + sizeof(bd->bi_r_version)); bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ bd->bi_plb_busfreq = gd->bus_clk; #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - bd->bi_pci_busfreq = get_PCI_freq (); - bd->bi_opbfreq = get_OPB_freq (); + bd->bi_pci_busfreq = get_PCI_freq(); + bd->bi_opbfreq = get_OPB_freq(); #elif defined(CONFIG_XILINX_405) - bd->bi_pci_busfreq = get_PCI_freq (); + bd->bi_pci_busfreq = get_PCI_freq(); #endif #endif - debug ("New Stack Pointer is: %08lx\n", addr_sp); + debug("New Stack Pointer is: %08lx\n", addr_sp); - WATCHDOG_RESET (); + WATCHDOG_RESET(); - gd->relocaddr = addr; /* Record relocation address, useful for debug */ + gd->relocaddr = addr; /* Store relocation addr, useful for debug */ - memcpy (id, (void *)gd, sizeof (gd_t)); + memcpy(id, (void *) gd, sizeof(gd_t)); - relocate_code (addr_sp, id, addr); + relocate_code(addr_sp, id, addr); /* NOTREACHED - relocate_code() does not return */ } -/************************************************************************ - * +/* * This is the next part if the initialization sequence: we are now * running from RAM and have a "normal" C environment, i. e. global * data can be written, BSS has been cleared, the stack size in not * that critical any more, etc. - * - ************************************************************************ */ -void board_init_r (gd_t *id, ulong dest_addr) +void board_init_r(gd_t *id, ulong dest_addr) { bd_t *bd; ulong malloc_start; -#if defined(CONFIG_SYS_FLASH_CHECKSUM) || defined(CONFIG_CMD_NET) - char *s; -#endif + #ifndef CONFIG_SYS_NO_FLASH ulong flash_size; #endif @@ -663,38 +664,38 @@ void board_init_r (gd_t *id, ulong dest_addr) serial_initialize(); #endif - debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); + debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); - WATCHDOG_RESET (); + WATCHDOG_RESET(); /* * Setup trap handlers */ - trap_init (dest_addr); + trap_init(dest_addr); #ifdef CONFIG_ADDR_MAP init_addr_map(); #endif #if defined(CONFIG_BOARD_EARLY_INIT_R) - board_early_init_r (); + board_early_init_r(); #endif monitor_flash_len = (ulong)&__init_end - dest_addr; - WATCHDOG_RESET (); + WATCHDOG_RESET(); #ifdef CONFIG_LOGBUFFER - logbuff_init_ptrs (); + logbuff_init_ptrs(); #endif #ifdef CONFIG_POST - post_output_backlog (); + post_output_backlog(); #endif WATCHDOG_RESET(); #if defined(CONFIG_SYS_DELAYED_ICACHE) - icache_enable (); /* it's time to enable the instruction cache */ + icache_enable(); /* it's time to enable the instruction cache */ #endif #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) @@ -706,85 +707,89 @@ void board_init_r (gd_t *id, ulong dest_addr) * Do early PCI configuration _before_ the flash gets initialised, * because PCU ressources are crucial for flash access on some boards. */ - pci_init (); + pci_init(); #endif #if defined(CONFIG_WINBOND_83C553) /* * Initialise the ISA bridge */ - initialise_w83c553f (); + initialise_w83c553f(); #endif - asm ("sync ; isync"); + asm("sync ; isync"); - mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN); + mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN); #if !defined(CONFIG_SYS_NO_FLASH) - puts ("Flash: "); + puts("Flash: "); if (board_flash_wp_on()) { printf("Uninitialized - Write Protect On\n"); /* Since WP is on, we can't find real size. Set to 0 */ flash_size = 0; - } else if ((flash_size = flash_init ()) > 0) { -# ifdef CONFIG_SYS_FLASH_CHECKSUM + } else if ((flash_size = flash_init()) > 0) { +#ifdef CONFIG_SYS_FLASH_CHECKSUM char *s; - print_size (flash_size, ""); + print_size(flash_size, ""); /* * Compute and print flash CRC if flashchecksum is set to 'y' * * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX */ - s = getenv ("flashchecksum"); + s = getenv("flashchecksum"); if (s && (*s == 'y')) { - printf (" CRC: %08X", - crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size) - ); + printf(" CRC: %08X", + crc32(0, + (const unsigned char *) + CONFIG_SYS_FLASH_BASE, flash_size) + ); } - putc ('\n'); -# else /* !CONFIG_SYS_FLASH_CHECKSUM */ - print_size (flash_size, "\n"); -# endif /* CONFIG_SYS_FLASH_CHECKSUM */ + putc('\n'); +#else /* !CONFIG_SYS_FLASH_CHECKSUM */ + print_size(flash_size, "\n"); +#endif /* CONFIG_SYS_FLASH_CHECKSUM */ } else { - puts (failed); - hang (); + puts(failed); + hang(); } - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */ - bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */ + /* update start of FLASH memory */ + bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; + /* size of FLASH memory (final value) */ + bd->bi_flashsize = flash_size; #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) /* Make a update of the Memctrl. */ - update_flash_size (flash_size); + update_flash_size(flash_size); #endif -# if defined(CONFIG_OXC) || defined(CONFIG_RMU) +#if defined(CONFIG_OXC) || defined(CONFIG_RMU) /* flash mapped at end of memory map */ bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size; -# elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE - bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */ -# endif +#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE + bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */ +#endif #endif /* !CONFIG_SYS_NO_FLASH */ - WATCHDOG_RESET (); + WATCHDOG_RESET(); /* initialize higher level parts of CPU like time base and timers */ - cpu_init_r (); + cpu_init_r(); - WATCHDOG_RESET (); + WATCHDOG_RESET(); #ifdef CONFIG_SPI -# if !defined(CONFIG_ENV_IS_IN_EEPROM) - spi_init_f (); -# endif - spi_init_r (); +#if !defined(CONFIG_ENV_IS_IN_EEPROM) + spi_init_f(); +#endif + spi_init_r(); #endif #if defined(CONFIG_CMD_NAND) - WATCHDOG_RESET (); - puts ("NAND: "); + WATCHDOG_RESET(); + puts("NAND: "); nand_init(); /* go init the NAND */ #endif @@ -794,13 +799,13 @@ void board_init_r (gd_t *id, ulong dest_addr) * Thus It is required that operations like pin multiplexer * be put in board_init. */ - WATCHDOG_RESET (); - puts ("MMC: "); - mmc_initialize (bd); + WATCHDOG_RESET(); + puts("MMC: "); + mmc_initialize(bd); #endif /* relocate environment function pointers etc. */ - env_relocate (); + env_relocate(); /* * after non-volatile devices & environment is setup and cpu code have @@ -826,21 +831,22 @@ void board_init_r (gd_t *id, ulong dest_addr) * "i2cfast" into account */ { - char *s = getenv ("i2cfast"); + char *s = getenv("i2cfast"); + if (s && ((*s == 'y') || (*s == 'Y'))) { bd->bi_iic_fast[0] = 1; bd->bi_iic_fast[1] = 1; } } -#endif /* CONFIG_I2CFAST */ -#endif /* CONFIG_405GP, CONFIG_405EP */ -#endif /* CONFIG_SYS_EXTBDINFO */ +#endif /* CONFIG_I2CFAST */ +#endif /* CONFIG_405GP, CONFIG_405EP */ +#endif /* CONFIG_SYS_EXTBDINFO */ #if defined(CONFIG_SC3) sc3_read_eeprom(); #endif -#if defined (CONFIG_ID_EEPROM) || defined (CONFIG_SYS_I2C_MAC_OFFSET) +#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) mac_read_from_eeprom(); #endif @@ -872,60 +878,60 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif /* CONFIG_CMD_NET */ /* IP Address */ - bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + bd->bi_ip_addr = getenv_IPaddr("ipaddr"); - WATCHDOG_RESET (); + WATCHDOG_RESET(); #if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) /* * Do pci configuration */ - pci_init (); + pci_init(); #endif /** leave this here (after malloc(), environment and PCI are working) **/ /* Initialize stdio devices */ - stdio_init (); + stdio_init(); /* Initialize the jump table for applications */ - jumptable_init (); + jumptable_init(); #if defined(CONFIG_API) /* Initialize API */ - api_init (); + api_init(); #endif /* Initialize the console (after the relocation and devices init) */ - console_init_r (); + console_init_r(); #if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ - misc_init_r (); + misc_init_r(); #endif #ifdef CONFIG_HERMES if (bd->bi_ethspeed != 0xFFFF) - hermes_start_lxt980 ((int) bd->bi_ethspeed); + hermes_start_lxt980((int) bd->bi_ethspeed); #endif #if defined(CONFIG_CMD_KGDB) - WATCHDOG_RESET (); - puts ("KGDB: "); - kgdb_init (); + WATCHDOG_RESET(); + puts("KGDB: "); + kgdb_init(); #endif - debug ("U-Boot relocated to %08lx\n", dest_addr); + debug("U-Boot relocated to %08lx\n", dest_addr); /* * Enable Interrupts */ - interrupt_init (); + interrupt_init(); #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) - status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); + status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); #endif - udelay (20); + udelay(20); /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); @@ -938,74 +944,74 @@ void board_init_r (gd_t *id, ulong dest_addr) } #endif - WATCHDOG_RESET (); + WATCHDOG_RESET(); #if defined(CONFIG_CMD_SCSI) - WATCHDOG_RESET (); - puts ("SCSI: "); - scsi_init (); + WATCHDOG_RESET(); + puts("SCSI: "); + scsi_init(); #endif #if defined(CONFIG_CMD_DOC) - WATCHDOG_RESET (); - puts ("DOC: "); - doc_init (); + WATCHDOG_RESET(); + puts("DOC: "); + doc_init(); #endif #ifdef CONFIG_BITBANGMII bb_miiphy_init(); #endif #if defined(CONFIG_CMD_NET) - WATCHDOG_RESET (); - puts ("Net: "); - eth_initialize (bd); + WATCHDOG_RESET(); + puts("Net: "); + eth_initialize(bd); #endif #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) - WATCHDOG_RESET (); - debug ("Reset Ethernet PHY\n"); - reset_phy (); + WATCHDOG_RESET(); + debug("Reset Ethernet PHY\n"); + reset_phy(); #endif #ifdef CONFIG_POST - post_run (NULL, POST_RAM | post_bootmode_get(0)); + post_run(NULL, POST_RAM | post_bootmode_get(0)); #endif #if defined(CONFIG_CMD_PCMCIA) \ && !defined(CONFIG_CMD_IDE) - WATCHDOG_RESET (); - puts ("PCMCIA:"); - pcmcia_init (); + WATCHDOG_RESET(); + puts("PCMCIA:"); + pcmcia_init(); #endif #if defined(CONFIG_CMD_IDE) - WATCHDOG_RESET (); -# ifdef CONFIG_IDE_8xx_PCCARD - puts ("PCMCIA:"); -# else - puts ("IDE: "); + WATCHDOG_RESET(); +#ifdef CONFIG_IDE_8xx_PCCARD + puts("PCMCIA:"); +#else + puts("IDE: "); #endif #if defined(CONFIG_START_IDE) if (board_start_ide()) - ide_init (); + ide_init(); #else - ide_init (); + ide_init(); #endif #endif #ifdef CONFIG_LAST_STAGE_INIT - WATCHDOG_RESET (); + WATCHDOG_RESET(); /* * Some parts can be only initialized if all others (like * Interrupts) are up and running (i.e. the PC-style ISA * keyboard). */ - last_stage_init (); + last_stage_init(); #endif #if defined(CONFIG_CMD_BEDBUG) - WATCHDOG_RESET (); - bedbug_init (); + WATCHDOG_RESET(); + bedbug_init(); #endif #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) @@ -1023,46 +1029,49 @@ void board_init_r (gd_t *id, ulong dest_addr) #ifdef CONFIG_LOGBUFFER #ifndef CONFIG_ALT_LB_ADDR /* Also take the logbuffer into account (pram is in kB) */ - pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024; + pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; #endif #endif - sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram); - setenv ("mem", (char *)memsz); + sprintf((char *) memsz, "%ldk", + (bd->bi_memsize / 1024) - pram); + setenv("mem", (char *) memsz); } #endif #ifdef CONFIG_PS2KBD - puts ("PS/2: "); + puts("PS/2: "); kbd_init(); #endif #ifdef CONFIG_MODEM_SUPPORT - { - extern int do_mdm_init; - do_mdm_init = gd->do_mdm_init; - } + { + extern int do_mdm_init; + + do_mdm_init = gd->do_mdm_init; + } #endif /* Initialization complete - start the monitor */ /* main_loop() can return to retry autoboot, if so just run it again. */ for (;;) { - WATCHDOG_RESET (); - main_loop (); + WATCHDOG_RESET(); + main_loop(); } /* NOTREACHED - no way out of command loop except booting */ } -void hang (void) +void hang(void) { - puts ("### ERROR ### Please RESET the board ###\n"); + puts("### ERROR ### Please RESET the board ###\n"); show_boot_progress(-30); - for (;;); + for (;;) + ; } -#if 0 /* We could use plain global data, but the resulting code is bigger */ +#if 0 /* We could use plain global data, but the resulting code is bigger */ /* * Pointer to initial global data area * @@ -1070,7 +1079,8 @@ void hang (void) */ #undef XTRN_DECLARE_GLOBAL_DATA_PTR #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ -DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); -#endif /* 0 */ +DECLARE_GLOBAL_DATA_PTR = + (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); +#endif /* 0 */ /************************************************************************/ |