summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv8/zynqmp/clk.c10
-rw-r--r--arch/arm/cpu/armv8/zynqmp/cpu.c8
-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/bitmain-antminer-s9.dts78
-rw-r--r--arch/arm/dts/zynq-minized.dts106
-rw-r--r--arch/arm/dts/zynqmp-clk-ccf.dtsi16
-rw-r--r--arch/arm/dts/zynqmp-zcu100-revC.dts1
-rw-r--r--arch/arm/dts/zynqmp-zcu104-revA.dts4
-rw-r--r--arch/arm/dts/zynqmp-zcu104-revC.dts15
-rw-r--r--arch/arm/dts/zynqmp-zcu111-revA.dts1
-rw-r--r--arch/arm/include/asm/arch-zynqmp/hardware.h14
-rw-r--r--arch/arm/include/asm/arch-zynqmp/sys_proto.h6
12 files changed, 234 insertions, 26 deletions
diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c
index 13e1977bfa..0593b6310f 100644
--- a/arch/arm/cpu/armv8/zynqmp/clk.c
+++ b/arch/arm/cpu/armv8/zynqmp/clk.c
@@ -16,10 +16,6 @@ unsigned long zynqmp_get_system_timer_freq(void)
u32 ver = zynqmp_get_silicon_version();
switch (ver) {
- case ZYNQMP_CSU_VERSION_VELOCE:
- return 10000;
- case ZYNQMP_CSU_VERSION_EP108:
- return 4000000;
case ZYNQMP_CSU_VERSION_QEMU:
return 50000000;
}
@@ -40,11 +36,7 @@ int set_cpu_clk_info(void)
{
gd->cpu_clk = get_tbclk();
- /* Support Veloce to show at least 1MHz via bdi */
- if (gd->cpu_clk > 1000000)
- gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
- else
- gd->bd->bi_arm_freq = 1;
+ gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
gd->bd->bi_dsp_freq = 0;
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 2748d65d14..e122be59c7 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -135,12 +135,8 @@ unsigned int zynqmp_get_silicon_version(void)
gd->cpu_clk = get_tbclk();
switch (gd->cpu_clk) {
- case 0 ... 1000000:
- return ZYNQMP_CSU_VERSION_VELOCE;
case 50000000:
return ZYNQMP_CSU_VERSION_QEMU;
- case 4000000:
- return ZYNQMP_CSU_VERSION_EP108;
}
return ZYNQMP_CSU_VERSION_SILICON;
@@ -177,8 +173,8 @@ int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001
-#define ZYNQMP_PM_VERSION_MAJOR 0
-#define ZYNQMP_PM_VERSION_MINOR 3
+#define ZYNQMP_PM_VERSION_MAJOR 1
+#define ZYNQMP_PM_VERSION_MINOR 0
#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a0349a8975..197639c405 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
+ zynq-minized.dtb \
zynq-picozed.dtb \
zynq-syzygy-hub.dtb \
zynq-topic-miami.dtb \
diff --git a/arch/arm/dts/bitmain-antminer-s9.dts b/arch/arm/dts/bitmain-antminer-s9.dts
new file mode 100644
index 0000000000..7362ad4e8f
--- /dev/null
+++ b/arch/arm/dts/bitmain-antminer-s9.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Bitmain Antminer S9 board DTS
+ *
+ * Copyright (C) 2018 Michal Simek
+ * Copyright (C) 2018 VanguardiaSur
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Bitmain Antminer S9 Board";
+ compatible = "bitmain,antminer-s9", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ mmc0 = &sdhci0;
+ gpio0 = &gpio0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ bootcount@efffff0 {
+ reg = <0xefffff0 0x10>;
+ no-map;
+ };
+
+ fpga_space@f000000 {
+ reg = <0xf000000 0x1000000>;
+ no-map;
+ };
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethernet_phy>;
+
+ /* 0362/5e62 */
+ ethernet_phy: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&sdhci0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+ disable-wp;
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&watchdog0 {
+ reset-on-timeout;
+ timeout-sec = <200>;
+};
diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts
new file mode 100644
index 0000000000..525921ee7b
--- /dev/null
+++ b/arch/arm/dts/zynq-minized.dts
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Avnet MiniZed board
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
+ */
+
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Avnet Zynq MiniZed Development Board";
+ compatible = "avnet,minized", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "";
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&qspi {
+ status = "okay";
+ is-dual = <0>;
+ num-cs = <1>;
+ flash@0 {
+ compatible = "micron,m25p128";
+ reg = <0x0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <50000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "boot";
+ reg = <0x0 0xff0000>;
+ };
+
+ partition@270000 {
+ label = "kernel";
+ reg = <0x270000 0xd80000>;
+ };
+
+ partition@ff0000 {
+ label = "bootenv";
+ reg = <0xff0000 0x10000>;
+ };
+
+ partition@1000000 {
+ label = "spare";
+ reg = <0x1000000 0x0>;
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+ usb-reset = <&gpio0 7 0>; /* USB_RST_N-MIO7 */
+};
+
+&sdhci1 {
+ status = "okay";
+ non-removable;
+ bus-width = <4>;
+ max-frequency = <12000000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mmccard: mmccard@0 {
+ compatible = "mmc-card";
+ reg = <0>;
+ broken-hpi;
+ };
+};
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index b18d8d19c3..247a35f921 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -248,6 +248,22 @@
clocks = <&clkc 59>, <&clkc 31>;
};
+&ttc0 {
+ clocks = <&clkc 31>;
+};
+
+&ttc1 {
+ clocks = <&clkc 31>;
+};
+
+&ttc2 {
+ clocks = <&clkc 31>;
+};
+
+&ttc3 {
+ clocks = <&clkc 31>;
+};
+
&uart0 {
clocks = <&clkc 56>, <&clkc 31>;
};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index bcd9c3958f..c6aaa08a00 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -252,7 +252,6 @@
&sdhci0 {
status = "okay";
no-1-8-v;
- broken-cd; /* CD has to be enabled by default */
disable-wp;
xlnx,mio_bank = <0>;
};
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index a0e13d8dc5..6a4b701ab8 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -130,9 +130,9 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- tca6416_u97: gpio@21 {
+ tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
- reg = <0x21>;
+ reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/*
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 6e3cf5a97f..fe742b894b 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -74,9 +74,9 @@
status = "okay";
clock-frequency = <400000>;
- tca6416_u97: gpio@21 {
+ tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
- reg = <0x21>;
+ reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/*
@@ -145,10 +145,15 @@
};
};
- i2c@4 {
+ i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <4>;
+ reg = <3>;
+ ina226@40 { /* u183 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
};
i2c@5 {
@@ -163,7 +168,7 @@
reg = <7>;
};
- /* 3, 6 not connected */
+ /* 4, 6 not connected */
};
};
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 4002d78806..aa9055b715 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -500,6 +500,7 @@
&sdhci1 {
status = "okay";
no-1-8-v;
+ disable-wp;
xlnx,mio_bank = <1>;
};
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index acc68251be..8a505edab3 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -30,6 +30,14 @@
#define PS_MODE2 BIT(2)
#define PS_MODE3 BIT(3)
+#define RESET_REASON_DEBUG_SYS BIT(6)
+#define RESET_REASON_SOFT BIT(5)
+#define RESET_REASON_SRST BIT(4)
+#define RESET_REASON_PSONLY BIT(3)
+#define RESET_REASON_PMU BIT(2)
+#define RESET_REASON_INTERNAL BIT(1)
+#define RESET_REASON_EXTERNAL BIT(0)
+
struct crlapb_regs {
u32 reserved0[36];
u32 cpu_r5_ctrl; /* 0x90 */
@@ -37,7 +45,9 @@ struct crlapb_regs {
u32 timestamp_ref_ctrl; /* 0x128 */
u32 reserved2[53];
u32 boot_mode; /* 0x200 */
- u32 reserved3[14];
+ u32 reserved3_0[7];
+ u32 reset_reason; /* 0x220 */
+ u32 reserved3_1[6];
u32 rst_lpd_top; /* 0x23C */
u32 reserved4[4];
u32 boot_pin_ctrl; /* 0x250 */
@@ -120,8 +130,6 @@ struct apu_regs {
/* Board version value */
#define ZYNQMP_CSU_BASEADDR 0xFFCA0000
#define ZYNQMP_CSU_VERSION_SILICON 0x0
-#define ZYNQMP_CSU_VERSION_EP108 0x1
-#define ZYNQMP_CSU_VERSION_VELOCE 0x2
#define ZYNQMP_CSU_VERSION_QEMU 0x3
#define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 6056bc6c0c..773b930512 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -13,8 +13,14 @@
#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D
#define KEY_PTR_LEN 32
+#define ZYNQMP_FPGA_BIT_AUTH_DDR 1
+#define ZYNQMP_FPGA_BIT_AUTH_OCM 2
+#define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3
+#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4
#define ZYNQMP_FPGA_BIT_NS 5
+#define ZYNQMP_FPGA_AUTH_DDR 1
+
enum {
IDCODE,
VERSION,
generated by cgit (git 2.34.1) at 2025-01-30 12:51:27 +0000