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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/dts/Makefile5
-rw-r--r--arch/arm/dts/armada-3720-espressobin.dts135
-rw-r--r--arch/arm/dts/armada-37xx.dtsi14
-rw-r--r--arch/arm/dts/armada-38x-controlcenterdc.dts589
-rw-r--r--arch/arm/dts/armada-7040.dtsi1
-rw-r--r--arch/arm/dts/armada-8040-mcbin.dts293
-rw-r--r--arch/arm/dts/armada-8040.dtsi1
-rw-r--r--arch/arm/dts/armada-ap806.dtsi8
-rw-r--r--arch/arm/dts/armada-cp110-master.dtsi22
-rw-r--r--arch/arm/dts/armada-cp110-slave.dtsi18
-rw-r--r--arch/arm/mach-mvebu/Kconfig14
-rw-r--r--arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c31
13 files changed, 1126 insertions, 6 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1eb373f3df..dacfe9a13f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1284,6 +1284,7 @@ source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
+source "board/gdsys/a38x/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index afeb43ff66..0fbbb9b8b4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -71,16 +71,19 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
dtb-$(CONFIG_ARCH_MVEBU) += \
armada-3720-db.dtb \
+ armada-3720-espressobin.dtb \
armada-375-db.dtb \
armada-388-clearfog.dtb \
armada-388-gp.dtb \
armada-385-amc.dtb \
armada-7040-db.dtb \
armada-8040-db.dtb \
+ armada-8040-mcbin.dtb \
armada-xp-gp.dtb \
armada-xp-maxbcm.dtb \
armada-xp-synology-ds414.dtb \
- armada-xp-theadorable.dtb
+ armada-xp-theadorable.dtb \
+ armada-38x-controlcenterdc.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-ref.dtb
diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
new file mode 100644
index 0000000000..aa6587af66
--- /dev/null
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -0,0 +1,135 @@
+/*
+ * Device Tree file for Marvell Armada 3720 community board
+ * (ESPRESSOBin)
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Konstantin Porotchkin <kostap@marvell.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "armada-372x.dtsi"
+
+/ {
+ model = "Marvell Armada 3720 Community Board ESPRESSOBin";
+ compatible = "marvell,armada-3720-espressobin", "marvell,armada3720", "marvell,armada3710";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = &eth0;
+ i2c0 = &i2c0;
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+ };
+};
+
+&comphy {
+ max-lanes = <3>;
+ phy0 {
+ phy-type = <PHY_TYPE_PEX0>;
+ phy-speed = <PHY_SPEED_2_5G>;
+ };
+
+ phy1 {
+ phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-speed = <PHY_SPEED_5G>;
+ };
+
+ phy2 {
+ phy-type = <PHY_TYPE_SATA0>;
+ phy-speed = <PHY_SPEED_5G>;
+ };
+};
+
+&eth0 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy_addr = <0x1>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* CON3 */
+&sata {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p128", "spi-flash";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ };
+};
+
+/* Exported on the micro USB connector CON32 through an FTDI */
+&uart0 {
+ status = "okay";
+};
+
+/* CON29 */
+&usb2 {
+ status = "okay";
+};
+
+/* CON31 */
+&usb3 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index 062f2a69f4..5bea63b983 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -193,6 +193,20 @@
status = "disabled";
};
+ pinctl0: pinctl@13830 { /* north bridge */
+ compatible = "marvell,armada-3700-pinctl";
+ bank-name = "armada-3700-nb";
+ reg = <0x13830 0x4>;
+ pin-count = <36>;
+ };
+
+ pinctl1: pinctl@18830 { /* south bridge */
+ compatible = "marvell,armada-3700-pinctl";
+ bank-name = "armada-3700-sb";
+ reg = <0x18830 0x4>;
+ pin-count = <30>;
+ };
+
comphy: comphy@18300 {
compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
reg = <0x18300 0x28>,
diff --git a/arch/arm/dts/armada-38x-controlcenterdc.dts b/arch/arm/dts/armada-38x-controlcenterdc.dts
new file mode 100644
index 0000000000..d183fd7502
--- /dev/null
+++ b/arch/arm/dts/armada-38x-controlcenterdc.dts
@@ -0,0 +1,589 @@
+/*
+ * Device Tree file for the Guntermann & Drunck ControlCenter-Compact board
+ *
+ * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
+ *
+ * based on the Device Tree file for Marvell Armada 388 evaluation board
+ * (DB-88F6820), which is
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "armada-388.dtsi"
+
+&gpio0 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio1 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+};
+
+/ {
+ model = "Controlcenter Digital Compact";
+ compatible = "marvell,a385-db", "marvell,armada388",
+ "marvell,armada385", "marvell,armada380";
+
+ chosen {
+ bootargs = "console=ttyS1,115200 earlyprintk";
+ stdout-path = "/soc/internal-regs/serial@12100";
+ };
+
+ aliases {
+ ethernet0 = &eth0;
+ ethernet2 = &eth2;
+ mdio-gpio0 = &MDIO0;
+ mdio-gpio1 = &MDIO1;
+ mdio-gpio2 = &MDIO2;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ i2c0 = &I2C0;
+ i2c1 = &I2C1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; /* 256 MB */
+ };
+
+ clocks {
+ sc16isclk: sc16isclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11059200>;
+ };
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+ internal-regs {
+ spi0: spi@10600 {
+ status = "okay";
+ sc16is741: sc16is741@0 {
+ compatible = "nxp,sc16is741";
+ reg = <0>;
+ clocks = <&sc16isclk>;
+ spi-max-frequency = <4000000>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ spi1: spi@10680 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q016a";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ };
+ spi-flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a11";
+ reg = <1>; /* Chip select 1 */
+ spi-max-frequency = <108000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ I2C0: i2c@11000 {
+ status = "okay";
+ clock-frequency = <1000000>;
+ u-boot,dm-pre-reloc;
+ PCA21: pca9698@21 {
+ compatible = "nxp,pca9698";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ PCA22: pca9698@22 {
+ compatible = "nxp,pca9698";
+ u-boot,dm-pre-reloc;
+ reg = <0x22>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ PCA23: pca9698@23 {
+ compatible = "nxp,pca9698";
+ reg = <0x23>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ PCA24: pca9698@24 {
+ compatible = "nxp,pca9698";
+ reg = <0x24>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ PCA25: pca9698@25 {
+ compatible = "nxp,pca9698";
+ reg = <0x25>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ PCA26: pca9698@26 {
+ compatible = "nxp,pca9698";
+ reg = <0x26>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+
+ I2C1: i2c@11100 {
+ status = "okay";
+ clock-frequency = <400000>;
+ at97sc3205t@29 {
+ compatible = "atmel,at97sc3204t";
+ reg = <0x29>;
+ u-boot,i2c-offset-len = <0>;
+ };
+ emc2305@2d {
+ compatible = "smsc,emc2305";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2d>;
+ fan@0 {
+ reg = <0>;
+ };
+ fan@1 {
+ reg = <1>;
+ };
+ fan@2 {
+ reg = <2>;
+ };
+ fan@3 {
+ reg = <3>;
+ };
+ fan@4 {
+ reg = <4>;
+ };
+ };
+ lm77@48 {
+ compatible = "national,lm77";
+ reg = <0x48>;
+ };
+ ads1015@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ };
+ lm77@4a {
+ compatible = "national,lm77";
+ reg = <0x4a>;
+ };
+ ads1015@4b {
+ compatible = "ti,ads1015";
+ reg = <0x4b>;
+ };
+ emc2305@4c {
+ compatible = "smsc,emc2305";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4c>;
+ fan@0 {
+ reg = <0>;
+ };
+ fan@1 {
+ reg = <1>;
+ };
+ fan@2 {
+ reg = <2>;
+ };
+ fan@3 {
+ reg = <3>;
+ };
+ fan@4 {
+ reg = <4>;
+ };
+ };
+ at24c512@54 {
+ compatible = "atmel,24c512";
+ reg = <0x54>;
+ u-boot,i2c-offset-len = <2>;
+ };
+ ds1339@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+ };
+
+ serial@12000 {
+ status = "okay";
+ };
+
+ serial@12100 {
+ status = "okay";
+ };
+
+ ethernet@34000 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "sgmii";
+ };
+
+ usb@58000 {
+ status = "ok";
+ };
+
+ ethernet@70000 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "sgmii";
+ };
+
+ mdio@72004 {
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+
+ sata@a8000 {
+ status = "okay";
+ };
+
+ sdhci@d8000 {
+ broken-cd;
+ wp-inverted;
+ bus-width = <4>;
+ status = "okay";
+ no-1-8-v;
+ };
+
+ usb3@f0000 {
+ status = "okay";
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+ /*
+ * The two PCIe units are accessible through
+ * standard PCIe slots on the board.
+ */
+ pcie@3,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ };
+
+ MDIO0: mdio0 {
+ compatible = "virtual,mdio-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = < /*MDC*/ &gpio0 13 0
+ /*MDIO*/ &gpio0 14 0>;
+ mv88e1240@0 {
+ reg = <0x0>;
+ };
+ mv88e1240@1 {
+ reg = <0x1>;
+ };
+ mv88e1240@2 {
+ reg = <0x2>;
+ };
+ mv88e1240@3 {
+ reg = <0x3>;
+ };
+ mv88e1240@4 {
+ reg = <0x4>;
+ };
+ mv88e1240@5 {
+ reg = <0x5>;
+ };
+ mv88e1240@6 {
+ reg = <0x6>;
+ };
+ mv88e1240@7 {
+ reg = <0x7>;
+ };
+ mv88e1240@8 {
+ reg = <0x8>;
+ };
+ mv88e1240@9 {
+ reg = <0x9>;
+ };
+ mv88e1240@a {
+ reg = <0xa>;
+ };
+ mv88e1240@b {
+ reg = <0xb>;
+ };
+ mv88e1240@c {
+ reg = <0xc>;
+ };
+ mv88e1240@d {
+ reg = <0xd>;
+ };
+ mv88e1240@e {
+ reg = <0xe>;
+ };
+ mv88e1240@f {
+ reg = <0xf>;
+ };
+ mv88e1240@10 {
+ reg = <0x10>;
+ };
+ mv88e1240@11 {
+ reg = <0x11>;
+ };
+ mv88e1240@12 {
+ reg = <0x12>;
+ };
+ mv88e1240@13 {
+ reg = <0x13>;
+ };
+ mv88e1240@14 {
+ reg = <0x14>;
+ };
+ mv88e1240@15 {
+ reg = <0x15>;
+ };
+ mv88e1240@16 {
+ reg = <0x16>;
+ };
+ mv88e1240@17 {
+ reg = <0x17>;
+ };
+ mv88e1240@18 {
+ reg = <0x18>;
+ };
+ mv88e1240@19 {
+ reg = <0x19>;
+ };
+ mv88e1240@1a {
+ reg = <0x1a>;
+ };
+ mv88e1240@1b {
+ reg = <0x1b>;
+ };
+ mv88e1240@1c {
+ reg = <0x1c>;
+ };
+ mv88e1240@1d {
+ reg = <0x1d>;
+ };
+ mv88e1240@1e {
+ reg = <0x1e>;
+ };
+ mv88e1240@1f {
+ reg = <0x1f>;
+ };
+ };
+
+ MDIO1: mdio1 {
+ compatible = "virtual,mdio-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = < /*MDC*/ &gpio0 25 0
+ /*MDIO*/ &gpio1 13 0>;
+ mv88e1240@0 {
+ reg = <0x0>;
+ };
+ mv88e1240@1 {
+ reg = <0x1>;
+ };
+ mv88e1240@2 {
+ reg = <0x2>;
+ };
+ mv88e1240@3 {
+ reg = <0x3>;
+ };
+ mv88e1240@4 {
+ reg = <0x4>;
+ };
+ mv88e1240@5 {
+ reg = <0x5>;
+ };
+ mv88e1240@6 {
+ reg = <0x6>;
+ };
+ mv88e1240@7 {
+ reg = <0x7>;
+ };
+ mv88e1240@8 {
+ reg = <0x8>;
+ };
+ mv88e1240@9 {
+ reg = <0x9>;
+ };
+ mv88e1240@a {
+ reg = <0xa>;
+ };
+ mv88e1240@b {
+ reg = <0xb>;
+ };
+ mv88e1240@c {
+ reg = <0xc>;
+ };
+ mv88e1240@d {
+ reg = <0xd>;
+ };
+ mv88e1240@e {
+ reg = <0xe>;
+ };
+ mv88e1240@f {
+ reg = <0xf>;
+ };
+ mv88e1240@10 {
+ reg = <0x10>;
+ };
+ mv88e1240@11 {
+ reg = <0x11>;
+ };
+ mv88e1240@12 {
+ reg = <0x12>;
+ };
+ mv88e1240@13 {
+ reg = <0x13>;
+ };
+ mv88e1240@14 {
+ reg = <0x14>;
+ };
+ mv88e1240@15 {
+ reg = <0x15>;
+ };
+ mv88e1240@16 {
+ reg = <0x16>;
+ };
+ mv88e1240@17 {
+ reg = <0x17>;
+ };
+ mv88e1240@18 {
+ reg = <0x18>;
+ };
+ mv88e1240@19 {
+ reg = <0x19>;
+ };
+ mv88e1240@1a {
+ reg = <0x1a>;
+ };
+ mv88e1240@1b {
+ reg = <0x1b>;
+ };
+ mv88e1240@1c {
+ reg = <0x1c>;
+ };
+ mv88e1240@1d {
+ reg = <0x1d>;
+ };
+ mv88e1240@1e {
+ reg = <0x1e>;
+ };
+ mv88e1240@1f {
+ reg = <0x1f>;
+ };
+ };
+
+ MDIO2: mdio2 {
+ compatible = "virtual,mdio-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = < /*MDC*/ &gpio1 14 0
+ /*MDIO*/ &gpio0 24 0>;
+ mv88e1240@0 {
+ reg = <0x0>;
+ };
+ mv88e1240@1 {
+ reg = <0x1>;
+ };
+ mv88e1240@2 {
+ reg = <0x2>;
+ };
+ mv88e1240@3 {
+ reg = <0x3>;
+ };
+ mv88e1240@4 {
+ reg = <0x4>;
+ };
+ mv88e1240@5 {
+ reg = <0x5>;
+ };
+ mv88e1240@6 {
+ reg = <0x6>;
+ };
+ mv88e1240@7 {
+ reg = <0x7>;
+ };
+ mv88e1240@8 {
+ reg = <0x8>;
+ };
+ mv88e1240@9 {
+ reg = <0x9>;
+ };
+ mv88e1240@a {
+ reg = <0xa>;
+ };
+ mv88e1240@b {
+ reg = <0xb>;
+ };
+ mv88e1240@c {
+ reg = <0xc>;
+ };
+ mv88e1240@d {
+ reg = <0xd>;
+ };
+ mv88e1240@e {
+ reg = <0xe>;
+ };
+ mv88e1240@f {
+ reg = <0xf>;
+ };
+ mv88e1240@10 {
+ reg = <0x10>;
+ };
+ mv88e1240@11 {
+ reg = <0x11>;
+ };
+ mv88e1240@12 {
+ reg = <0x12>;
+ };
+ mv88e1240@13 {
+ reg = <0x13>;
+ };
+ mv88e1240@14 {
+ reg = <0x14>;
+ };
+ mv88e1240@15 {
+ reg = <0x15>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ finder_led {
+ label = "finder-led";
+ gpios = <&PCA22 25 0>;
+ };
+
+ status_led {
+ label = "status-led";
+ gpios = <&gpio0 29 0>;
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-7040.dtsi b/arch/arm/dts/armada-7040.dtsi
index 78d995d627..b5be0c4652 100644
--- a/arch/arm/dts/armada-7040.dtsi
+++ b/arch/arm/dts/armada-7040.dtsi
@@ -45,6 +45,7 @@
* one CP110.
*/
+#include <dt-bindings/gpio/gpio.h>
#include "armada-ap806-quad.dtsi"
#include "armada-cp110-master.dtsi"
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
new file mode 100644
index 0000000000..e42b092b25
--- /dev/null
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -0,0 +1,293 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include "armada-8040.dtsi" /* include SoC device tree */
+
+/ {
+ model = "MACCHIATOBin-8040";
+ compatible = "marvell,armada8040-mcbin",
+ "marvell,armada8040";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cpm_i2c0;
+ i2c1 = &cpm_i2c1;
+ spi0 = &cps_spi1;
+ gpio0 = &ap_gpio0;
+ gpio1 = &cpm_gpio0;
+ gpio2 = &cpm_gpio1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ simple-bus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb3h0_vbus: usb3-vbus0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_xhci_vbus_pins>;
+ regulator-name = "reg-usb3h0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <500000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
+ };
+ };
+};
+
+/* Accessible over the mini-USB CON9 connector on the main board */
+&uart0 {
+ status = "okay";
+};
+
+&ap_pinctl {
+ /*
+ * MPP Bus:
+ * eMMC [0-10]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
+ 1 3 0 0 0 0 0 0 0 3 >;
+};
+
+/* on-board eMMC */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_emmc_pins>;
+ bus-width= <8>;
+ status = "okay";
+};
+
+&cpm_pinctl {
+ /*
+ * MPP Bus:
+ * [0-31] = 0xff: Keep default CP0_shared_pins:
+ * [11] CLKOUT_MPP_11 (out)
+ * [23] LINK_RD_IN_CP2CP (in)
+ * [25] CLKOUT_MPP_25 (out)
+ * [29] AVS_FB_IN_CP2CP (in)
+ * [32,34] SMI
+ * [33] MSS power down
+ * [35-38] CP0 I2C1 and I2C0
+ * [39] MSS CKE Enable
+ * [40,41] CP0 UART1 TX/RX
+ * [42,43] XSMI (controls two 10G phys)
+ * [47] USB VBUS EN
+ * [48] FAN PWM
+ * [49] 10G port 1 interrupt
+ * [50] 10G port 0 interrupt
+ * [51] 2.5G SFP TX fault
+ * [52] PCIe reset out
+ * [53] 2.5G SFP mode
+ * [54] 2.5G SFP LOS
+ * [55] Micro SD card detect
+ * [56-61] Micro SD
+ * [62] CP1 KR SFP FAULT
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0 7 0xa 7 2 2 2 2 0xa
+ 7 7 8 8 0 0 0 0 0 0
+ 0 0 0 0 0 0 0xe 0xe 0xe 0xe
+ 0xe 0xe 0 >;
+
+ cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
+ marvell,pins = < 47 >;
+ marvell,function = <0>;
+ };
+
+ cpm_pcie_reset_pins: cpm-pcie-reset-pins {
+ marvell,pins = < 52 >;
+ marvell,function = <0>;
+ };
+};
+
+/* uSD slot */
+&cpm_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_sdhci_pins>;
+ bus-width= <4>;
+ status = "okay";
+};
+
+/* PCIe x4 */
+&cpm_pcie0 {
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_pcie_reset_pins>;
+ marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */
+ status = "okay";
+};
+
+&cpm_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cpm_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_i2c1_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cpm_sata0 {
+ status = "okay";
+};
+
+&cpm_comphy {
+ /*
+ * CP0 Serdes Configuration:
+ * Lane 0: PCIe0 (x4)
+ * Lane 1: PCIe0 (x4)
+ * Lane 2: PCIe0 (x4)
+ * Lane 3: PCIe0 (x4)
+ * Lane 4: KR (10G)
+ * Lane 5: SATA1
+ */
+ phy0 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+ phy1 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+ phy2 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+ phy3 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+ phy4 {
+ phy-type = <PHY_TYPE_KR>;
+ };
+ phy5 {
+ phy-type = <PHY_TYPE_SATA1>;
+ };
+};
+
+&cps_sata0 {
+ status = "okay";
+};
+
+&cps_usb3_0 {
+ vbus-supply = <&reg_usb3h0_vbus>;
+ status = "okay";
+};
+
+&cps_utmi0 {
+ status = "okay";
+};
+
+&cps_pinctl {
+ /*
+ * MPP Bus:
+ * [0-5] TDM
+ * [6,7] CP1_UART 0
+ * [8] CP1 10G SFP LOS
+ * [9] CP1 10G PHY RESET
+ * [10] CP1 10G SFP TX Disable
+ * [11] CP1 10G SFP Mode
+ * [12] SPI1 CS1n
+ * [13] SPI1 MISO (TDM and SPI ROM shared)
+ * [14] SPI1 CS0n
+ * [15] SPI1 MOSI (TDM and SPI ROM shared)
+ * [16] SPI1 CLK (TDM and SPI ROM shared)
+ * [24] CP1 2.5G SFP TX Disable
+ * [26] CP0 10G SFP TX Fault
+ * [27] CP0 10G SFP Mode
+ * [28] CP0 10G SFP LOS
+ * [29] CP0 10G SFP TX Disable
+ * [30] USB Over current indication
+ * [31] 10G Port 0 phy reset
+ * [32-62] = 0xff: Keep default CP1_shared_pins:
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0
+ 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0
+ 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0xff 0xff 0xff>;
+};
+
+&cps_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cps_spi1_pins>;
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xce0000>;
+ };
+ };
+ };
+};
+
+&cps_comphy {
+ /*
+ * CP1 Serdes Configuration:
+ * Lane 0: SGMII2
+ * Lane 1: SATA 0
+ * Lane 2: USB HOST 0
+ * Lane 3: SATA1
+ * Lane 4: KR (10G)
+ * Lane 5: SGMII3
+ */
+ phy0 {
+ phy-type = <PHY_TYPE_SGMII2>;
+ phy-speed = <PHY_SPEED_1_25G>;
+ };
+ phy1 {
+ phy-type = <PHY_TYPE_SATA0>;
+ };
+ phy2 {
+ phy-type = <PHY_TYPE_USB3_HOST0>;
+ };
+ phy3 {
+ phy-type = <PHY_TYPE_SATA1>;
+ };
+ phy4 {
+ phy-type = <PHY_TYPE_KR>;
+ };
+ phy5 {
+ phy-type = <PHY_TYPE_SGMII3>;
+ };
+};
diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi
index 9c1b28c476..96cc112ac9 100644
--- a/arch/arm/dts/armada-8040.dtsi
+++ b/arch/arm/dts/armada-8040.dtsi
@@ -45,6 +45,7 @@
* two CP110.
*/
+#include <dt-bindings/gpio/gpio.h>
#include "armada-ap806-quad.dtsi"
#include "armada-cp110-master.dtsi"
#include "armada-cp110-slave.dtsi"
diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi
index 3042cb154b..e0d301682b 100644
--- a/arch/arm/dts/armada-ap806.dtsi
+++ b/arch/arm/dts/armada-ap806.dtsi
@@ -158,6 +158,14 @@
};
};
+ ap_gpio0: gpio@6F5040 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x6F5040 0x40>;
+ ngpios = <20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
xor@400000 {
compatible = "marvell,mv-xor-v2";
reg = <0x400000 0x1000>,
diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
index 661a69679e..1f0edde0e0 100644
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ b/arch/arm/dts/armada-cp110-master.dtsi
@@ -94,6 +94,10 @@
marvell,pins = < 37 38 >;
marvell,function = <2>;
};
+ cpm_i2c1_pins: cpm-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
marvell,pins = < 44 45 46 47 48 49 50 51
52 53 54 55 >;
@@ -113,6 +117,24 @@
};
};
+ cpm_gpio0: gpio@440100 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x440100 0x40>;
+ ngpios = <32>;
+ gpiobase = <20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ cpm_gpio1: gpio@440140 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x440140 0x40>;
+ ngpios = <31>;
+ gpiobase = <52>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
cpm_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci";
reg = <0x540000 0x30000>;
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi
index 92ef55cf26..ff3fbedab2 100644
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ b/arch/arm/dts/armada-cp110-slave.dtsi
@@ -100,6 +100,24 @@
};
};
+ cps_gpio0: gpio@440100 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x440100 0x40>;
+ ngpios = <32>;
+ gpiobase = <20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ cps_gpio1: gpio@440140 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x440140 0x40>;
+ ngpios = <31>;
+ gpiobase = <52>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
cps_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci";
reg = <0x540000 0x30000>;
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 412bda4160..6ae54ef46a 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -74,8 +74,8 @@ config TARGET_CLEARFOG
bool "Support ClearFog"
select 88F6820
-config TARGET_MVEBU_DB_88F3720
- bool "Support DB-88F3720 Armada 3720"
+config TARGET_MVEBU_ARMADA_37XX
+ bool "Support Armada 37xx platforms"
select ARMADA_3700
config TARGET_DB_88F6720
@@ -112,11 +112,15 @@ config TARGET_THEADORABLE
select BOARD_LATE_INIT if USB
select MV78260
+config TARGET_CONTROLCENTERDC
+ bool "Support CONTROLCENTERDC"
+ select 88F6820
+
endchoice
config SYS_BOARD
default "clearfog" if TARGET_CLEARFOG
- default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720
+ default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX
default "db-88f6720" if TARGET_DB_88F6720
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
@@ -128,7 +132,7 @@ config SYS_BOARD
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
- default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720
+ default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX
default "db-88f6720" if TARGET_DB_88F6720
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
@@ -140,7 +144,7 @@ config SYS_CONFIG_NAME
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
- default "Marvell" if TARGET_MVEBU_DB_88F3720
+ default "Marvell" if TARGET_MVEBU_ARMADA_37XX
default "Marvell" if TARGET_DB_88F6720
default "Marvell" if TARGET_DB_88F6820_GP
default "Marvell" if TARGET_DB_88F6820_AMC
diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
index afc0cefda3..5925bae69f 100644
--- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
@@ -230,6 +230,20 @@ static int serdes_max_lines_get(void)
return 0;
}
+/*
+ * Tests have shown that on some boards the default width of the
+ * configuration pulse for the PEX link detection might lead to
+ * non-established PCIe links (link down). Especially under certain
+ * conditions (higher temperature) and with specific PCIe devices.
+ * To enable a board-specific detection pulse width this weak
+ * array "serdes_pex_pulse_width[4]" is introduced which can be
+ * overwritten if needed by a board-specific version. If the board
+ * code does not provide a non-weak version of this variable, the
+ * default value will be used. So nothing is changed from the
+ * current setup on the supported board.
+ */
+__weak u8 serdes_pex_pulse_width[4] = { 2, 2, 2, 2 };
+
int serdes_phy_config(void)
{
int status = MV_OK;
@@ -891,6 +905,23 @@ int serdes_phy_config(void)
pex_unit = line_num >> 2;
pex_line_num = line_num % 4;
if (0 == pex_line_num) {
+ /*
+ * Configure the detection pulse with before
+ * the reset is deasserted
+ */
+
+ /* Read the old value (indirect access) */
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x48 << 16) | (1 << 31) |
+ (pex_line_num << 24));
+ tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
+ tmp &= ~(1 << 31); /* Clear read */
+ tmp &= ~(3 << 6); /* Mask width */
+ /* Insert new detection pulse width */
+ tmp |= serdes_pex_pulse_width[pex_unit] << 6;
+ /* Write value back */
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+
reg_write(PEX_PHY_ACCESS_REG(pex_unit),
(0xC1 << 16) | 0x24);
DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
generated by cgit (git 2.34.1) at 2025-01-05 00:09:56 +0000