diff options
Diffstat (limited to 'arch')
48 files changed, 1559 insertions, 47 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 629c5e8c2d..7b80630aa1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1631,6 +1631,13 @@ config ARCH_ASPEED select OF_CONTROL imply CMD_DM +config TARGET_DURIAN + bool "Support Phytium Durian Platform" + select ARM64 + help + Support for durian platform. + It has 2GB Sdram, uart and pcie. + endchoice config ARCH_SUPPORT_TFABOOT @@ -1830,6 +1837,7 @@ source "board/woodburn/Kconfig" source "board/xilinx/Kconfig" source "board/xilinx/zynq/Kconfig" source "board/xilinx/zynqmp/Kconfig" +source "board/phytium/durian/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 94fa68250d..b9511da3f3 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -50,8 +50,8 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. -config SECURE_BOOT - bool "Secure Boot" +config NXP_ESBC + bool "NXP_ESBC" help Enable Freescale Secure Boot feature. Normally selected by defconfig. If unsure, do not change. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 24c606a232..f1578b10bc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -45,6 +45,7 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A008514 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A050382 imply PANIC_HANG config ARCH_LS1043A @@ -375,8 +376,8 @@ config EMC2305 Enable the EMC2305 fan controller for configuration of fan speed. -config SECURE_BOOT - bool "Secure Boot" +config NXP_ESBC + bool "NXP_ESBC" help Enable Freescale Secure Boot feature @@ -584,6 +585,8 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool +config SYS_FSL_ERRATUM_A050382 + bool config SYS_FSL_HAS_RGMII bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index efecbc07e7..e398aecd12 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -24,10 +24,12 @@ endif ifneq ($(CONFIG_ARCH_LX2160A),) obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +obj-y += icid.o lx2160_ids.o endif ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o +obj-y += icid.o ls2088_ids.o endif ifneq ($(CONFIG_ARCH_LS1043A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 8fd6c751c6..83a3319321 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -1072,6 +1072,8 @@ static void config_core_prefetch(void) if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; + else + return; prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable", &arglen, buf); @@ -1221,7 +1223,7 @@ void __efi_runtime reset_cpu(ulong addr) #endif } -#ifdef CONFIG_EFI_LOADER +#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET) void __efi_runtime EFIAPI efi_reset_system( enum efi_reset_type reset_type, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index b3e67321b4..bbd550b036 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -64,7 +64,7 @@ void get_sys_info(struct sys_info *sys_info) }; uint i, cluster; -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) uint rcw_tmp; #endif uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -131,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) CONFIG_SYS_FSL_IFC_CLK_DIV; #endif -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) #define HWA_CGA_M2_CLK_SEL 0x00380000 #define HWA_CGA_M2_CLK_SHIFT 19 rcw_tmp = in_le32(&gur->rcwsr[5]); @@ -159,7 +159,7 @@ void get_sys_info(struct sys_info *sys_info) break; } #endif -#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB) +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) sys_info->freq_cga_m2 = sys_info->freq_systembus; #endif } @@ -176,10 +176,10 @@ int get_clocks(void) #endif #if defined(CONFIG_FSL_ESDHC) #if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; #endif -#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) gd->arch.sdhc_clk = sys_info.freq_cga_m2; #endif #else diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c index d9d125e8ba..9462298fbf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = { SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID), SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID), SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID), +#ifdef CONFIG_FSL_CAAM SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), @@ -28,6 +29,7 @@ struct icid_id_table icid_tbl[] = { SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), +#endif }; int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c index 49e27553b1..23743ae10c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = { SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID), +#ifdef CONFIG_FSL_CAAM SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), @@ -25,6 +26,7 @@ struct icid_id_table icid_tbl[] = { SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), +#endif }; int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c new file mode 100644 index 0000000000..e6403b7952 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,ls2080a-ahci", FSL_SATA1_STREAM_ID), + SET_SATA_ICID(2, "fsl,ls2080a-ahci", FSL_SATA2_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), +#endif +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c new file mode 100644 index 0000000000..3a0ed1fa55 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID), + SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID), + SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID), + SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID), +#endif +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 1f1869e8cf..f0df88c565 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -341,7 +341,8 @@ void fsl_lsch3_early_init_f(void) bypass_smmu(); #endif -#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) +#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ + defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) set_icids(); #endif } @@ -828,6 +829,11 @@ int fsl_setenv_mcinitcmd(void) #endif #ifdef CONFIG_BOARD_LATE_INIT +__weak int fsl_board_late_init(void) +{ + return 0; +} + int board_late_init(void) { #ifdef CONFIG_CHAIN_OF_TRUST @@ -862,6 +868,6 @@ int board_late_init(void) qspi_ahb_init(); #endif - return 0; + return fsl_board_late_init(); } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 8eeeef199b..3f6a5f6a42 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -34,7 +34,7 @@ u32 spl_boot_device(void) void spl_board_init(void) { -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2) +#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2) /* * In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3e2677c4f1..85ef00a2bd 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-khadas-edge.dtb \ rk3399-khadas-edge-captain.dtb \ rk3399-khadas-edge-v.dtb \ + rk3399-leez-p710.dtb \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ rk3399-nanopi-neo4.dtb \ @@ -835,6 +836,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb +dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 4be1ab87d2..abc8b21a11 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -192,4 +192,9 @@ status = "disabled"; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + }; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 174d202306..5c110ef9dd 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -97,6 +97,13 @@ u-boot,dm-spl; }; + wkup_vtm0: wkup_vtm@42050000 { + compatible = "ti,am654-vtm", "ti,am654-avs"; + reg = <0x42050000 0x25c>; + power-domains = <&k3_pds 80>; + #thermal-sensor-cells = <1>; + }; + clk_200mhz: dummy_clock { compatible = "fixed-clock"; #clock-cells = <0>; @@ -131,6 +138,12 @@ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; +&wkup_vtm0 { + vdd-supply-3 = <&vdd_mpu>; + vdd-supply-4 = <&vdd_mpu>; + u-boot,dm-spl; +}; + &wkup_pmx0 { u-boot,dm-spl; wkup_uart0_pins_default: wkup_uart0_pins_default { @@ -211,4 +224,18 @@ pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; + u-boot,dm-spl; + + vdd_mpu: tps62363@60 { + compatible = "ti,tps62363"; + reg = <0x60>; + regulator-name = "VDD_MPU"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-always-on; + regulator-boot-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + u-boot,dm-spl; + }; }; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index 92beeea34d..5dd07ac4da 100644 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -57,6 +57,17 @@ clock-names = "fclk"; }; + wkup_i2c0: i2c@42120000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x0 0x42120000 0x0 0x100>; + interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 197 0>; + power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; + }; + mcu_uart0: serial@40a00000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 54d7998d27..41af48214f 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -59,6 +59,13 @@ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>; mbox-names = "tx", "rx"; }; + + wkup_vtm0: wkup_vtm@42040000 { + compatible = "ti,am654-vtm", "ti,j721e-avs"; + reg = <0x0 0x42040000 0x0 0x330>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; &dmsc { @@ -86,6 +93,13 @@ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; + + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ + >; + }; }; &main_pmx0 { @@ -140,4 +154,34 @@ ti,driver-strength-ohm = <50>; }; +&wkup_i2c0 { + u-boot,dm-spl; + tps659413a: tps659413a@48 { + reg = <0x48>; + compatible = "ti,tps659413"; + u-boot,dm-spl; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + regulators: regulators { + u-boot,dm-spl; + buck12_reg: buck12 { + /*VDD_MPU*/ + regulator-name = "buck12"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + u-boot,dm-spl; + }; + }; + }; +}; + +&wkup_vtm0 { + vdd-supply-2 = <&buck12_reg>; + u-boot,dm-spl; +}; + #include "k3-j721e-common-proc-board-u-boot.dtsi" diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi index 1abd9a3887..e5d9e4f1b1 100644 --- a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi @@ -17,6 +17,26 @@ }; }; +&gpio1 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio2 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio3 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio5 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio6 { + /delete-property/ u-boot,dm-spl; +}; + &i2c1 { clock-frequency = <400000>; }; diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi index 976330f897..76f74326ae 100644 --- a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi @@ -21,6 +21,26 @@ clock-frequency = <400000>; }; +&gpio1 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio2 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio3 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio5 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio6 { + /delete-property/ u-boot,dm-spl; +}; + /delete-node/ &uart2; /delete-node/ &uart3; /delete-node/ &mmc2; diff --git a/arch/arm/dts/phytium-durian.dts b/arch/arm/dts/phytium-durian.dts new file mode 100644 index 0000000000..3b76949a26 --- /dev/null +++ b/arch/arm/dts/phytium-durian.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019, Phytium Ltd. + * shuyiqi <shuyiqi@phytium.com.cn> + */ + +/dts-v1/; + +/ { + model = "Phytium Durian"; + compatible = "phytium,durian"; + #address-cells = <2>; + #size-cells = <2>; + + pcie-controller@40000000 { + compatible = "phytium,pcie-host-1.0"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xF00000>, + <0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + uart@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clock = <48000000>; + }; +}; + diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi index 1d441f7124..e5946d2d2d 100644 --- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -5,6 +5,11 @@ #include "rk3328-u-boot.dtsi" #include "rk3328-sdram-lpddr3-1600.dtsi" +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; &usb_host0_xhci { status = "okay"; diff --git a/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi new file mode 100644 index 0000000000..f8b2a1d56e --- /dev/null +++ b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Andy Yan <andy.yan@gmail.com> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; diff --git a/arch/arm/dts/rk3399-leez-p710.dts b/arch/arm/dts/rk3399-leez-p710.dts new file mode 100644 index 0000000000..32baa57b94 --- /dev/null +++ b/arch/arm/dts/rk3399-leez-p710.dts @@ -0,0 +1,645 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Andy Yan <andy.yan@gmail.com> + */ + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pwm/pwm.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Leez RK3399 P710"; + compatible = "leez,p710", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + dc5v_adp: dc5v-adp { + compatible = "regulator-fixed"; + regulator-name = "dc5v_adapter"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc5v_adp>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host0: vcc5v0_host1: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host3: vcc5v0-host3 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host3"; + enable-active-high; + gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host3_en>; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_lan: vcc3v3-lan { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vim-supply = <&vcc3v3_sys>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c7>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_hdmi: LDO_REG2 { + regulator-name = "vcc1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc0v9_hdmi: LDO_REG7 { + regulator-name = "vcc0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcc_1v8>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_3v0>; +}; + +&pinctrl { + bt { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb2 { + vcc5v0_host3_en: vcc5v0-host3-en { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + status = "okay"; + + vref-supply = <&vcc_1v8>; +}; + +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + status = "okay"; + + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host0>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host1>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 37e2fe4e66..3c06a55cb8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -166,7 +166,7 @@ extern int fman_icid_tbl_sz; #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ SET_ICID_ENTRY( \ - (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ + (CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \ (FSL_SEC_JR##jr_num##_OFFSET == \ SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ ? NULL \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 4f050470dd..d46477d96e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -87,6 +87,8 @@ /* SATA */ #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) +#define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000) +#define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000) /* QDMA */ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) @@ -445,7 +447,9 @@ struct ccsr_gur { u8 res_538[0x550 - 0x538]; /* add more registers when needed */ u32 sata1_amqr; u32 sata2_amqr; - u8 res_558[0x570-0x558]; /* add more registers when needed */ + u32 sata3_amqr; + u32 sata4_amqr; + u8 res_560[0x570 - 0x560]; /* add more registers when needed */ u32 misc1_amqr; u8 res_574[0x590-0x574]; /* add more registers when needed */ u32 spare1_amqr; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 93bdcc4caa..94ea99a349 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -105,8 +105,25 @@ #define FSL_SEC_JR4_STREAM_ID 68 #define FSL_SDMMC2_STREAM_ID 69 + +/* + * Erratum A-050382 workaround + * + * Description: + * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not + * correctly forwarded to the SMMU. + * Workaround: + * Program eDMA ICID in the eDMA_AMQR register in DCFG to 40. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A050382 +#define FSL_EDMA_STREAM_ID 40 +#else #define FSL_EDMA_STREAM_ID 70 +#endif + #define FSL_GPU_STREAM_ID 71 #define FSL_DISPLAY_STREAM_ID 72 +#define FSL_SATA3_STREAM_ID 73 +#define FSL_SATA4_STREAM_ID 74 #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h index 15b9788d9c..4bf69dbe08 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h @@ -66,4 +66,7 @@ enum apll_frequencies { APLL_600_MHZ, }; +void rk3328_configure_cpu(struct rk3328_cru *cru, + enum apll_frequencies apll_freq); + #endif /* __ASM_ARCH_CRU_RK3328_H_ */ diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 723f3cf497..8959749ad6 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -23,6 +23,7 @@ #ifdef __KERNEL__ #include <linux/types.h> +#include <linux/kernel.h> #include <asm/byteorder.h> #include <asm/memory.h> #include <asm/barriers.h> @@ -315,9 +316,105 @@ extern void _memset_io(unsigned long, int, size_t); extern void __readwrite_bug(const char *fn); +/* Optimized copy functions to read from/write to IO sapce */ +#ifdef CONFIG_ARM64 +/* + * Copy data from IO memory space to "real" memory space. + */ +static inline +void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count) +{ + while (count && !IS_ALIGNED((unsigned long)from, 8)) { + *(u8 *)to = __raw_readb(from); + from++; + to++; + count--; + } + + while (count >= 8) { + *(u64 *)to = __raw_readq(from); + from += 8; + to += 8; + count -= 8; + } + + while (count) { + *(u8 *)to = __raw_readb(from); + from++; + to++; + count--; + } +} + +/* + * Copy data from "real" memory space to IO memory space. + */ +static inline +void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count) +{ + while (count && !IS_ALIGNED((unsigned long)to, 8)) { + __raw_writeb(*(u8 *)from, to); + from++; + to++; + count--; + } + + while (count >= 8) { + __raw_writeq(*(u64 *)from, to); + from += 8; + to += 8; + count -= 8; + } + + while (count) { + __raw_writeb(*(u8 *)from, to); + from++; + to++; + count--; + } +} + +/* + * "memset" on IO memory space. + */ +static inline +void __memset_io(volatile void __iomem *dst, int c, size_t count) +{ + u64 qc = (u8)c; + + qc |= qc << 8; + qc |= qc << 16; + qc |= qc << 32; + + while (count && !IS_ALIGNED((unsigned long)dst, 8)) { + __raw_writeb(c, dst); + dst++; + count--; + } + + while (count >= 8) { + __raw_writeq(qc, dst); + dst += 8; + count -= 8; + } + + while (count) { + __raw_writeb(c, dst); + dst++; + count--; + } +} +#endif /* CONFIG_ARM64 */ + +#ifdef CONFIG_ARM64 +#define memset_io(a, b, c) __memset_io((a), (b), (c)) +#define memcpy_fromio(a, b, c) __memcpy_fromio((a), (b), (c)) +#define memcpy_toio(a, b, c) __memcpy_toio((a), (b), (c)) +#else #define memset_io(a, b, c) memset((void *)(a), (b), (c)) #define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) #define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) +#endif /* * If this architecture has ISA IO, then define the isa_read/isa_write diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index b2913e8165..47c223917a 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -235,12 +235,18 @@ static void cache_disable(uint32_t cache_bit) /* if cache isn;t enabled no need to disable */ if ((reg & CR_C) != CR_C) return; +#ifdef CONFIG_SYS_ARM_MMU /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; +#endif } reg = get_cr(); +#ifdef CONFIG_SYS_ARM_MMU if (cache_bit == (CR_C | CR_M)) +#elif defined(CONFIG_SYS_ARM_MPU) + if (cache_bit == CR_C) +#endif flush_dcache_all(); set_cr(reg & ~cache_bit); } diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 0b564f7bd1..99edcd9a24 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -116,6 +116,13 @@ void board_init_f(ulong dummy) /* Perform EEPROM-based board detection */ do_board_detect(); +#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs), + &dev); + if (ret) + printf("AVS init failed: %d\n", ret); +#endif + #ifdef CONFIG_K3_AM654_DDRSS ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 5e3813252b..d0bf86abeb 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -118,6 +118,13 @@ void board_init_f(ulong dummy) preloader_console_init(); #endif +#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs), + &dev); + if (ret) + printf("AVS init failed: %d\n", ret); +#endif + #if defined(CONFIG_K3_J721E_DDRSS) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index 585edcf9d5..3c045a5e17 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -63,6 +63,21 @@ def append_bl31_node(file, atf_index, phy_addr, elf_entry): file.write('\t\t};\n') file.write('\n') +def append_tee_node(file, atf_index, phy_addr, elf_entry): + # Append TEE DT node to input FIT dts file. + data = 'tee_0x%08x.bin' % phy_addr + file.write('\t\tatf_%d {\n' % atf_index) + file.write('\t\t\tdescription = \"TEE\";\n') + file.write('\t\t\tdata = /incbin/("%s");\n' % data) + file.write('\t\t\ttype = "tee";\n') + file.write('\t\t\tarch = "arm64";\n') + file.write('\t\t\tos = "tee";\n') + file.write('\t\t\tcompression = "none";\n') + file.write('\t\t\tload = <0x%08x>;\n' % phy_addr) + file.write('\t\t\tentry = <0x%08x>;\n' % elf_entry) + file.write('\t\t};\n') + file.write('\n') + def append_fdt_node(file, dtbs): # Append FDT nodes. cnt = 1 @@ -115,15 +130,23 @@ def generate_atf_fit_dts_uboot(fit_file, uboot_file_name): index, entry, p_paddr, data = segments[0] fit_file.write(DT_UBOOT % p_paddr) -def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name): +def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, tee_file_name, dtbs_file_name): segments = unpack_elf(bl31_file_name) for index, entry, paddr, data in segments: append_bl31_node(fit_file, index + 1, paddr, entry) + num_segments = len(segments) + + if tee_file_name: + tee_segments = unpack_elf(tee_file_name) + for index, entry, paddr, data in tee_segments: + append_tee_node(fit_file, num_segments + index + 1, paddr, entry) + num_segments = num_segments + len(tee_segments) + append_fdt_node(fit_file, dtbs_file_name) fit_file.write(DT_IMAGES_NODE_END) - append_conf_node(fit_file, dtbs_file_name, len(segments)) + append_conf_node(fit_file, dtbs_file_name, num_segments) -def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name): +def generate_atf_fit_dts(fit_file_name, bl31_file_name, tee_file_name, uboot_file_name, dtbs_file_name): # Generate FIT script for ATF image. if fit_file_name != sys.stdout: fit_file = open(fit_file_name, "wb") @@ -132,7 +155,7 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_fi fit_file.write(DT_HEADER) generate_atf_fit_dts_uboot(fit_file, uboot_file_name) - generate_atf_fit_dts_bl31(fit_file, bl31_file_name, dtbs_file_name) + generate_atf_fit_dts_bl31(fit_file, bl31_file_name, tee_file_name, dtbs_file_name) fit_file.write(DT_END) if fit_file_name != sys.stdout: @@ -144,6 +167,13 @@ def generate_atf_binary(bl31_file_name): with open(file_name, "wb") as atf: atf.write(data) +def generate_tee_binary(tee_file_name): + if tee_file_name: + for index, entry, paddr, data in unpack_elf(tee_file_name): + file_name = 'tee_0x%08x.bin' % paddr + with open(file_name, "wb") as atf: + atf.write(data) + def unpack_elf(filename): with open(filename, 'rb') as file: elf = file.read() @@ -178,7 +208,14 @@ def main(): logging.warning(' BL31 file bl31.elf NOT found, resulting binary is non-functional') logging.warning(' Please read Building section in doc/README.rockchip') - opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h") + if "TEE" in os.environ: + tee_elf = os.getenv("TEE") + elif os.path.isfile("./tee.elf"): + tee_elf = "./tee.elf" + else: + tee_elf = "" + + opts, args = getopt.getopt(sys.argv[1:], "o:u:b:t:h") for opt, val in opts: if opt == "-o": fit_its = val @@ -186,14 +223,17 @@ def main(): uboot_elf = val elif opt == "-b": bl31_elf = val + elif opt == "-t": + tee_elf = val elif opt == "-h": print(__doc__) sys.exit(2) dtbs = args - generate_atf_fit_dts(fit_its, bl31_elf, uboot_elf, dtbs) + generate_atf_fit_dts(fit_its, bl31_elf, tee_elf, uboot_elf, dtbs) generate_atf_binary(bl31_elf) + generate_tee_binary(tee_elf) if __name__ == "__main__": main() diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index 95f0e3ccbe..1b012f7f67 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -14,8 +14,8 @@ #define GRF_BASE 0x20008000 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "dwmmc@1021c000", - [BROM_BOOTSOURCE_SD] = "dwmmc@10214000", + [BROM_BOOTSOURCE_EMMC] = "/dwmmc@1021c000", + [BROM_BOOTSOURCE_SD] = "/dwmmc@10214000", }; #ifdef CONFIG_DEBUG_UART_BOARD_INIT diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c index cd0bf8a70c..562117e6c1 100644 --- a/arch/arm/mach-rockchip/rk322x/rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -8,8 +8,8 @@ #include <asm/arch-rockchip/hardware.h> const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "dwmmc@30020000", - [BROM_BOOTSOURCE_SD] = "dwmmc@30000000", + [BROM_BOOTSOURCE_EMMC] = "/dwmmc@30020000", + [BROM_BOOTSOURCE_SD] = "/dwmmc@30000000", }; #ifdef CONFIG_DEBUG_UART_BOARD_INIT diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 4ebc0792d5..afb62fca78 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -67,6 +67,7 @@ config TARGET_FIREFLY_RK3288 bool "Firefly-RK3288" select BOARD_LATE_INIT select SPL_BOARD_INIT if SPL + select TPL help Firefly is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 057ce92080..987b4e0d58 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -22,8 +22,8 @@ DECLARE_GLOBAL_DATA_PTR; #define GRF_BASE 0xff770000 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000", - [BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000", + [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000", }; #ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index c2448d7273..8c81242e5d 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -19,8 +19,8 @@ DECLARE_GLOBAL_DATA_PTR; #define FW_DDR_CON_REG 0xFF7C0040 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000", - [BROM_BOOTSOURCE_SD] = "rksdmmc@ff500000", + [BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000", + [BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000", }; static struct mm_region rk3328_mem_map[] = { diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index 7ccd417a18..20ae797794 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -54,8 +54,8 @@ static struct mm_region rk3368_mem_map[] = { struct mm_region *mem_map = rk3368_mem_map; const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000", - [BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000", + [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000", }; #ifdef CONFIG_ARCH_EARLY_INIT_R diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 6660d05349..f781eacd16 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -91,6 +91,9 @@ config TPL_STACK config TPL_TEXT_BASE default 0xff8c2000 +config SPL_STACK_R_ADDR + default 0x04000000 + source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index fc0a54214f..3770e07258 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,5 +1,8 @@ if ARCH_SOCFPGA +config ERR_PTR_OFFSET + default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range + config NR_DRAM_BANKS default 1 diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c038a6ddb0..8cc82f80b4 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1208,8 +1208,8 @@ config FSL_LAW help Use Freescale common code for Local Access Window -config SECURE_BOOT - bool "Secure Boot" +config NXP_ESBC + bool "NXP_ESBC" help Enable Freescale Secure Boot feature. Normally selected by defconfig. If unsure, do not change. diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index cac9280790..c2b2ef2041 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -38,7 +38,7 @@ #ifdef CONFIG_FSL_CAAM #include <fsl_sec.h> #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) #include <asm/fsl_pamu.h> #include <fsl_secboot_err.h> #endif @@ -440,7 +440,7 @@ ulong cpu_init_f(void) #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif -#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) struct law_entry law; #endif #ifdef CONFIG_ARCH_MPC8548 @@ -460,7 +460,7 @@ ulong cpu_init_f(void) disable_tlb(14); disable_tlb(15); -#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) /* Disable the LAW created for NOR flash by the PBI commands */ law = find_law(CONFIG_SYS_PBI_FLASH_BASE); if (law.index != -1) @@ -963,7 +963,7 @@ int cpu_init_r(void) fman_enet_init(); #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) if (pamu_init() < 0) fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); #endif diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index dbc705388c..38e907f5ad 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -33,7 +33,7 @@ #endif #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \ - !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + !defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define NOR_BOOT #endif @@ -123,7 +123,7 @@ _start_e500: #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \ +#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500MC) && \ !defined(CONFIG_E6500) /* ISBC uses L2 as stack. * Disable L2 cache here so that u-boot can enable it later @@ -467,7 +467,7 @@ nexti: mflr r1 /* R1 = our PC */ blt 1b #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \ - !defined(CONFIG_SECURE_BOOT) + !defined(CONFIG_NXP_ESBC) /* * TLB entry for debuggging in AS1 * Create temporary TLB entry in AS0 to handle debug exception @@ -1065,7 +1065,7 @@ create_init_ram_area: 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 -#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) +#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC) /* create a temp mapping in AS = 1 for Flash mapping * created by PBL for ISBC code */ @@ -1080,7 +1080,7 @@ create_init_ram_area: * and for targets with CONFIG_SPL like T1, T2, T4, only for * u-boot-spl i.e. CONFIG_SPL_BUILD */ -#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) && \ +#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \ (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE * to L3 Address configured by PBL for ISBC code diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 30f35e25e3..ca9e6aa8eb 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -259,7 +259,7 @@ void init_laws(void) #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \ +#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500) && \ !defined(CONFIG_E500MC) /* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms, * which is not disabled before transferring the control to uboot. @@ -268,7 +268,7 @@ void init_laws(void) disable_law(0); #endif -#if !defined(CONFIG_SECURE_BOOT) +#if !defined(CONFIG_NXP_ESBC) /* * if any non DDR LAWs has been created earlier, remove them before * LAW table is parsed. diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 021c85f00f..3195351c9c 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb +dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb diff --git a/arch/powerpc/dts/socrates-u-boot.dtsi b/arch/powerpc/dts/socrates-u-boot.dtsi new file mode 100644 index 0000000000..14a7c245dc --- /dev/null +++ b/arch/powerpc/dts/socrates-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 + * Heiko Schocher, DENX Software Engineering, hs@denx.de + */ +/ { + binman { + filename = "u-boot-socrates.bin"; + pad-byte = <0xff>; + // Place dtb one sector before u-boot-nodtb.bin + blob { + filename = "dts/dt.dtb"; + }; + u-boot-nodtb { + filename = "u-boot-nodtb.bin"; + offset = <0x20000>; + }; + }; + + chosen { + stdout-path = &serial0; + }; + + soc8544@e0000000 { + i2c@3000 { + u-boot,dm-pre-reloc; + }; + }; +}; + +&pci0 { + clock-frequency = <33000000>; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x01000000 0x0 0xe2000000 0xe2000000 0x0 0x01000000>; +}; + +&serial0 { + u-boot,dm-pre-reloc; + clock-frequency = <333333330>; +}; diff --git a/arch/powerpc/dts/socrates.dts b/arch/powerpc/dts/socrates.dts new file mode 100644 index 0000000000..452cf58b5e --- /dev/null +++ b/arch/powerpc/dts/socrates.dts @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree Source for the Socrates board (MPC8544). + * + * Copyright (c) 2008 Emcraft Systems. + * Sergei Poselenov, <sposelenov@emcraft.com> + * + */ + +/dts-v1/; + +/ { + model = "abb,socrates"; + compatible = "abb,socrates"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8544@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000>; // Filled in by U-Boot + }; + + soc8544@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + + ranges = <0x00000000 0xe0000000 0x00100000>; + bus-frequency = <0>; // Filled in by U-Boot + compatible = "fsl,mpc8544-immr", "simple-bus"; + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8544-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,mpc8544-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8544-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; + cache-size = <0x40000>; // L2, 256K + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8544-i2c", "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + fsl,preserve-clocking; + + dtt@28 { + compatible = "winbond,w83782d"; + reg = <0x28>; + }; + rtc@32 { + compatible = "epson,rx8025"; + reg = <0x32>; + interrupts = <7 1>; + interrupt-parent = <&mpic>; + }; + dtt@4c { + compatible = "dallas,ds75"; + reg = <0x4c>; + }; + ts@4a { + compatible = "ti,tsc2003"; + reg = <0x4a>; + interrupt-parent = <&mpic>; + interrupts = <8 1>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl,mpc8544-i2c", "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + fsl,preserve-clocking; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 30 2 34 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy0>; + tbi-handle = <&tbi0>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <0 1>; + reg = <0>; + }; + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <0 1>; + reg = <1>; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + }; + }; + }; + + enet1: ethernet@26000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + ranges = <0x0 0x26000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 32 2 33 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy1>; + tbi-handle = <&tbi1>; + phy-connection-type = "rgmii-id"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + }; + }; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + global-utilities@e0000 { //global utilities block + compatible = "fsl,mpc8548-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + }; + + + localbus { + compatible = "fsl,mpc8544-localbus", + "fsl,pq3-localbus", + "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xe0005000 0x40>; + interrupt-parent = <&mpic>; + interrupts = <19 2>; + + ranges = <0 0 0xfc000000 0x04000000 + 2 0 0xc8000000 0x04000000 + 3 0 0xc0000000 0x00100000 + >; /* Overwritten by U-Boot */ + + nor_flash@0,0 { + compatible = "amd,s29gl256n", "cfi-flash"; + bank-width = <2>; + reg = <0x0 0x000000 0x4000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x0 0x1e0000>; + read-only; + }; + partition@1e0000 { + label = "dtb"; + reg = <0x1e0000 0x20000>; + }; + partition@200000 { + label = "root"; + reg = <0x200000 0x200000>; + }; + partition@400000 { + label = "user"; + reg = <0x400000 0x3b80000>; + }; + partition@3f80000 { + label = "env"; + reg = <0x3f80000 0x40000>; + read-only; + }; + partition@3fc0000 { + label = "u-boot"; + reg = <0x3fc0000 0x40000>; + read-only; + }; + }; + + display@2,0 { + compatible = "fujitsu,lime"; + reg = <2 0x0 0x4000000>; + interrupt-parent = <&mpic>; + interrupts = <6 1>; + }; + + fpga_pic: fpga-pic@3,10 { + compatible = "abb,socrates-fpga-pic"; + reg = <3 0x10 0x10>; + interrupt-controller; + /* IRQs 2, 10, 11, active low, level-sensitive */ + interrupts = <2 1 10 1 11 1>; + interrupt-parent = <&mpic>; + #interrupt-cells = <3>; + }; + + spi@3,60 { + compatible = "abb,socrates-spi"; + reg = <3 0x60 0x10>; + interrupts = <8 4 0>; // number, type, routing + interrupt-parent = <&fpga_pic>; + }; + + nand@3,70 { + compatible = "abb,socrates-nand"; + reg = <3 0x70 0x04>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + data@0 { + label = "data"; + reg = <0x0 0x40000000>; + }; + }; + + can@3,100 { + compatible = "philips,sja1000"; + reg = <3 0x100 0x80>; + interrupts = <2 8 1>; // number, type, routing + interrupt-parent = <&fpga_pic>; + }; + }; + + pci0: pci@e0008000 { + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + reg = <0xe0008000 0x1000>; + clock-frequency = <66666666>; + + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x11 */ + 0x8800 0x0 0x0 1 &mpic 5 1 + /* IDSEL 0x12 */ + 0x9000 0x0 0x0 1 &mpic 4 1>; + interrupt-parent = <&mpic>; + interrupts = <24 2>; + bus-range = <0x0 0x0>; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 + 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>; + }; + +}; diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 64c10074a8..035bf12467 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -7,7 +7,7 @@ #define __FSL_SECURE_BOOT_H #include <asm/config_mpc85xx.h> -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 #elif defined(CONFIG_TARGET_BSC9132QDS) @@ -74,7 +74,7 @@ */ #define CONFIG_FSL_ISBC_KEY_EXT #endif -#endif /* #ifdef CONFIG_SECURE_BOOT */ +#endif /* #ifdef CONFIG_NXP_ESBC */ #ifdef CONFIG_CHAIN_OF_TRUST #ifdef CONFIG_SPL_BUILD |