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-rw-r--r--arch/arm/include/asm/mmu.h8
-rw-r--r--arch/arm/include/asm/system.h36
-rw-r--r--arch/arm/lib/cache-cp15.c24
-rw-r--r--arch/arm/mach-bcm283x/Kconfig1
-rw-r--r--arch/arm/mach-bcm283x/include/mach/base.h8
-rw-r--r--arch/arm/mach-bcm283x/init.c21
6 files changed, 83 insertions, 15 deletions
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
new file mode 100644
index 0000000000..9ac16f599e
--- /dev/null
+++ b/arch/arm/include/asm/mmu.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASM_ARM_MMU_H
+#define __ASM_ARM_MMU_H
+
+void init_addr_map(void);
+
+#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index b8c1b4ea74..37c1bfd726 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -207,7 +207,7 @@ int __asm_invalidate_l3_icache(void);
void __asm_switch_ttbr(u64 new_ttbr);
/*
- * Switch from EL3 to EL2 for ARMv8
+ * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8
*
* @args: For loading 64-bit OS, fdt address.
* For loading 32-bit OS, zero.
@@ -222,7 +222,7 @@ void __asm_switch_ttbr(u64 new_ttbr);
void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
u64 arg4, u64 entry_point, u64 es_flag);
/*
- * Switch from EL2 to EL1 for ARMv8
+ * armv8_switch_to_el1() - switch from EL2 to EL1 for ARMv8
*
* @args: For loading 64-bit OS, fdt address.
* For loading 32-bit OS, zero.
@@ -248,11 +248,12 @@ void flush_l3_cache(void);
void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
/*
- *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
+ * smc_call() - issue a secure monitor call
+ *
+ * Issue a secure monitor call in accordance with ARM "SMC Calling convention",
* DEN0028A
*
* @args: input and output arguments
- *
*/
void smc_call(struct pt_regs *args);
@@ -521,10 +522,12 @@ enum {
#endif
/**
+ * mmu_page_table_flush() - register an update to page tables
+ *
* Register an update to the page tables, and flush the TLB
*
- * \param start start address of update in page table
- * \param stop stop address of update in page table
+ * @start: start address of update in page table
+ * @stop: stop address of update in page table
*/
void mmu_page_table_flush(unsigned long start, unsigned long stop);
@@ -585,11 +588,26 @@ s32 psci_features(u32 function_id, u32 psci_fid);
void save_boot_params_ret(void);
/**
+ * mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping
+ *
+ * Change the virt/phys mapping and cache settings for a region.
+ *
+ * @virt: virtual start address of memory region to change
+ * @phys: physical address for the memory region to set
+ * @size: size of memory region to change
+ * @option: dcache option to select
+ */
+void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
+ size_t size, enum dcache_option option);
+
+/**
+ * mmu_set_region_dcache_behaviour() - set cache settings
+ *
* Change the cache settings for a region.
*
- * \param start start address of memory region to change
- * \param size size of memory region to change
- * \param option dcache option to select
+ * @start: start address of memory region to change
+ * @size: size of memory region to change
+ * @option: dcache option to select
*/
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option);
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 1da2e92fe2..39717610d4 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -25,7 +25,8 @@ __weak void arm_init_domains(void)
{
}
-void set_section_dcache(int section, enum dcache_option option)
+static void set_section_phys(int section, phys_addr_t phys,
+ enum dcache_option option)
{
#ifdef CONFIG_ARMV7_LPAE
u64 *page_table = (u64 *)gd->arch.tlb_addr;
@@ -37,7 +38,7 @@ void set_section_dcache(int section, enum dcache_option option)
#endif
/* Add the page offset */
- value |= ((u32)section << MMU_SECTION_SHIFT);
+ value |= phys;
/* Add caching bits */
value |= option;
@@ -46,13 +47,18 @@ void set_section_dcache(int section, enum dcache_option option)
page_table[section] = value;
}
+void set_section_dcache(int section, enum dcache_option option)
+{
+ set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
+}
+
__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
{
debug("%s: Warning: not implemented\n", __func__);
}
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
- enum dcache_option option)
+void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
+ size_t size, enum dcache_option option)
{
#ifdef CONFIG_ARMV7_LPAE
u64 *page_table = (u64 *)gd->arch.tlb_addr;
@@ -74,8 +80,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
option);
#endif
- for (upto = start; upto < end; upto++)
- set_section_dcache(upto, option);
+ for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
+ set_section_phys(upto, phys, option);
/*
* Make sure range is cache line aligned
@@ -90,6 +96,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
mmu_page_table_flush(startpt, stoppt);
}
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+ enum dcache_option option)
+{
+ mmu_set_region_dcache_behaviour_phys(start, start, size, option);
+}
+
__weak void dram_bank_mmu_setup(int bank)
{
bd_t *bd = gd->bd;
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index e6eb904e7f..b3287ce8bc 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -36,6 +36,7 @@ config BCM2711_32B
select BCM2711
select ARMV7_LPAE
select CPU_V7A
+ select PHYS_64BIT
config BCM2711_64B
bool "Broadcom BCM2711 SoC 64-bit support"
diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
index c4ae39852f..4ccaf69693 100644
--- a/arch/arm/mach-bcm283x/include/mach/base.h
+++ b/arch/arm/mach-bcm283x/include/mach/base.h
@@ -8,4 +8,12 @@
extern unsigned long rpi_bcm283x_base;
+#ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#include <addr_map.h>
+#define phys_to_virt addrmap_phys_to_virt
+#define virt_to_phys addrmap_virt_to_phys
+#endif
+#endif
+
#endif
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index f4d00d892d..fc83392db2 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -134,6 +134,27 @@ int mach_cpu_init(void)
}
#ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
+#include <addr_map.h>
+#include <asm/system.h>
+
+void init_addr_map(void)
+{
+ mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+ DCACHE_OFF);
+
+ /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+ addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
+ /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+ addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+ BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
+}
+#endif
+
void enable_caches(void)
{
dcache_enable();
generated by cgit (git 2.34.1) at 2025-02-05 06:03:54 +0000