diff options
Diffstat (limited to 'arch')
54 files changed, 1046 insertions, 210 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 109d49f57d..8f910f39a3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -450,9 +450,15 @@ config TARGET_SUN4I config TARGET_SUN5I bool "Support sun5i" +config TARGET_SUN6I + bool "Support sun6i" + config TARGET_SUN7I bool "Support sun7i" +config TARGET_SUN8I + bool "Support sun8i" + config TARGET_SNOWBALL bool "Support snowball" diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c index 46ed055023..b8d5c785df 100644 --- a/arch/arm/cpu/arm926ejs/at91/led.c +++ b/arch/arm/cpu/arm926ejs/at91/led.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> +#include <status_led.h> #ifdef CONFIG_RED_LED void red_led_on(void) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 828d10bb5a..29b1d73438 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -9,7 +9,9 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> +#include <ns16550.h> #include <spl.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> @@ -36,6 +38,63 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_DM_GPIO +static const struct omap_gpio_platdata am33xx_gpio[] = { + { 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, + { 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, +#ifdef CONFIG_AM43XX + { 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX }, +#endif +}; + +U_BOOT_DEVICES(am33xx_gpios) = { + { "gpio_omap", &am33xx_gpio[0] }, + { "gpio_omap", &am33xx_gpio[1] }, + { "gpio_omap", &am33xx_gpio[2] }, + { "gpio_omap", &am33xx_gpio[3] }, +#ifdef CONFIG_AM43XX + { "gpio_omap", &am33xx_gpio[4] }, + { "gpio_omap", &am33xx_gpio[5] }, +#endif +}; + +# ifndef CONFIG_OF_CONTROL +/* + * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove + * the CONFIGs. At the same time, we should move this to the board files. + */ +static const struct ns16550_platdata am33xx_serial[] = { + { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK }, +# ifdef CONFIG_SYS_NS16550_COM2 + { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK }, +# ifdef CONFIG_SYS_NS16550_COM3 + { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK }, + { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK }, +# endif +# endif +}; + +U_BOOT_DEVICES(am33xx_uarts) = { + { "serial_omap", &am33xx_serial[0] }, +# ifdef CONFIG_SYS_NS16550_COM2 + { "serial_omap", &am33xx_serial[1] }, +# ifdef CONFIG_SYS_NS16550_COM3 + { "serial_omap", &am33xx_serial[2] }, + { "serial_omap", &am33xx_serial[3] }, + { "serial_omap", &am33xx_serial[4] }, + { "serial_omap", &am33xx_serial[5] }, +# endif +# endif +}; +# endif + +#else + static const struct gpio_bank gpio_bank_am33xx[] = { { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, @@ -49,6 +108,8 @@ static const struct gpio_bank gpio_bank_am33xx[] = { const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; +#endif + #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int cpu_mmc_init(bd_t *bis) { diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 6352422253..a202b0318e 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/armv7.h> +#include <asm/bootm.h> #include <asm/pl310.h> #include <asm/errno.h> #include <asm/io.h> diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 667e77ff05..c942fe67ee 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -17,13 +17,15 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <mmc.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> #include <asm/cache.h> #include <asm/armv7.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/omap_common.h> #include <asm/arch/mmc_host_def.h> #include <i2c.h> @@ -38,6 +40,27 @@ static void omap3_setup_aux_cr(void); static void omap3_invalidate_l2_cache_secure(void); #endif +#ifdef CONFIG_DM_GPIO +static const struct omap_gpio_platdata omap34xx_gpio[] = { + { 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX }, + { 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX }, + { 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX }, +}; + +U_BOOT_DEVICES(am33xx_gpios) = { + { "gpio_omap", &omap34xx_gpio[0] }, + { "gpio_omap", &omap34xx_gpio[1] }, + { "gpio_omap", &omap34xx_gpio[2] }, + { "gpio_omap", &omap34xx_gpio[3] }, + { "gpio_omap", &omap34xx_gpio[4] }, + { "gpio_omap", &omap34xx_gpio[5] }, +}; + +#else + static const struct gpio_bank gpio_bank_34xx[6] = { { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, @@ -49,6 +72,8 @@ static const struct gpio_bank gpio_bank_34xx[6] = { const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; +#endif + #ifdef CONFIG_SPL_BUILD /* * We use static variables because global data is not ready yet. @@ -266,7 +291,7 @@ int __weak misc_init_r(void) * Routine: wait_for_command_complete * Description: Wait for posting to finish on watchdog *****************************************************************************/ -void wait_for_command_complete(struct watchdog *wd_base) +static void wait_for_command_complete(struct watchdog *wd_base) { int pending = 1; do { diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c index 6c7330a0ca..a2aadc9816 100644 --- a/arch/arm/cpu/armv7/omap3/emif4.c +++ b/arch/arm/cpu/armv7/omap3/emif4.c @@ -61,7 +61,7 @@ u32 get_sdr_cs_offset(u32 cs) * - Init the emif4 module for DDR access * - Early init routines, called from flash or SRAM. */ -void do_emif4_init(void) +static void do_emif4_init(void) { unsigned int regval; /* Set the DDR PHY parameters in PHY ctrl registers */ diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index bef5f05eaa..bbb65bbe72 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -16,6 +16,8 @@ #include <asm/io.h> #include <asm/arch/mem.h> /* get mem tables */ #include <asm/arch/sys_proto.h> +#include <asm/bootm.h> + #include <i2c.h> #include <linux/compiler.h> @@ -202,7 +204,7 @@ u32 __weak get_board_rev(void) /******************************************************** * get_base(); get upper addr of current execution *******************************************************/ -u32 get_base(void) +static u32 get_base(void) { u32 val; diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index e9721b27b6..24f1daee64 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -11,9 +11,13 @@ obj-y += timer.o obj-y += board.o obj-y += clock.o obj-y += pinmux.o +obj-$(CONFIG_SUN6I) += prcm.o +obj-$(CONFIG_SUN8I) += prcm.o obj-$(CONFIG_SUN4I) += clock_sun4i.o obj-$(CONFIG_SUN5I) += clock_sun4i.o +obj-$(CONFIG_SUN6I) += clock_sun6i.o obj-$(CONFIG_SUN7I) += clock_sun4i.o +obj-$(CONFIG_SUN8I) += clock_sun6i.o ifndef CONFIG_SPL_BUILD obj-y += cpu_info.o diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index f2cedbb156..06eb6768e8 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -50,18 +50,35 @@ u32 spl_boot_mode(void) int gpio_init(void) { -#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)) +#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I) + /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); +#endif + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPF(4), 1); +#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)) sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); - sunxi_gpio_set_pull(SUNXI_GPB(23), 1); + sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); - sunxi_gpio_set_pull(SUNXI_GPB(20), 1); + sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); - sunxi_gpio_set_pull(SUNXI_GPG(4), 1); + sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX); + sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); #else #error Unsupported console port number. Please fix pin mux settings in board.c #endif @@ -71,6 +88,7 @@ int gpio_init(void) void reset_cpu(ulong addr) { +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) static const struct sunxi_wdog *wdog = &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; @@ -82,12 +100,22 @@ void reset_cpu(ulong addr) /* sun5i sometimes gets stuck without this */ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } +#else /* CONFIG_SUN6I || CONFIG_SUN8I || .. */ + static const struct sunxi_wdog *wdog = + ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; + + /* Set the watchdog for its shortest interval (.5s) and wait */ + writel(WDT_CFG_RESET, &wdog->cfg); + writel(WDT_MODE_EN, &wdog->mode); + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); +#endif } /* do some early init */ void s_init(void) { -#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I) +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \ + defined CONFIG_SUN6I || defined CONFIG_SUN8I) /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n" diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index ecbdb0162b..4a0d64fb30 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -180,6 +180,17 @@ void clock_set_pll1(unsigned int hz) } #endif +unsigned int clock_get_pll5p(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll5_cfg); + int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT); + int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1; + int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT); + return (24000000 * n * k) >> p; +} + unsigned int clock_get_pll6(void) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c new file mode 100644 index 0000000000..1eae9767d0 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -0,0 +1,76 @@ +/* + * sun6i specific clock code + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/prcm.h> +#include <asm/arch/sys_proto.h> + +void clock_init_uart(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + +#if CONFIG_CONS_INDEX < 5 + /* uart clock source is apb2 */ + writel(APB2_CLK_SRC_OSC24M| + APB2_CLK_RATE_N_1| + APB2_CLK_RATE_M(1), + &ccm->apb2_div); + + /* open the clock for uart */ + setbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + + /* deassert uart reset */ + setbits_le32(&ccm->apb2_reset_cfg, + 1 << (APB2_RESET_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); +#else + /* enable R_PIO and R_UART clocks, and de-assert resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); +#endif + + /* Dup with clock_init_safe(), drop once sun6i SPL support lands */ + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); +} + +int clock_twi_onoff(int port, int state) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (port > 3) + return -1; + + /* set the apb clock gate for twi */ + if (state) + setbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port)); + else + clrbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port)); + + return 0; +} + +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; + int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; + return 24000000 * n * k / 2; +} diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index 5cf35acc1e..4f2a09cd2e 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -23,8 +23,12 @@ int print_cpuinfo(void) case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break; default: puts("CPU: Allwinner A1X (SUN5I)\n"); } +#elif defined CONFIG_SUN6I + puts("CPU: Allwinner A31 (SUN6I)\n"); #elif defined CONFIG_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); +#elif defined CONFIG_SUN8I + puts("CPU: Allwinner A23 (SUN8I)\n"); #else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c index 584f7420d7..3cf3cbf19a 100644 --- a/arch/arm/cpu/armv7/sunxi/dram.c +++ b/arch/arm/cpu/armv7/sunxi/dram.c @@ -252,15 +252,9 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) { u32 reg_val; struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* PLL5P and PLL6 are the potential clock sources for MBUS */ - u32 pll6x_div, pll5p_div; - u32 pll6x_clk = clock_get_pll6() / 1000000; - u32 pll5p_clk = clk / 24 * 48; + u32 pll5p_clk, pll6x_clk; + u32 pll5p_div, pll6x_div; u32 pll5p_rate, pll6x_rate; -#ifdef CONFIG_SUN7I - pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */ -#endif /* setup DRAM PLL */ reg_val = readl(&ccm->pll5_cfg); @@ -268,33 +262,32 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */ reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */ reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */ +#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT + /* Old kernels are hardcoded to P=1 (divide by 2) */ + reg_val |= CCM_PLL5_CTRL_P(1); +#endif if (clk >= 540 && clk < 552) { - /* dram = 540MHz, pll5p = 1080MHz */ - pll5p_clk = 1080; + /* dram = 540MHz */ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15)); } else if (clk >= 512 && clk < 528) { - /* dram = 512MHz, pll5p = 1536MHz */ - pll5p_clk = 1536; + /* dram = 512MHz */ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4)); reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16)); } else if (clk >= 496 && clk < 504) { - /* dram = 496MHz, pll5p = 1488MHz */ - pll5p_clk = 1488; + /* dram = 496MHz */ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2)); reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31)); } else if (clk >= 468 && clk < 480) { - /* dram = 468MHz, pll5p = 936MHz */ - pll5p_clk = 936; + /* dram = 468MHz */ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13)); } else if (clk >= 396 && clk < 408) { - /* dram = 396MHz, pll5p = 792MHz */ - pll5p_clk = 792; + /* dram = 396MHz */ reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3)); reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11)); @@ -322,6 +315,13 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) /* setup MBUS clock */ if (!mbus_clk) mbus_clk = 300; + + /* PLL5P and PLL6 are the potential clock sources for MBUS */ + pll6x_clk = clock_get_pll6() / 1000000; +#ifdef CONFIG_SUN7I + pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */ +#endif + pll5p_clk = clock_get_pll5p() / 1000000; pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk); pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk); pll6x_rate = pll6x_clk / pll6x_div; diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c new file mode 100644 index 0000000000..19b4938dc9 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/prcm.c @@ -0,0 +1,35 @@ +/* + * Sunxi A31 Power Management Unit + * + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> + * http://linux-sunxi.org + * + * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work + * + * (C) Copyright 2006-2013 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/prcm.h> +#include <asm/arch/sys_proto.h> + +/* APB0 clock gate and reset bit offsets are the same. */ +void prcm_apb0_enable(u32 flags) +{ + struct sunxi_prcm_reg *prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + + /* open the clock for module */ + setbits_le32(&prcm->apb0_gate, flags); + + /* deassert reset for module */ + setbits_le32(&prcm->apb0_reset, flags); +} diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c index fd77f3f0ef..d98cec9018 100644 --- a/arch/arm/cpu/armv7/tegra20/display.c +++ b/arch/arm/cpu/armv7/tegra20/display.c @@ -194,7 +194,8 @@ static void rgb_enable(struct dc_com_reg *com) writel(rgb_sel_tab[i], &com->pin_output_sel[i]); } -int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config) +static int setup_window(struct disp_ctl_win *win, + struct fdt_disp_config *config) { win->x = 0; win->y = 0; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile index b385e19544..781b511a97 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c new file mode 100644 index 0000000000..0047223181 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/platdevice.h> + +#define UART_MASTER_CLK 36864000 + +SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) +SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) +SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) +SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile index 712afd1bee..e11f4f6d8b 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \ sg_init.o pll_init.o clkrst_init.o pinctrl.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c new file mode 100644 index 0000000000..6da921e920 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/platdevice.h> + +#define UART_MASTER_CLK 73728000 + +SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) +SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) +SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) +SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile index b385e19544..781b511a97 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o +obj-y += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c new file mode 100644 index 0000000000..59d054a310 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/platdevice.h> + +#define UART_MASTER_CLK 80000000 + +SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) +SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) +SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) +SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/cpu/tegra-common/sys_info.c index de20325ecf..5933c35ddd 100644 --- a/arch/arm/cpu/tegra-common/sys_info.c +++ b/arch/arm/cpu/tegra-common/sys_info.c @@ -8,7 +8,7 @@ #include <common.h> #include <linux/ctype.h> -void upstring(char *s) +static void upstring(char *s) { while (*s) { *s = toupper(*s); diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi index 2f66deda9f..e70b4d1f1f 100644 --- a/arch/arm/dts/am335x-bone-common.dtsi +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -10,6 +10,10 @@ model = "TI AM335x BeagleBone"; compatible = "ti,am335x-bone", "ti,am33xx"; + chosen { + stdout-path = &uart0; + }; + cpus { cpu@0 { cpu0-supply = <&dcdc2_reg>; diff --git a/arch/arm/dts/dt-bindings/gpio/gpio.h b/arch/arm/dts/dt-bindings/gpio/gpio.h deleted file mode 100644 index e6b1e0a808..0000000000 --- a/arch/arm/dts/dt-bindings/gpio/gpio.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * This header provides constants for most GPIO bindings. - * - * Most GPIO bindings include a flags cell as part of the GPIO specifier. - * In most cases, the format of the flags cell uses the standard values - * defined in this header. - */ - -#ifndef _DT_BINDINGS_GPIO_GPIO_H -#define _DT_BINDINGS_GPIO_GPIO_H - -#define GPIO_ACTIVE_HIGH 0 -#define GPIO_ACTIVE_LOW 1 - -#endif diff --git a/arch/arm/dts/dt-bindings/pinctrl/am33xx.h b/arch/arm/dts/dt-bindings/pinctrl/am33xx.h deleted file mode 100644 index 2fbc804e1a..0000000000 --- a/arch/arm/dts/dt-bindings/pinctrl/am33xx.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This header provides constants specific to AM33XX pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H -#define _DT_BINDINGS_PINCTRL_AM33XX_H - -#include <dt-bindings/pinctrl/omap.h> - -/* am33xx specific mux bit defines */ -#undef PULL_ENA -#undef INPUT_EN - -#define PULL_DISABLE (1 << 3) -#define INPUT_EN (1 << 5) -#define SLEWCTRL_FAST (1 << 6) - -/* update macro depending on INPUT_EN and PULL_ENA */ -#undef PIN_OUTPUT -#undef PIN_OUTPUT_PULLUP -#undef PIN_OUTPUT_PULLDOWN -#undef PIN_INPUT -#undef PIN_INPUT_PULLUP -#undef PIN_INPUT_PULLDOWN - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) - -/* undef non-existing modes */ -#undef PIN_OFF_NONE -#undef PIN_OFF_OUTPUT_HIGH -#undef PIN_OFF_OUTPUT_LOW -#undef PIN_OFF_INPUT_PULLUP -#undef PIN_OFF_INPUT_PULLDOWN -#undef PIN_OFF_WAKEUPENABLE - -#endif - diff --git a/arch/arm/dts/dt-bindings/pinctrl/omap.h b/arch/arm/dts/dt-bindings/pinctrl/omap.h deleted file mode 100644 index edbd250809..0000000000 --- a/arch/arm/dts/dt-bindings/pinctrl/omap.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This header provides constants for OMAP pinctrl bindings. - * - * Copyright (C) 2009 Nokia - * Copyright (C) 2009-2010 Texas Instruments - */ - -#ifndef _DT_BINDINGS_PINCTRL_OMAP_H -#define _DT_BINDINGS_PINCTRL_OMAP_H - -/* 34xx mux mode options for each pin. See TRM for options */ -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 - -/* 24xx/34xx mux bit defines */ -#define PULL_ENA (1 << 3) -#define PULL_UP (1 << 4) -#define ALTELECTRICALSEL (1 << 5) - -/* 34xx specific mux bit defines */ -#define INPUT_EN (1 << 8) -#define OFF_EN (1 << 9) -#define OFFOUT_EN (1 << 10) -#define OFFOUT_VAL (1 << 11) -#define OFF_PULL_EN (1 << 12) -#define OFF_PULL_UP (1 << 13) -#define WAKEUP_EN (1 << 14) - -/* 44xx specific mux bit defines */ -#define WAKEUP_EVENT (1 << 15) - -/* Active pin states */ -#define PIN_OUTPUT 0 -#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) -#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) -#define PIN_INPUT INPUT_EN -#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) - -/* Off mode states */ -#define PIN_OFF_NONE 0 -#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) -#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) -#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP) -#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) -#define PIN_OFF_WAKEUPENABLE WAKEUP_EN - -#endif - diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index ed826a0e19..09fc22760d 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -7,7 +7,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <bootm.h> #include <common.h> +#include <netdev.h> #include <asm/errno.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/imx-common/misc.c b/arch/arm/imx-common/misc.c index dbecf4e434..12256a38eb 100644 --- a/arch/arm/imx-common/misc.c +++ b/arch/arm/imx-common/misc.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <asm/arch/sys_proto.h> #include <asm/errno.h> #include <asm/io.h> #include <asm/imx-common/regs-common.h> diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index dded857c3a..61f427d914 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -119,6 +119,20 @@ struct bcm2835_mbox_tag_hdr { * }; */ +#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003 + +struct bcm2835_mbox_tag_get_mac_address { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + } req; + struct { + u8 mac[6]; + u8 pad[2]; + } resp; + } body; +}; + #define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005 struct bcm2835_mbox_tag_get_arm_mem { diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 09dfc90a9b..062f3de1d0 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -10,6 +10,8 @@ #ifndef __SYS_PROTO_H__ #define __SYS_PROTO_H__ +#include <asm/imx-common/regs-common.h> + int mxs_reset_block(struct mxs_register_32 *reg); int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 5866bf23e8..34bd8c509a 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -64,6 +64,7 @@ void try_unlock_memory(void); u32 get_boot_type(void); void invalidate_dcache(u32); u32 wait_on_value(u32, u32, void *, u32); +void cancel_out(u32 *num, u32 *den, u32 den_limit); void sdelay(unsigned long); void make_cs1_contiguous(void); void omap_nand_switch_ecc(uint32_t, uint32_t); diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 5669f392fa..c562f621c2 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -15,12 +15,17 @@ #define CLK_GATE_CLOSE 0x0 /* clock control module regs definition */ +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) +#include <asm/arch/clock_sun6i.h> +#else #include <asm/arch/clock_sun4i.h> +#endif #ifndef __ASSEMBLY__ int clock_init(void); int clock_twi_onoff(int port, int state); void clock_set_pll1(unsigned int hz); +unsigned int clock_get_pll5p(void); unsigned int clock_get_pll6(void); void clock_init_safe(void); void clock_init_uart(void); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 1ba997adf9..90af8e2506 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -199,13 +199,16 @@ struct sunxi_ccm_reg { #define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3) #define CCM_PLL5_CTRL_M1_X(n) ((n) - 1) #define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4) +#define CCM_PLL5_CTRL_K_SHIFT 4 #define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3) #define CCM_PLL5_CTRL_K_X(n) ((n) - 1) #define CCM_PLL5_CTRL_LDO (0x1 << 7) #define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8) +#define CCM_PLL5_CTRL_N_SHIFT 8 #define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f) #define CCM_PLL5_CTRL_N_X(n) (n) #define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16) +#define CCM_PLL5_CTRL_P_SHIFT 16 #define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3) #define CCM_PLL5_CTRL_P_X(n) ((n) - 1) #define CCM_PLL5_CTRL_BW (0x1 << 18) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h new file mode 100644 index 0000000000..1397b35889 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -0,0 +1,205 @@ +/* + * sun6i clock register definitions + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_SUN6I_H +#define _SUNXI_CLOCK_SUN6I_H + +struct sunxi_ccm_reg { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 reserved0; + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 reserved1; + u32 pll3_cfg; /* 0x10 pll3 control */ + u32 reserved2; + u32 pll4_cfg; /* 0x18 pll4 control */ + u32 reserved3; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 reserved4; + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 reserved5; + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 reserved6; + u32 pll8_cfg; /* 0x38 pll8 control */ + u32 reserved7; + u32 mipi_pll_cfg; /* 0x40 MIPI pll control */ + u32 pll9_cfg; /* 0x44 pll9 control */ + u32 pll10_cfg; /* 0x48 pll10 control */ + u32 reserved8; + u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ + u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ + u32 apb2_div; /* 0x58 APB2 divide ratio */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb1_gate; /* 0x68 apb1 module clock gating */ + u32 apb2_gate; /* 0x6c apb2 module clock gating */ + u32 reserved9[4]; + u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ + u32 nand1_clk_cfg; /* 0x84 nand1 clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c security system clock control */ + u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ + u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ + u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */ + u32 spi3_clk_cfg; /* 0xac spi3 clock control */ + u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/ + u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ + u32 reserved10[2]; + u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ + u32 reserved11[2]; + u32 usb_clk_cfg; /* 0xcc USB clock control */ + u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */ + u32 reserved12[7]; + u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */ + u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ + u32 reserved13[2]; + u32 dram_clk_gate; /* 0x100 DRAM module gating */ + u32 be0_clk_cfg; /* 0x104 BE0 module clock */ + u32 be1_clk_cfg; /* 0x108 BE1 module clock */ + u32 fe0_clk_cfg; /* 0x10c FE0 module clock */ + u32 fe1_clk_cfg; /* 0x110 FE1 module clock */ + u32 mp_clk_cfg; /* 0x114 MP module clock */ + u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ + u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */ + u32 reserved14[3]; + u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */ + u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */ + u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */ + u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */ + u32 ve_clk_cfg; /* 0x13c VE module clock */ + u32 adda_clk_cfg; /* 0x140 ADDA module clock */ + u32 avs_clk_cfg; /* 0x144 AVS module clock */ + u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/ + u32 reserved15; + u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ + u32 ps_clk_cfg; /* 0x154 PS module clock */ + u32 mtc_clk_cfg; /* 0x158 MTC module clock */ + u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */ + u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */ + u32 reserved16; + u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ + u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */ + u32 reserved17[4]; + u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */ + u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */ + u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */ + u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */ + u32 reserved18[4]; + u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ + u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ + u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */ + u32 reserved19[21]; + u32 pll_lock; /* 0x200 PLL Lock Time */ + u32 pll1_lock; /* 0x204 PLL1 Lock Time */ + u32 reserved20[6]; + u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */ + u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */ + u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */ + u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */ + u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */ + u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */ + u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */ + u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */ + u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */ + u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */ + u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */ + u32 reserved21[13]; + u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */ + u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */ + u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */ + u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */ + u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */ + u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */ + u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */ + u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */ + u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */ + u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */ + u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */ + u32 reserved22[5]; + u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ + u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ + u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ + u32 reserved23; + u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */ + u32 reserved24; + u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */ +}; + +/* apb2 bit field */ +#define APB2_CLK_SRC_LOSC (0x0 << 24) +#define APB2_CLK_SRC_OSC24M (0x1 << 24) +#define APB2_CLK_SRC_PLL6 (0x2 << 24) +#define APB2_CLK_SRC_MASK (0x3 << 24) +#define APB2_CLK_RATE_N_1 (0x0 << 16) +#define APB2_CLK_RATE_N_2 (0x1 << 16) +#define APB2_CLK_RATE_N_4 (0x2 << 16) +#define APB2_CLK_RATE_N_8 (0x3 << 16) +#define APB2_CLK_RATE_N_MASK (3 << 16) +#define APB2_CLK_RATE_M(m) (((m)-1) << 0) +#define APB2_CLK_RATE_M_MASK (0x1f << 0) + +/* apb2 gate field */ +#define APB2_GATE_UART_SHIFT (16) +#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) +#define APB2_GATE_TWI_SHIFT (0) +#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) + +/* cpu_axi_cfg bits */ +#define AXI_DIV_SHIFT 0 +#define ATB_DIV_SHIFT 8 +#define CPU_CLK_SRC_SHIFT 16 + +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define ATB_DIV_1 0 +#define ATB_DIV_2 1 +#define ATB_DIV_4 2 +#define CPU_CLK_SRC_OSC24M 1 +#define CPU_CLK_SRC_PLL1 2 + +#define PLL1_CFG_DEFAULT 0x90011b21 + +#define PLL6_CFG_DEFAULT 0x90041811 + +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_K_SHIFT 4 +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) + +#define AHB_GATE_OFFSET_MMC3 11 +#define AHB_GATE_OFFSET_MMC2 10 +#define AHB_GATE_OFFSET_MMC1 9 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) + +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6 (0x1 << 24) + +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) + +#define AHB_RESET_OFFSET_MMC3 11 +#define AHB_RESET_OFFSET_MMC2 10 +#define AHB_RESET_OFFSET_MMC1 9 +#define AHB_RESET_OFFSET_MMC0 8 +#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) + +/* apb2 reset */ +#define APB2_RESET_UART_SHIFT (16) +#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) +#define APB2_RESET_TWI_SHIFT (0) +#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) + +#endif /* _SUNXI_CLOCK_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index a987e51d57..0de79a0d50 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -95,6 +95,11 @@ #define SUNXI_MALI400_BASE 0x01c40000 #define SUNXI_GMAC_BASE 0x01c50000 +#define SUNXI_DRAM_COM_BASE 0x01c62000 +#define SUNXI_DRAM_CTL_BASE 0x01c63000 +#define SUNXI_DRAM_PHY_CH1_BASE 0x01c65000 +#define SUNXI_DRAM_PHY_CH2_BASE 0x01c66000 + /* module sram */ #define SUNXI_SRAM_C_BASE 0x01d00000 @@ -105,6 +110,11 @@ #define SUNXI_MP_BASE 0x01e80000 #define SUNXI_AVG_BASE 0x01ea0000 +#define SUNXI_PRCM_BASE 0x01f01400 +#define SUNXI_R_UART_BASE 0x01f02800 +#define SUNXI_R_PIO_BASE 0x01f02c00 +#define SUNXI_P2WI_BASE 0x01f03400 + /* CoreSight Debug Module */ #define SUNXI_CSDM_BASE 0x3f500000 diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index f7f3d8c41a..7bb649950a 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -10,6 +10,7 @@ #define _SUNXI_GPIO_H #include <linux/types.h> +#include <asm/arch/cpu.h> /* * sunxi has 9 banks of gpio, they are: @@ -27,8 +28,27 @@ #define SUNXI_GPIO_G 6 #define SUNXI_GPIO_H 7 #define SUNXI_GPIO_I 8 + +/* + * This defines the number of GPIO banks for the _main_ GPIO controller. + * You should fix up the padding in struct sunxi_gpio_reg below if you + * change this. + */ #define SUNXI_GPIO_BANKS 9 +/* + * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) + * at a different register offset. + * + * sun6i has 2 banks: + * PL0 - PL8 | PM0 - PM7 + * + * sun8i has 1 bank: + * PL0 - PL11 + */ +#define SUNXI_GPIO_L 11 +#define SUNXI_GPIO_M 12 + struct sunxi_gpio { u32 cfg[4]; u32 dat; @@ -50,8 +70,9 @@ struct sunxi_gpio_reg { struct sunxi_gpio_int gpio_int; }; -#define BANK_TO_GPIO(bank) \ - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] +#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ + &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) #define GPIO_BANK(pin) ((pin) >> 5) #define GPIO_NUM(pin) ((pin) & 0x1f) @@ -75,6 +96,8 @@ struct sunxi_gpio_reg { #define SUNXI_GPIO_G_NR 32 #define SUNXI_GPIO_H_NR 32 #define SUNXI_GPIO_I_NR 32 +#define SUNXI_GPIO_L_NR 32 +#define SUNXI_GPIO_M_NR 32 #define SUNXI_GPIO_NEXT(__gpio) \ ((__gpio##_START) + (__gpio##_NR) + 0) @@ -89,6 +112,8 @@ enum sunxi_gpio_number { SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), + SUNXI_GPIO_L_START = 352, + SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), }; /* SUNXI GPIO number definitions */ @@ -101,6 +126,8 @@ enum sunxi_gpio_number { #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) +#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) /* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0 @@ -117,6 +144,8 @@ enum sunxi_gpio_number { #define SUN5I_GPB19_UART0_TX 2 #define SUN5I_GPB20_UART0_RX 2 +#define SUN5I_GPG3_SDC1 2 + #define SUN5I_GPG3_UART1_TX 4 #define SUN5I_GPG4_UART1_RX 4 @@ -125,15 +154,27 @@ enum sunxi_gpio_number { #define SUNXI_GPF0_SDC0 2 #define SUNXI_GPF2_SDC0 2 + +#ifdef CONFIG_SUN8I +#define SUNXI_GPF2_UART0_TX 3 +#define SUNXI_GPF4_UART0_RX 3 +#else #define SUNXI_GPF2_UART0_TX 4 #define SUNXI_GPF4_UART0_RX 4 +#endif #define SUN4I_GPG0_SDC1 4 #define SUN4I_GPH22_SDC1 5 +#define SUN6I_GPH20_UART0_TX 2 +#define SUN6I_GPH21_UART0_RX 2 + #define SUN4I_GPI4_SDC3 2 +#define SUN8I_GPL2_R_UART_TX 2 +#define SUN8I_GPL3_R_UART_RX 2 + /* GPIO pin pull-up/down config */ #define SUNXI_GPIO_PULL_DISABLE 0 #define SUNXI_GPIO_PULL_UP 1 diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index 53196e3b02..8a216740a7 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -43,7 +43,10 @@ struct sunxi_mmc { u32 chda; /* 0x90 */ u32 cbda; /* 0x94 */ u32 res1[26]; - u32 fifo; /* 0x100 FIFO access address */ +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) + u32 res2[64]; +#endif + u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */ }; #define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) @@ -120,5 +123,5 @@ struct sunxi_mmc { #define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) #define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) -int sunxi_mmc_init(int sdc_no); +struct mmc *sunxi_mmc_init(int sdc_no); #endif /* _SUNXI_MMC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h new file mode 100644 index 0000000000..3d3bfa6cd1 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -0,0 +1,238 @@ +/* + * Sunxi A31 Power Management Unit register definition. + * + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> + * http://linux-sunxi.org + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_PRCM_H +#define _SUNXI_PRCM_H + +#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4) +#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3) +#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1) +#define PRCM_CPUS_CFG_PRE_DIV(n) \ + __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n)) +#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8) +#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f) +#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1) +#define PRCM_CPUS_CFG_POST_DIV(n) \ + __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n)) +#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16) +#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3) +#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0 +#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1 +#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2 +#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3 +#define PRCM_CPUS_CFG_CLK_SRC_LOSC \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC) +#define PRCM_CPUS_CFG_CLK_SRC_HOSC \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC) +#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6) +#define PRCM_CPUS_CFG_CLK_SRC_PDIV \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV) + +#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0) +#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3) +#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1) +#define PRCM_APB0_RATIO_DIV(n) \ + __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n)) + +#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0) +#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1) + +#define PRCM_APB0_GATE_PIO (0x1 << 0) +#define PRCM_APB0_GATE_IR (0x1 << 1) +#define PRCM_APB0_GATE_TIMER01 (0x1 << 2) +#define PRCM_APB0_GATE_P2WI (0x1 << 3) +#define PRCM_APB0_GATE_UART (0x1 << 4) +#define PRCM_APB0_GATE_1WIRE (0x1 << 5) +#define PRCM_APB0_GATE_I2C (0x1 << 6) + +#define PRCM_APB0_RESET_PIO (0x1 << 0) +#define PRCM_APB0_RESET_IR (0x1 << 1) +#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) +#define PRCM_APB0_RESET_P2WI (0x1 << 3) +#define PRCM_APB0_RESET_UART (0x1 << 4) +#define PRCM_APB0_RESET_1WIRE (0x1 << 5) +#define PRCM_APB0_RESET_I2C (0x1 << 6) + +#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0) +#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1) +#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4) +#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \ + __PRCM_PLL_CTRL_USB_CLK_SRC(0x3) +#define __PRCM_PLL_CTRL_USB_CLK_0 0x0 +#define __PRCM_PLL_CTRL_USB_CLK_1 0x1 +#define __PRCM_PLL_CTRL_USB_CLK_2 0x2 +#define __PRCM_PLL_CTRL_USB_CLK_3 0x3 +#define PRCM_PLL_CTRL_USB_CLK_0 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0) +#define PRCM_PLL_CTRL_USB_CLK_1 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1) +#define PRCM_PLL_CTRL_USB_CLK_2 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2) +#define PRCM_PLL_CTRL_USB_CLK_3 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3) +#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12) +#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \ + __PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3) +#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \ + __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) +#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20) +#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3) +#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0 +#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1 +#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2 +#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3 +#define PRCM_PLL_CTRL_HOSC_CLK_0 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0) +#define PRCM_PLL_CTRL_HOSC_CLK_1 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1) +#define PRCM_PLL_CTRL_HOSC_CLK_2 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2) +#define PRCM_PLL_CTRL_HOSC_CLK_3 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3) +#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24) +#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0) +#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1) +#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2) +#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3) +#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */ +#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16) +#define PRCM_PLL_CTRL_LDO_OUT_MASK \ + __PRCM_PLL_CTRL_LDO_OUT(0x7) +/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */ +#define PRCM_PLL_CTRL_LDO_OUT_L(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7) +#define PRCM_PLL_CTRL_LDO_OUT_H(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7) +#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000) +#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160) +#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24) + +#define PRCM_CLK_1WIRE_GATE (0x1 << 31) + +#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0) +#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf) +#define __PRCM_CLK_MOD0_M_X(n) (n - 1) +#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n)) +#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8) +#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7) +#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16) +#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3) +#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1) +#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n)) +#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20) +#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7) +#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24) +#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7) +#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31) + +#define PRCM_APB0_RESET_PIO (0x1 << 0) +#define PRCM_APB0_RESET_IR (0x1 << 1) +#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) +#define PRCM_APB0_RESET_P2WI (0x1 << 3) +#define PRCM_APB0_RESET_UART (0x1 << 4) +#define PRCM_APB0_RESET_1WIRE (0x1 << 5) +#define PRCM_APB0_RESET_I2C (0x1 << 6) + +#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8) +#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7) +#define __PRCM_CLK_OUTD_M_X() ((n) - 1) +#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n)) +#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20) +#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7) +#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1) +#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n) +#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24) +#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3) +#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0 +#define __PRCM_CLK_OUTD_SRC_LOSC 0x1 +#define __PRCM_CLK_OUTD_SRC_HOSC 0x2 +#define __PRCM_CLK_OUTD_SRC_ERR 0x3 +#define PRCM_CLK_OUTD_SRC_LOSC2 \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2) +#define PRCM_CLK_OUTD_SRC_LOSC \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC) +#define PRCM_CLK_OUTD_SRC_HOSC \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC) +#define PRCM_CLK_OUTD_SRC_ERR \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR) +#define PRCM_CLK_OUTD_EN (0x1 << 31) + +#define PRCM_CPU0_PWROFF (0x1 << 0) +#define PRCM_CPU1_PWROFF (0x1 << 1) +#define PRCM_CPU2_PWROFF (0x1 << 2) +#define PRCM_CPU3_PWROFF (0x1 << 3) +#define PRCM_CPU_ALL_PWROFF (0xf << 0) + +#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0) +#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1) +#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2) +#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3) + +#define PRCM_VDD_GPU_PWROFF (0x1 << 0) + +#define PRCM_VDD_SYS_RESET (0x1 << 0) + +#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff) + +#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff) + +#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff) + +#ifndef __ASSEMBLY__ +struct sunxi_prcm_reg { + u32 cpus_cfg; /* 0x000 */ + u8 res0[0x8]; /* 0x004 */ + u32 apb0_ratio; /* 0x00c */ + u32 cpu0_cfg; /* 0x010 */ + u32 cpu1_cfg; /* 0x014 */ + u32 cpu2_cfg; /* 0x018 */ + u32 cpu3_cfg; /* 0x01c */ + u8 res1[0x8]; /* 0x020 */ + u32 apb0_gate; /* 0x028 */ + u8 res2[0x14]; /* 0x02c */ + u32 pll_ctrl0; /* 0x040 */ + u32 pll_ctrl1; /* 0x044 */ + u8 res3[0x8]; /* 0x048 */ + u32 clk_1wire; /* 0x050 */ + u32 clk_ir; /* 0x054 */ + u8 res4[0x58]; /* 0x058 */ + u32 apb0_reset; /* 0x0b0 */ + u8 res5[0x3c]; /* 0x0b4 */ + u32 clk_outd; /* 0x0f0 */ + u8 res6[0xc]; /* 0x0f4 */ + u32 cpu_pwroff; /* 0x100 */ + u8 res7[0xc]; /* 0x104 */ + u32 vdd_sys_pwroff; /* 0x110 */ + u8 res8[0x4]; /* 0x114 */ + u32 gpu_pwroff; /* 0x118 */ + u8 res9[0x4]; /* 0x11c */ + u32 vdd_pwr_reset; /* 0x120 */ + u8 res10[0x20]; /* 0x124 */ + u32 cpu1_pwr_clamp; /* 0x144 */ + u32 cpu2_pwr_clamp; /* 0x148 */ + u32 cpu3_pwr_clamp; /* 0x14c */ + u8 res11[0x30]; /* 0x150 */ + u32 dram_pwr; /* 0x180 */ + u8 res12[0xc]; /* 0x184 */ + u32 dram_tst; /* 0x190 */ +}; + +void prcm_apb0_enable(u32 flags); +#endif /* __ASSEMBLY__ */ +#endif /* _PRCM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h index 58e14fd0f7..03a0684c79 100644 --- a/arch/arm/include/asm/arch-sunxi/timer.h +++ b/arch/arm/include/asm/arch-sunxi/timer.h @@ -11,14 +11,10 @@ #ifndef _SUNXI_TIMER_H_ #define _SUNXI_TIMER_H_ -#define WDT_CTRL_RESTART (0x1 << 0) -#define WDT_CTRL_KEY (0x0a57 << 1) -#define WDT_MODE_EN (0x1 << 0) -#define WDT_MODE_RESET_EN (0x1 << 1) - #ifndef __ASSEMBLY__ #include <linux/types.h> +#include <asm/arch/watchdog.h> /* General purpose timer */ struct sunxi_timer { @@ -43,12 +39,6 @@ struct sunxi_64cnt { u32 hi; /* 0xa8 */ }; -/* Watchdog */ -struct sunxi_wdog { - u32 ctl; /* 0x90 */ - u32 mode; /* 0x94 */ -}; - /* Rtc */ struct sunxi_rtc { u32 ctl; /* 0x100 */ @@ -77,15 +67,20 @@ struct sunxi_timer_reg { struct sunxi_timer timer[6]; /* We have 6 timers */ u8 res2[16]; struct sunxi_avs avs; - struct sunxi_wdog wdog; - u8 res3[8]; - struct sunxi_64cnt cnt64; +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) + struct sunxi_wdog wdog; /* 0x90 */ + /* XXX the following is not accurate for sun5i/sun7i */ + struct sunxi_64cnt cnt64; /* 0xa0 */ u8 res4[0x58]; struct sunxi_rtc rtc; struct sunxi_alarm alarm; struct sunxi_tgp tgp[4]; u8 res5[8]; u32 cpu_cfg; +#else /* CONFIG_SUN6I || CONFIG_SUN8I || ... */ + u8 res3[16]; + struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ +#endif }; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h new file mode 100644 index 0000000000..ccc8fa32c4 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/watchdog.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2014 + * Chen-Yu Tsai <wens@csie.org> + * + * Watchdog register definitions + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_WATCHDOG_H_ +#define _SUNXI_WATCHDOG_H_ + +#define WDT_CTRL_RESTART (0x1 << 0) +#define WDT_CTRL_KEY (0x0a57 << 1) + +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) + +#define WDT_MODE_EN (0x1 << 0) +#define WDT_MODE_RESET_EN (0x1 << 1) + +struct sunxi_wdog { + u32 ctl; /* 0x00 */ + u32 mode; /* 0x04 */ + u32 res[2]; +}; + +#else + +#define WDT_CFG_RESET (0x1) +#define WDT_MODE_EN (0x1) + +struct sunxi_wdog { + u32 irq_en; /* 0x00 */ + u32 irq_sta; /* 0x04 */ + u32 res1[2]; + u32 ctl; /* 0x10 */ + u32 cfg; /* 0x14 */ + u32 mode; /* 0x18 */ + u32 res2; +}; + +#endif + +#endif /* _SUNXI_WATCHDOG_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h index ff773646cb..783bb3c0fa 100644 --- a/arch/arm/include/asm/arch-tegra/board.h +++ b/arch/arm/include/asm/arch-tegra/board.h @@ -24,10 +24,11 @@ void gpio_early_init(void); /* overrideable GPIO config */ * an empty stub function will be called. */ -void pinmux_init(void); /* overrideable general pinmux setup */ -void pin_mux_usb(void); /* overrideable USB pinmux setup */ -void pin_mux_spi(void); /* overrideable SPI pinmux setup */ -void pin_mux_nand(void); /* overrideable NAND pinmux setup */ -void pin_mux_display(void); /* overrideable DISPLAY pinmux setup */ +void pinmux_init(void); /* overridable general pinmux setup */ +void pin_mux_usb(void); /* overridable USB pinmux setup */ +void pin_mux_spi(void); /* overridable SPI pinmux setup */ +void pin_mux_nand(void); /* overridable NAND pinmux setup */ +void pin_mux_mmc(void); /* overridable mmc pinmux setup */ +void pin_mux_display(void); /* overridable DISPLAY pinmux setup */ #endif diff --git a/arch/arm/include/asm/arch-uniphier/platdevice.h b/arch/arm/include/asm/arch-uniphier/platdevice.h new file mode 100644 index 0000000000..cdf7d132d4 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/platdevice.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_PLATDEVICE_H +#define ARCH_PLATDEVICE_H + +#include <dm/platdata.h> +#include <dm/platform_data/serial-uniphier.h> + +#define SERIAL_DEVICE(n, ba, clk) \ +static struct uniphier_serial_platform_data serial_device##n = { \ + .base = ba, \ + .uartclk = clk \ +}; \ +U_BOOT_DEVICE(serial##n) = { \ + .name = DRIVER_NAME, \ + .platdata = &serial_device##n \ +}; + +#endif /* ARCH_PLATDEVICE_H */ diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h index 5d25d04c3b..839af54d48 100644 --- a/arch/arm/include/asm/omap_gpio.h +++ b/arch/arm/include/asm/omap_gpio.h @@ -23,6 +23,21 @@ #include <asm/arch/cpu.h> +enum gpio_method { + METHOD_GPIO_24XX = 4, +}; + +#ifdef CONFIG_DM_GPIO + +/* Information about a GPIO bank */ +struct omap_gpio_platdata { + int bank_index; + ulong base; /* address of registers in physical memory */ + enum gpio_method method; +}; + +#else + struct gpio_bank { void *base; int method; @@ -30,8 +45,6 @@ struct gpio_bank { extern const struct gpio_bank *const omap_gpio_bank; -#define METHOD_GPIO_24XX 4 - /** * Check if gpio is valid. * @@ -39,4 +52,6 @@ extern const struct gpio_bank *const omap_gpio_bank; * @return 1 if ok, 0 on error */ int gpio_is_valid(int gpio); +#endif + #endif /* _GPIO_H_ */ diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index b16694c72f..f97f3dd149 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -45,4 +45,19 @@ void reset_timer_masked (void); ulong get_timer_masked (void); void udelay_masked (unsigned long usec); +/* calls to c from vectors.S */ +void bad_mode(void); +void do_undefined_instruction(struct pt_regs *pt_regs); +void do_software_interrupt(struct pt_regs *pt_regs); +void do_prefetch_abort(struct pt_regs *pt_regs); +void do_data_abort(struct pt_regs *pt_regs); +void do_not_used(struct pt_regs *pt_regs); +#ifdef CONFIG_ARM64 +void do_fiq(struct pt_regs *pt_regs, unsigned int esr); +void do_irq(struct pt_regs *pt_regs, unsigned int esr); +#else +void do_fiq(struct pt_regs *pt_regs); +void do_irq(struct pt_regs *pt_regswq); +#endif + #endif /* _U_BOOT_ARM_H_ */ diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 76adaf3aa4..f6062557e6 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -34,6 +34,7 @@ #include <onenand_uboot.h> #include <mmc.h> #include <scsi.h> +#include <status_led.h> #include <libfdt.h> #include <fdtdec.h> #include <post.h> @@ -63,25 +64,15 @@ extern void dataflash_print_info(void); ************************************************************************ * May be supplied by boards if desired */ -inline void __coloured_LED_init(void) {} -void coloured_LED_init(void) - __attribute__((weak, alias("__coloured_LED_init"))); -inline void __red_led_on(void) {} -void red_led_on(void) __attribute__((weak, alias("__red_led_on"))); -inline void __red_led_off(void) {} -void red_led_off(void) __attribute__((weak, alias("__red_led_off"))); -inline void __green_led_on(void) {} -void green_led_on(void) __attribute__((weak, alias("__green_led_on"))); -inline void __green_led_off(void) {} -void green_led_off(void) __attribute__((weak, alias("__green_led_off"))); -inline void __yellow_led_on(void) {} -void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on"))); -inline void __yellow_led_off(void) {} -void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off"))); -inline void __blue_led_on(void) {} -void blue_led_on(void) __attribute__((weak, alias("__blue_led_on"))); -inline void __blue_led_off(void) {} -void blue_led_off(void) __attribute__((weak, alias("__blue_led_off"))); +__weak void coloured_LED_init(void) {} +__weak void red_led_on(void) {} +__weak void red_led_off(void) {} +__weak void green_led_on(void) {} +__weak void green_led_off(void) {} +__weak void yellow_led_on(void) {} +__weak void yellow_led_off(void) {} +__weak void blue_led_on(void) {} +__weak void blue_led_off(void) {} /* ************************************************************************ @@ -198,27 +189,21 @@ static int arm_pci_init(void) */ typedef int (init_fnc_t) (void); -void __dram_init_banksize(void) +__weak void dram_init_banksize(void) { gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; } -void dram_init_banksize(void) - __attribute__((weak, alias("__dram_init_banksize"))); -int __arch_cpu_init(void) +__weak int arch_cpu_init(void) { return 0; } -int arch_cpu_init(void) - __attribute__((weak, alias("__arch_cpu_init"))); -int __power_init_board(void) +__weak int power_init_board(void) { return 0; } -int power_init_board(void) - __attribute__((weak, alias("__power_init_board"))); /* Record the board_init_f() bootstage (after arch_cpu_init()) */ static int mark_bootstage(void) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 39fe7a17fc..0d19c8ae23 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -15,6 +15,7 @@ #include <common.h> #include <command.h> #include <image.h> +#include <vxworks.h> #include <u-boot/zlib.h> #include <asm/byteorder.h> #include <libfdt.h> diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index f6b7c03578..9019736d2c 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -21,6 +21,7 @@ #include <common.h> #include <asm/proc-armv/ptrace.h> +#include <asm/u-boot-arm.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 329bb3ab35..338bab19e4 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -85,12 +85,25 @@ car_init_ret: /* Align global data to 16-byte boundary */ andl $0xfffffff0, %esp + /* Zero the global data since it won't happen later */ + xorl %eax, %eax + movl $GENERATED_GBL_DATA_SIZE, %ecx + movl %esp, %edi + rep stosb + /* Setup first parameter to setup_gdt */ movl %esp, %eax /* Reserve space for global descriptor table */ subl $X86_GDT_SIZE, %esp +#if defined(CONFIG_SYS_MALLOC_F_LEN) + subl $CONFIG_SYS_MALLOC_F_LEN, %esp + movl %eax, %edx + addl $GD_MALLOC_BASE, %edx + movl %esp, (%edx) +#endif + /* Align temporary global descriptor table to 16-byte boundary */ andl $0xfffffff0, %esp diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi index 4862a59704..c8dc4cec3c 100644 --- a/arch/x86/dts/coreboot.dtsi +++ b/arch/x86/dts/coreboot.dtsi @@ -1,13 +1,14 @@ /include/ "skeleton.dtsi" / { - aliases { - console = "/serial"; + chosen { + stdout-path = "/serial"; }; serial { - compatible = "ns16550"; - reg-shift = <1>; + compatible = "coreboot-uart"; + reg = <0x3f8 0x10>; + reg-shift = <0>; io-mapped = <1>; multiplier = <1>; baudrate = <115200>; diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts index 67ce52a102..f2fcb3927c 100644 --- a/arch/x86/dts/link.dts +++ b/arch/x86/dts/link.dts @@ -12,7 +12,23 @@ silent_console = <0>; }; - gpio: gpio {}; + gpioa { + compatible = "intel,ich6-gpio"; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + reg = <0x40 0x10>; + bank-name = "C"; + }; serial { reg = <0x3f8 8>; diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h new file mode 100644 index 0000000000..3ec1816833 --- /dev/null +++ b/arch/x86/include/asm/arch-coreboot/gpio.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2014, Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_GPIO_H_ +#define _X86_ARCH_GPIO_H_ + +struct ich6_bank_platdata { + uint32_t base_addr; + const char *bank_name; +}; + +#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index fe09f31515..8bda414dbd 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -6,6 +6,7 @@ #ifndef _X86_GPIO_H_ #define _X86_GPIO_H_ +#include <asm/arch/gpio.h> #include <asm-generic/gpio.h> #endif /* _X86_GPIO_H_ */ diff --git a/arch/x86/include/asm/ibmpc.h b/arch/x86/include/asm/ibmpc.h index 0f9665f549..e6d183b479 100644 --- a/arch/x86/include/asm/ibmpc.h +++ b/arch/x86/include/asm/ibmpc.h @@ -18,14 +18,4 @@ #define SYSCTLA 0x92 #define SLAVE_PIC 0xa0 -#if 1 -#define UART0_BASE 0x3f8 -#define UART1_BASE 0x2f8 -#else -/* FixMe: uarts swapped */ -#define UART0_BASE 0x2f8 -#define UART1_BASE 0x3f8 -#endif - - #endif diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 2f0e92f123..b1902834e8 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -282,7 +282,6 @@ void boot_zimage(void *setup_base, void *load_address) :: [kernel_entry]"a"(load_address), [boot_params] "S"(setup_base), "b"(0), "D"(0) - : "%ebp" ); } |