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-rw-r--r--arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c16
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c3
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fdt.c23
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c9
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h6
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/soc.h14
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h2
7 files changed, 63 insertions, 10 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index bb169aaaf4..df64f5415a 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -68,12 +68,18 @@ static void __secure ls1_deepsleep_irq_cfg(void)
ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
/*
- * Workaround: There is bug of register ippdexpcr1, when read it always
- * returns zero, so its value is saved to a scrachpad register to be
- * read, that is why we don't read it from register ippdexpcr1 itself.
+ * Workaround of errata A-008646
+ * Errata states that read to register ippdexpcr1 always returns
+ * zero irrespective of what value is written into it. So its value
+ * is first saved to a spare register and then read from it
*/
- ippdexpcr1 = in_le32(&scfg->sparecr[7]);
- out_be32(&rcpm->ippdexpcr1, ippdexpcr1);
+ ippdexpcr1 = in_be32(&scfg->sparecr[7]);
+
+ /*
+ * To allow OCRAM to be used as wakeup source in deep sleep,
+ * do not power it down.
+ */
+ out_be32(&rcpm->ippdexpcr1, ippdexpcr1 | RCPM_IPPDEXPCR1_OCRAM1);
if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index a5d0b5370f..8fd6c751c6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -59,6 +59,9 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+ CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
+ CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
+ CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 19917b207a..e993209593 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -401,6 +401,26 @@ void fdt_fixup_remove_jr(void *blob)
}
#endif
+#ifdef CONFIG_ARCH_LS1028A
+static void fdt_disable_multimedia(void *blob, unsigned int svr)
+{
+ int off;
+
+ if (IS_MULTIMEDIA_EN(svr))
+ return;
+
+ /* Disable eDP/LCD node */
+ off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500");
+ if (off != -FDT_ERR_NOTFOUND)
+ fdt_status_disabled(blob, off);
+
+ /* Disable GPU node */
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
+ if (off != -FDT_ERR_NOTFOUND)
+ fdt_status_disabled(blob, off);
+}
+#endif
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -462,4 +482,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
fdt_fixup_msi(blob);
#endif
+#ifdef CONFIG_ARCH_LS1028A
+ fdt_disable_multimedia(blob, svr);
+#endif
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3fd34e3a43..1f1869e8cf 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -627,10 +627,19 @@ void fsl_lsch2_early_init_f(void)
#endif
#endif
/* Make SEC reads and writes snoopable */
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
+ SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+ SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+ SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+ SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
+ SCFG_SNPCNFGCR_SATAWRSNP);
+#else
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP |
SCFG_SNPCNFGCR_SATARDSNP |
SCFG_SNPCNFGCR_SATAWRSNP);
+#endif
/*
* Enable snoop requests and DVM message requests for
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 3a59abb10e..862ec2e2f1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -409,6 +409,12 @@ struct ccsr_gur {
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
+#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000
+#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000
+#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000
+#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000
+#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000
+#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000
/* RGMIIPCR bit definitions*/
#define SCFG_RGMIIPCR_EN_AUTO BIT(3)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 234440b5fe..35719d747b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
* Copyright 2015 Freescale Semiconductor
*/
@@ -83,6 +83,9 @@ enum boot_src get_boot_src(void);
/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
#define SVR_LS1043A_P23 0x879202
#define SVR_LS1023A_P23 0x87920A
+#define SVR_LS1017A 0x870B24
+#define SVR_LS1018A 0x870B20
+#define SVR_LS1027A 0x870B04
#define SVR_LS1028A 0x870B00
#define SVR_LS1046A 0x870700
#define SVR_LS1026A 0x870708
@@ -100,9 +103,9 @@ enum boot_src get_boot_src(void);
#define SVR_LS2044A 0x870930
#define SVR_LS2081A 0x870918
#define SVR_LS2041A 0x870914
-#define SVR_LX2160A 0x873601
-#define SVR_LX2120A 0x873621
-#define SVR_LX2080A 0x873603
+#define SVR_LX2160A 0x873600
+#define SVR_LX2120A 0x873620
+#define SVR_LX2080A 0x873602
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
@@ -112,6 +115,9 @@ enum boot_src get_boot_src(void);
#ifdef CONFIG_ARCH_LX2160A
#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
#endif
+#ifdef CONFIG_ARCH_LS1028A
+#define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1))
+#endif
#define IS_SVR_REV(svr, maj, min) \
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
#define SVR_DEV(svr) ((svr) >> 8)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 137cd61804..f2ba182346 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -155,7 +155,7 @@ struct ccsr_gur {
#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
-#define SCFG_QSPI_CLKSEL 0xc0100000
+#define SCFG_QSPI_CLKSEL 0x50100000
#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
#define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000
#define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000
generated by cgit (git 2.34.1) at 2025-01-24 23:45:00 +0000