diff options
Diffstat (limited to 'arch')
55 files changed, 1507 insertions, 273 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1bcf345028..8e67e1c587 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -475,7 +475,7 @@ config TPL_USE_ARCH_MEMSET config SET_STACK_SIZE bool "Enable an option to set max stack size that can be used" - default y if ARCH_VERSAL || ARCH_ZYNQMP + default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ help This will enable an option to set max stack size that can be used by U-Boot. @@ -484,6 +484,7 @@ config STACK_SIZE hex "Define max stack size that can be used by U-Boot" depends on SET_STACK_SIZE default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP + default 0x1000000 if ARCH_ZYNQ help Define Max stack size that can be used by U-Boot so that the initrd_high will be calculated as base stack pointer minus this diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index b25639183f..2f75b2cdd3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -46,6 +46,7 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A050382 + select RESV_RAM if GIC_V3_ITS imply PANIC_HANG config ARCH_LS1043A @@ -152,6 +153,7 @@ config ARCH_LS1088A select SYS_I2C_MXC_I2C2 if !TFABOOT select SYS_I2C_MXC_I2C3 if !TFABOOT select SYS_I2C_MXC_I2C4 if !TFABOOT + select RESV_RAM if GIC_V3_ITS imply SCSI imply PANIC_HANG @@ -202,6 +204,7 @@ config ARCH_LS2080A select SYS_I2C_MXC_I2C2 if !TFABOOT select SYS_I2C_MXC_I2C3 if !TFABOOT select SYS_I2C_MXC_I2C4 if !TFABOOT + select RESV_RAM if GIC_V3_ITS imply DISTRO_DEFAULTS imply PANIC_HANG @@ -229,6 +232,7 @@ config ARCH_LX2160A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F select SYS_I2C_MXC + select RESV_RAM if GIC_V3_ITS imply DISTRO_DEFAULTS imply PANIC_HANG imply SCSI diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index b443894453..b3f5c2f641 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1156,8 +1156,10 @@ int arch_early_init_r(void) fsl_rgmii_init(); #endif #ifdef CONFIG_FMAN_ENET +#ifndef CONFIG_DM_ETH fman_enet_init(); #endif +#endif #ifdef CONFIG_SYS_DPAA_QBMAN setup_qbman_portals(); #endif @@ -1379,7 +1381,7 @@ static int tfa_dram_init_banksize(void) if (i > 0) ret = 0; -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bd->bi_dram[2].size >= @@ -1402,7 +1404,7 @@ static int tfa_dram_init_banksize(void) board_reserve_ram_top(gd->bd->bi_dram[0].size); } } -#endif /* CONFIG_FSL_MC_ENET */ +#endif /* CONFIG_RESV_RAM */ return ret; } @@ -1465,7 +1467,7 @@ int dram_init_banksize(void) } #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bd->bi_dram[2].size >= @@ -1488,7 +1490,7 @@ int dram_init_banksize(void) board_reserve_ram_top(gd->bd->bi_dram[0].size); } } -#endif /* CONFIG_FSL_MC_ENET */ +#endif /* CONFIG_RESV_RAM */ #ifdef CONFIG_SYS_DP_DDR_BASE_PHY #ifdef CONFIG_SYS_DDR_BLOCK3_BASE diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 077438765c..3bbad827cb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -471,6 +471,10 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); +#ifdef CONFIG_GIC_V3_ITS + ls_gic_rd_tables_init(blob); +#endif + #if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4) ft_pci_setup(blob, bd); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d0e10cb007..28bb1d7401 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -6,10 +6,12 @@ #include <common.h> #include <clock_legacy.h> +#include <cpu_func.h> #include <env.h> #include <fsl_immap.h> #include <fsl_ifc.h> #include <init.h> +#include <linux/sizes.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> #include <asm/io.h> @@ -17,6 +19,7 @@ #include <asm/arch-fsl-layerscape/config.h> #include <asm/arch-fsl-layerscape/ns_access.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/gic-v3.h> #ifdef CONFIG_LAYERSCAPE_NS_ACCESS #include <fsl_csu.h> #endif @@ -30,9 +33,50 @@ #include <fsl_immap.h> #ifdef CONFIG_TFABOOT #include <env_internal.h> +#endif +#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS) DECLARE_GLOBAL_DATA_PTR; #endif +#ifdef CONFIG_GIC_V3_ITS +#define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K) +#define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K) +#define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \ + PROPTABLE_MAX_SZ, SZ_1M) +static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size) +{ + u32 phandle; + int err; + struct fdt_memory gic_rd_tables; + + gic_rd_tables.start = base; + gic_rd_tables.end = base + size - 1; + err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables, + &phandle); + if (err < 0) + debug("%s: failed to add reserved memory: %d\n", __func__, err); + + return err; +} + +int ls_gic_rd_tables_init(void *blob) +{ + u64 gic_lpi_base; + int ret; + + gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K); + ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE); + if (ret) + return ret; + + ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores()); + if (ret) + debug("%s: failed to init gic-lpi-tables\n", __func__); + + return ret; +} +#endif + bool soc_has_dp_ddr(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ed47fff571..2c123bd6da 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -377,7 +377,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls1088a-rdb.dtb \ fsl-ls1088a-qds.dtb \ fsl-ls1028a-rdb.dtb \ - fsl-ls1028a-qds.dtb \ + fsl-ls1028a-qds-duart.dtb \ + fsl-ls1028a-qds-lpuart.dtb \ fsl-lx2160a-rdb.dtb \ fsl-lx2160a-qds.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ diff --git a/arch/arm/dts/fsl-ls1028a-qds-duart.dts b/arch/arm/dts/fsl-ls1028a-qds-duart.dts new file mode 100644 index 0000000000..83264e0f54 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-duart.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Freescale Layerscape-1028AQDS family SoC. + * + * Copyright 2020 NXP + */ + +/dts-v1/; +#include "fsl-ls1028a-qds.dtsi" + +/ { + chosen { + stdout-path = &serial0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts new file mode 100644 index 0000000000..063857b2f2 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Freescale Layerscape-1028AQDS family SoC. + * + * Copyright 2020 NXP + */ + +/dts-v1/; +#include "fsl-ls1028a-qds.dtsi" + +/ { + chosen { + stdout-path = &lpuart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dtsi index 029a8e386b..4f56f40bd3 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dts +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -151,6 +151,10 @@ status = "okay"; }; +&lpuart0 { + status = "okay"; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 5365bfb1a8..9911690e5c 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -240,6 +240,66 @@ status = "disabled"; }; + lpuart0: serial@2260000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2260000 0x0 0x1000>; + interrupts = <0 232 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; + + lpuart1: serial@2270000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2270000 0x0 0x1000>; + interrupts = <0 233 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; + + lpuart2: serial@2280000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2280000 0x0 0x1000>; + interrupts = <0 234 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; + + lpuart3: serial@2290000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2290000 0x0 0x1000>; + interrupts = <0 235 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; + + lpuart4: serial@22a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x22a0000 0x0 0x1000>; + interrupts = <0 236 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; + + lpuart5: serial@22b0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x22b0000 0x0 0x1000>; + interrupts = <0 237 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + }; + usb1: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; diff --git a/arch/arm/dts/fsl-ls1043-post.dtsi b/arch/arm/dts/fsl-ls1043-post.dtsi new file mode 100644 index 0000000000..e4eab9e5c6 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043-post.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 device tree nodes for ls1043 + * + * Copyright 2015-2016 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +&soc { + +/* include used FMan blocks */ +#include "qoriq-fman3-0.dtsi" +#include "qoriq-fman3-0-1g-0.dtsi" +#include "qoriq-fman3-0-1g-1.dtsi" +#include "qoriq-fman3-0-1g-2.dtsi" +#include "qoriq-fman3-0-1g-3.dtsi" +#include "qoriq-fman3-0-1g-4.dtsi" +#include "qoriq-fman3-0-1g-5.dtsi" +#include "qoriq-fman3-0-10g-0.dtsi" + +}; + +&fman0 { + fsl,erratum-a050385; + + /* these aliases provide the FMan ports mapping */ + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet4: ethernet@e8000 { + }; + + enet5: ethernet@ea000 { + }; + + enet6: ethernet@f0000 { + }; +}; diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts index 721b158169..6e4ea5b40c 100644 --- a/arch/arm/dts/fsl-ls1043a-rdb.dts +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -3,6 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1043A family SoC. * * Copyright (C) 2015, Freescale Semiconductor + * Copyright 2020 NXP * * Mingkai Hu <Mingkai.hu@freescale.com> */ @@ -98,3 +99,83 @@ &duart1 { status = "okay"; }; + +#include "fsl-ls1043-post.dtsi" + +&fman0 { + ethernet@e0000 { + phy-handle = <&qsgmii_phy1>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + ethernet@e2000 { + phy-handle = <&qsgmii_phy2>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-txid"; + status = "okay"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-txid"; + status = "okay"; + }; + + ethernet@e8000 { + phy-handle = <&qsgmii_phy3>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + ethernet@ea000 { + phy-handle = <&qsgmii_phy4>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + ethernet@f0000 { /* 10GEC1 */ + phy-handle = <&aqr105_phy>; + phy-connection-type = "xgmii"; + status = "okay"; + }; + + mdio@fc000 { + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + qsgmii_phy1: ethernet-phy@4 { + reg = <0x4>; + }; + + qsgmii_phy2: ethernet-phy@5 { + reg = <0x5>; + }; + + qsgmii_phy3: ethernet-phy@6 { + reg = <0x6>; + }; + + qsgmii_phy4: ethernet-phy@7 { + reg = <0x7>; + }; + }; + + mdio@fd000 { + aqr105_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 132 4>; + reg = <0x1>; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index b159c3ca73..0a959f0f2d 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -31,7 +31,7 @@ interrupts = <1 9 0xf08>; }; - soc { + soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm/dts/fsl-ls1046-post.dtsi b/arch/arm/dts/fsl-ls1046-post.dtsi new file mode 100644 index 0000000000..2dac6a05f7 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046-post.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 device tree nodes for ls1046 + * + * Copyright 2015-2016 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +&soc { + +/* include used FMan blocks */ +#include "qoriq-fman3-0.dtsi" +#include "qoriq-fman3-0-1g-0.dtsi" +#include "qoriq-fman3-0-1g-1.dtsi" +#include "qoriq-fman3-0-1g-2.dtsi" +#include "qoriq-fman3-0-1g-3.dtsi" +#include "qoriq-fman3-0-1g-4.dtsi" +#include "qoriq-fman3-0-1g-5.dtsi" +#include "qoriq-fman3-0-10g-0.dtsi" +#include "qoriq-fman3-0-10g-1.dtsi" +}; + +&fman0 { + /* these aliases provide the FMan ports mapping */ + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet4: ethernet@e8000 { + }; + + enet5: ethernet@ea000 { + }; + + enet6: ethernet@f0000 { + }; + + enet7: ethernet@f2000 { + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index 83e34ab02a..cac65a7afa 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -3,6 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright 2016, Freescale Semiconductor + * Copyright 2020 NXP * * Mingkai Hu <Mingkai.hu@freescale.com> */ @@ -51,3 +52,69 @@ &i2c3 { status = "okay"; }; + +#include "fsl-ls1046-post.dtsi" + +&fman0 { + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; + status = "okay"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; + status = "okay"; + }; + + ethernet@e8000 { + phy-handle = <&sgmii_phy1>; + phy-connection-type = "sgmii"; + status = "okay"; + }; + + ethernet@ea000 { + phy-handle = <&sgmii_phy2>; + phy-connection-type = "sgmii"; + status = "okay"; + }; + + ethernet@f0000 { /* 10GEC1 */ + phy-handle = <&aqr106_phy>; + phy-connection-type = "xgmii"; + status = "okay"; + }; + + ethernet@f2000 { /* 10GEC2 */ + fixed-link = <0 1 1000 0 0>; + phy-connection-type = "xgmii"; + status = "okay"; + }; + + mdio@fc000 { + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy1: ethernet-phy@3 { + reg = <0x3>; + }; + + sgmii_phy2: ethernet-phy@4 { + reg = <0x4>; + }; + }; + + mdio@fd000 { + aqr106_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 131 4>; + reg = <0x0>; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index fdf93fd268..4e91d5c995 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -31,7 +31,7 @@ interrupts = <1 9 0xf08>; }; - soc { + soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts index 0fe351973d..46a5780547 100644 --- a/arch/arm/dts/fsl-ls1088a-rdb.dts +++ b/arch/arm/dts/fsl-ls1088a-rdb.dts @@ -17,6 +17,108 @@ }; }; +&dpmac1 { + status = "okay"; + phy-connection-type = "xgmii"; +}; + +&dpmac2 { + status = "okay"; + phy-handle = <&mdio2_phy1>; + phy-connection-type = "xgmii"; +}; + +&dpmac3 { + status = "okay"; + phy-handle = <&mdio1_phy5>; + phy-connection-type = "qsgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&mdio1_phy6>; + phy-connection-type = "qsgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&mdio1_phy7>; + phy-connection-type = "qsgmii"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&mdio1_phy8>; + phy-connection-type = "qsgmii"; +}; + +&dpmac7 { + status = "okay"; + phy-handle = <&mdio1_phy1>; + phy-connection-type = "qsgmii"; +}; + +&dpmac8 { + status = "okay"; + phy-handle = <&mdio1_phy2>; + phy-connection-type = "qsgmii"; +}; + +&dpmac9 { + status = "okay"; + phy-handle = <&mdio1_phy3>; + phy-connection-type = "qsgmii"; +}; + +&dpmac10 { + status = "okay"; + phy-handle = <&mdio1_phy4>; + phy-connection-type = "qsgmii"; +}; + +&emdio1 { + status = "okay"; + + /* Freescale F104 PHY1 */ + mdio1_phy1: emdio1_phy@1 { + reg = <0x1c>; + }; + mdio1_phy2: emdio1_phy@2 { + reg = <0x1d>; + }; + mdio1_phy3: emdio1_phy@3 { + reg = <0x1e>; + }; + mdio1_phy4: emdio1_phy@4 { + reg = <0x1f>; + }; + + /* F104 PHY2 */ + mdio1_phy5: emdio1_phy@5 { + reg = <0x0c>; + }; + mdio1_phy6: emdio1_phy@6 { + reg = <0x0d>; + }; + mdio1_phy7: emdio1_phy@7 { + reg = <0x0e>; + }; + mdio1_phy8: emdio1_phy@8 { + reg = <0x0f>; + }; +}; + +&emdio2 { + status = "okay"; + + /* Aquantia AQR105 10G PHY */ + mdio2_phy1: emdio2_phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 2 0x4>; + reg = <0x0>; + }; +}; + &i2c0 { status = "okay"; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index abc8b21a11..133cacb93e 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -82,12 +82,6 @@ interrupts = <0 32 0x1>; /* edge triggered */ }; - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - }; - dspi: dspi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; @@ -197,4 +191,100 @@ method = "smc"; }; + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc", "simple-mfd"; + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + #address-cells = <3>; + #size-cells = <1>; + + /* + * Region type 0x0 - MC portals + * Region type 0x1 - QBMAN portals + */ + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; + + dpmacs { + compatible = "simple-mfd"; + #address-cells = <1>; + #size-cells = <0>; + + dpmac1: dpmac@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x1>; + status = "disabled"; + }; + + dpmac2: dpmac@2 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x2>; + status = "disabled"; + }; + + dpmac3: dpmac@3 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x3>; + status = "disabled"; + }; + + dpmac4: dpmac@4 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x4>; + status = "disabled"; + }; + + dpmac5: dpmac@5 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x5>; + status = "disabled"; + }; + + dpmac6: dpmac@6 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x6>; + status = "disabled"; + }; + + dpmac7: dpmac@7 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x7>; + status = "disabled"; + }; + + dpmac8: dpmac@8 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x8>; + status = "disabled"; + }; + + dpmac9: dpmac@9 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x9>; + status = "disabled"; + }; + + dpmac10: dpmac@a { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xa>; + status = "disabled"; + }; + }; + }; + + emdio1: mdio@8B96000 { + compatible = "fsl,ls-mdio"; + reg = <0x0 0x8B96000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emdio2: mdio@8B97000 { + compatible = "fsl,ls-mdio"; + reg = <0x0 0x8B97000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 99ed33af95..fb5777e268 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -50,12 +50,6 @@ interrupts = <0 32 0x1>; /* edge triggered */ }; - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - }; - i2c0: i2c@2000000 { status = "disabled"; compatible = "fsl,vf610-i2c"; @@ -200,4 +194,88 @@ status = "disabled"; }; + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc", "simple-mfd"; + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + #address-cells = <3>; + #size-cells = <1>; + + /* + * Region type 0x0 - MC portals + * Region type 0x1 - QBMAN portals + */ + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; + + dpmacs { + compatible = "simple-mfd"; + #address-cells = <1>; + #size-cells = <0>; + + dpmac1: dpmac@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x1>; + status = "disabled"; + }; + + dpmac2: dpmac@2 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x2>; + status = "disabled"; + }; + + dpmac3: dpmac@3 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x3>; + status = "disabled"; + }; + + dpmac4: dpmac@4 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x4>; + status = "disabled"; + }; + + dpmac5: dpmac@5 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x5>; + status = "disabled"; + }; + + dpmac6: dpmac@6 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x6>; + status = "disabled"; + }; + + dpmac7: dpmac@7 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x7>; + status = "disabled"; + }; + + dpmac8: dpmac@8 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x8>; + status = "disabled"; + }; + }; + }; + + emdio1: mdio@8B96000 { + compatible = "fsl,ls-mdio"; + reg = <0x0 0x8B96000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emdio2: mdio@8B97000 { + compatible = "fsl,ls-mdio"; + reg = <0x0 0x8B97000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts index 72b2177b70..16b9aeec96 100644 --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts @@ -21,6 +21,94 @@ }; }; +&dpmac1 { + status = "okay"; + phy-handle = <&mdio1_phy1>; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-handle = <&mdio1_phy2>; + phy-connection-type = "xfi"; +}; + +&dpmac3 { + status = "okay"; + phy-handle = <&mdio1_phy3>; + phy-connection-type = "xfi"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&mdio1_phy4>; + phy-connection-type = "xfi"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&mdio2_phy1>; + phy-connection-type = "xfi"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&mdio2_phy2>; + phy-connection-type = "xfi"; +}; + +&dpmac7 { + status = "okay"; + phy-handle = <&mdio2_phy3>; + phy-connection-type = "xfi"; +}; + +&dpmac8 { + status = "okay"; + phy-handle = <&mdio2_phy4>; + phy-connection-type = "xfi"; +}; + +&emdio1 { + status = "okay"; + + /* CS4340 PHYs */ + mdio1_phy1: emdio1_phy@1 { + reg = <0x10>; + }; + mdio1_phy2: emdio1_phy@2 { + reg = <0x11>; + }; + mdio1_phy3: emdio1_phy@3 { + reg = <0x12>; + }; + mdio1_phy4: emdio1_phy@4 { + reg = <0x13>; + }; +}; + +&emdio2 { + status = "okay"; + + /* AQR405 PHYs */ + mdio2_phy1: emdio2_phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + mdio2_phy2: emdio2_phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + mdio2_phy3: emdio2_phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + mdio2_phy4: emdio2_phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; +}; + &dspi { bus-num = <0>; status = "okay"; diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index 87617ca51f..d787778de8 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -21,6 +21,58 @@ }; }; +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac17 { + status = "okay"; + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + status = "okay"; + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; + +&emdio1 { + status = "okay"; + rgmii_phy1: ethernet-phy@1 { + /* AR8035 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-id004d.d072"; + reg = <0x1>; + /* Poll mode - no "interrupts" property defined */ + }; + rgmii_phy2: ethernet-phy@2 { + /* AR8035 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-id004d.d072"; + reg = <0x2>; + /* Poll mode - no "interrupts" property defined */ + }; + aquantia_phy1: ethernet-phy@4 { + /* AQR107 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x4>; + }; + aquantia_phy2: ethernet-phy@5 { + /* AQR107 PHY - "compatible" property not strictly needed */ + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x5>; + }; +}; + &esdhc0 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 42ce4379ec..17ecdc569b 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -363,4 +363,69 @@ bus-range = <0x0 0xff>; ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; }; + + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc", "simple-mfd"; + reg = <0x00000008 0x0c000000 0 0x40>, + <0x00000000 0x08340000 0 0x40000>; + #address-cells = <3>; + #size-cells = <1>; + + /* + * Region type 0x0 - MC portals + * Region type 0x1 - QBMAN portals + */ + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; + + dpmacs { + compatible = "simple-mfd"; + #address-cells = <1>; + #size-cells = <0>; + + dpmac3: dpmac@3 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x3>; + status = "disabled"; + }; + + dpmac4: dpmac@4 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x4>; + status = "disabled"; + }; + + dpmac17: dpmac@11 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x11>; + status = "disabled"; + }; + + dpmac18: dpmac@12 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x12>; + status = "disabled"; + }; + }; + }; + + /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ + emdio1: mdio@8b96000 { + compatible = "fsl,ls-mdio"; + reg = <0x0 0x8b96000 0x0 0x1000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */ + emdio2: mdio@8b97000 { + compatible = "fsl,ls-mdio"; + reg = <0x0 0x8b97000 0x0 0x1000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/qoriq-fman3-0-10g-0.dtsi b/arch/arm/dts/qoriq-fman3-0-10g-0.dtsi new file mode 100644 index 0000000000..8f4776e883 --- /dev/null +++ b/arch/arm/dts/qoriq-fman3-0-10g-0.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 10g port #0 device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +fman@1a00000 { + fman0_rx_0x10: port@90000 { + cell-index = <0x10>; + compatible = "fsl,fman-v3-port-rx"; + reg = <0x90000 0x1000>; + fsl,fman-10g-port; + }; + + fman0_tx_0x30: port@b0000 { + cell-index = <0x30>; + compatible = "fsl,fman-v3-port-tx"; + reg = <0xb0000 0x1000>; + fsl,fman-10g-port; + }; + + ethernet@f0000 { + cell-index = <0x8>; + compatible = "fsl,fman-memac"; + reg = <0xf0000 0x1000>; + fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>; + pcsphy-handle = <&pcsphy6>; + status = "disabled"; + }; + + mdio@f1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + reg = <0xf1000 0x1000>; + + pcsphy6: ethernet-phy@0 { + reg = <0x0>; + }; + }; +}; diff --git a/arch/arm/dts/qoriq-fman3-0-10g-1.dtsi b/arch/arm/dts/qoriq-fman3-0-10g-1.dtsi new file mode 100644 index 0000000000..b5eb22f6a9 --- /dev/null +++ b/arch/arm/dts/qoriq-fman3-0-10g-1.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 10g port #1 device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +fman@1a00000 { + fman0_rx_0x11: port@91000 { + cell-index = <0x11>; + compatible = "fsl,fman-v3-port-rx"; + reg = <0x91000 0x1000>; + fsl,fman-10g-port; + }; + + fman0_tx_0x31: port@b1000 { + cell-index = <0x31>; + compatible = "fsl,fman-v3-port-tx"; + reg = <0xb1000 0x1000>; + fsl,fman-10g-port; + }; + + ethernet@f2000 { + cell-index = <0x9>; + compatible = "fsl,fman-memac"; + reg = <0xf2000 0x1000>; + fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>; + pcsphy-handle = <&pcsphy7>; + status = "disabled"; + }; + + mdio@f3000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + reg = <0xf3000 0x1000>; + + pcsphy7: ethernet-phy@0 { + reg = <0x0>; + }; + }; +}; diff --git a/arch/arm/dts/qoriq-fman3-0-1g-0.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-0.dtsi new file mode 100644 index 0000000000..4264d47709 --- /dev/null +++ b/arch/arm/dts/qoriq-fman3-0-1g-0.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 1g port #0 device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +fman@1a00000 { + fman0_rx_0x08: port@88000 { + cell-index = <0x8>; + compatible = "fsl,fman-v3-port-rx"; + reg = <0x88000 0x1000>; + }; + + fman0_tx_0x28: port@a8000 { + cell-index = <0x28>; + compatible = "fsl,fman-v3-port-tx"; + reg = <0xa8000 0x1000>; + }; + + ethernet@e0000 { + cell-index = <0>; + compatible = "fsl,fman-memac"; + reg = <0xe0000 0x1000>; + fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>; + ptp-timer = <&ptp_timer0>; + pcsphy-handle = <&pcsphy0>; + status = "disabled"; + }; + + mdio@e1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + reg = <0xe1000 0x1000>; + + pcsphy0: ethernet-phy@0 { + reg = <0x0>; + }; + }; +}; diff --git a/arch/arm/dts/qoriq-fman3-0-1g-1.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-1.dtsi new file mode 100644 index 0000000000..d60f8c77ac --- /dev/null +++ b/arch/arm/dts/qoriq-fman3-0-1g-1.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 1g port #1 device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +fman@1a00000 { + fman0_rx_0x09: port@89000 { + cell-index = <0x9>; + compatible = "fsl,fman-v3-port-rx"; + reg = <0x89000 0x1000>; + }; + + fman0_tx_0x29: port@a9000 { + cell-index = <0x29>; + compatible = "fsl,fman-v3-port-tx"; + reg = <0xa9000 0x1000>; + }; + + ethernet@e2000 { + cell-index = <1>; + compatible = "fsl,fman-memac"; + reg = <0xe2000 0x1000>; + fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>; + ptp-timer = <&ptp_timer0>; + pcsphy-handle = <&pcsphy1>; + status = "disabled"; + }; + + mdio@e3000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + reg = <0xe3000 0x1000>; + + pcsphy1: ethernet-phy@0 { + reg = <0x0>; + }; + }; +}; diff --git a/arch/arm/dts/qoriq-fman3-0-1g-2.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-2.dtsi new file mode 100644 index 0000000000..7c5edc01dc --- /dev/null +++ b/arch/arm/dts/qoriq-fman3-0-1g-2.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 1g port #2 device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +fman@1a00000 { + fman0_rx_0x0a: port@8a000 { + cell-index = <0xa>; + compatible = "fsl,fman-v3-port-rx"; + reg = <0x8a000 0x1000>; + }; + + fman0_tx_0x2a: port@aa000 { + cell-index = <0x2a>; + compatible = "fsl,fman-v3-port-tx"; + reg = <0xaa000 0x1000>; + }; + + ethernet@e4000 { + cell-index = <2>; + compatible = "fsl,fman-memac"; + reg = <0xe4000 0x1000>; + fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>; + ptp-timer = <&ptp_timer0>; + pcsphy-handle = <&pcsphy2>; + status = "disabled"; + }; + + mdio@e5000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + reg = <0xe5000 0x1000>; + + pcsphy2: ethernet-phy@0 { + reg = <0x0>; + }; + }; +}; diff --git a/arch/arm/dts/qoriq-fman3-0-1g-3.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-3.dtsi new file mode 100644 index 0000000000..2d2de58c52 --- /dev/null +++ b/arch/arm/dts/qoriq-fman3-0-1g-3.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 1g port #3 device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +fman@1a00000 { + fman0_rx_0x0b: port@8b000 { + cell-index = <0xb>; + compatible = "fsl,fman-v3-port-rx"; + reg = <0x8b000 0x1000>; + }; + + fman0_tx_0x2b: port@ab000 { + cell-index = <0x2b>; + compatible = "fsl,fman-v3-port-tx"; + reg = <0xab000 0x1000>; + }; + + ethernet@e6000 { + cell-index = <3>; + compatible = "fsl,fman-memac"; + reg = <0xe6000 0x1000>; + fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>; + ptp-timer = <&ptp_timer0>; + pcsphy-handle = <&pcsphy3>; + status = "disabled"; + }; + + mdio@e7000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + reg = <0xe7000 0x1000>; + + pcsphy3: ethernet-phy@0 { + reg = <0x0>; + }; + }; +}; diff --git a/arch/arm/dts/qoriq-fman3-0-1g-4.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-4.dtsi new file mode 100644 index 0000000000..f5a73dc733 --- /dev/null +++ b/arch/arm/dts/qoriq-fman3-0-1g-4.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 1g port #4 device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +fman@1a00000 { + fman0_rx_0x0c: port@8c000 { + cell-index = <0xc>; + compatible = "fsl,fman-v3-port-rx"; + reg = <0x8c000 0x1000>; + }; + + fman0_tx_0x2c: port@ac000 { + cell-index = <0x2c>; + compatible = "fsl,fman-v3-port-tx"; + reg = <0xac000 0x1000>; + }; + + ethernet@e8000 { + cell-index = <4>; + compatible = "fsl,fman-memac"; + reg = <0xe8000 0x1000>; + fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; + ptp-timer = <&ptp_timer0>; + pcsphy-handle = <&pcsphy4>; + status = "disabled"; + }; + + mdio@e9000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + reg = <0xe9000 0x1000>; + + pcsphy4: ethernet-phy@0 { + reg = <0x0>; + }; + }; +}; diff --git a/arch/arm/dts/qoriq-fman3-0-1g-5.dtsi b/arch/arm/dts/qoriq-fman3-0-1g-5.dtsi new file mode 100644 index 0000000000..baa5751191 --- /dev/null +++ b/arch/arm/dts/qoriq-fman3-0-1g-5.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 1g port #5 device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +fman@1a00000 { + fman0_rx_0x0d: port@8d000 { + cell-index = <0xd>; + compatible = "fsl,fman-v3-port-rx"; + reg = <0x8d000 0x1000>; + }; + + fman0_tx_0x2d: port@ad000 { + cell-index = <0x2d>; + compatible = "fsl,fman-v3-port-tx"; + reg = <0xad000 0x1000>; + }; + + ethernet@ea000 { + cell-index = <5>; + compatible = "fsl,fman-memac"; + reg = <0xea000 0x1000>; + fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>; + ptp-timer = <&ptp_timer0>; + pcsphy-handle = <&pcsphy5>; + status = "disabled"; + }; + + mdio@eb000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + reg = <0xeb000 0x1000>; + + pcsphy5: ethernet-phy@0 { + reg = <0x0>; + }; + }; +}; diff --git a/arch/arm/dts/qoriq-fman3-0.dtsi b/arch/arm/dts/qoriq-fman3-0.dtsi new file mode 100644 index 0000000000..82fe796f4b --- /dev/null +++ b/arch/arm/dts/qoriq-fman3-0.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 device tree + * + * Copyright 2012-2015 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +fman0: fman@1a00000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + compatible = "fsl,fman"; + ranges = <0x0 0x0 0x1a00000 0xfe000>; + reg = <0x0 0x1a00000 0x0 0xfe000>; + clocks = <&clockgen 3 0>; + clock-names = "fmanclk"; + fsl,qman-channel-range = <0x800 0x10>; + ptimer-handle = <&ptp_timer0>; + + muram@0 { + compatible = "fsl,fman-muram"; + reg = <0x0 0x60000>; + }; + + fman0_oh_0x2: port@82000 { + cell-index = <0x2>; + compatible = "fsl,fman-v3-port-oh"; + reg = <0x82000 0x1000>; + }; + + fman0_oh_0x3: port@83000 { + cell-index = <0x3>; + compatible = "fsl,fman-v3-port-oh"; + reg = <0x83000 0x1000>; + }; + + fman0_oh_0x4: port@84000 { + cell-index = <0x4>; + compatible = "fsl,fman-v3-port-oh"; + reg = <0x84000 0x1000>; + }; + + fman0_oh_0x5: port@85000 { + cell-index = <0x5>; + compatible = "fsl,fman-v3-port-oh"; + reg = <0x85000 0x1000>; + }; + + fman0_oh_0x6: port@86000 { + cell-index = <0x6>; + compatible = "fsl,fman-v3-port-oh"; + reg = <0x86000 0x1000>; + }; + + fman0_oh_0x7: port@87000 { + cell-index = <0x7>; + compatible = "fsl,fman-v3-port-oh"; + reg = <0x87000 0x1000>; + }; + + mdio0: mdio@fc000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + reg = <0xfc000 0x1000>; + }; + + xmdio0: mdio@fd000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + reg = <0xfd000 0x1000>; + }; +}; + +ptp_timer0: ptp-timer@1afe000 { + compatible = "fsl,fman-ptp-timer"; + reg = <0x0 0x1afe000 0x0 0x1000>; + clocks = <&clockgen 3 0>; +}; diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts index 1e16d7fab9..32cb3bffcb 100644 --- a/arch/arm/dts/zynq-cse-nand.dts +++ b/arch/arm/dts/zynq-cse-nand.dts @@ -38,6 +38,21 @@ #size-cells = <1>; ranges; + smcc: memory-controller@e000e000 { + #address-cells = <1>; + #size-cells = <1>; + clock-names = "memclk", "apb_pclk"; + clocks = <&clkc 11>, <&clkc 44>; + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; + ranges; + reg = <0xe000e000 0x1000>; + + nand0: flash@e1000000 { + compatible = "arm,pl353-nand-r2p1"; + reg = <0xe1000000 0x1000000>; + }; + }; + slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 39b5d7fff9..bf982e2218 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -162,9 +162,9 @@ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ - "", "", /* 78 - 79 */ - "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 -89 */ + "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ + "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ @@ -198,9 +198,6 @@ #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ - /* u160 IRPS5401 0x17/0x47 */ - /* u167 IRPS5401 0x1c/0x4c */ - /* u175 IRPS5401 0x1d/0x4d */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ @@ -209,6 +206,19 @@ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ + + irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ + compatible = "infineon,irps5401"; + reg = <0x47>; /* pmbus / i2c 0x17 */ + }; + irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ + compatible = "infineon,irps5401"; + reg = <0x4c>; /* pmbus / i2c 0x1c */ + }; + irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ + compatible = "infineon,irps5401"; + reg = <0x4d>; /* pmbus / i2c 0x1d */ + }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 3ceb39dce0..a4bd6b800a 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -147,15 +147,13 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ - #clock-cells = <0>; + irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; - reg = <0x43>; + reg = <0x43>; /* pmbus / i2c 0x13 */ }; - irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ - #clock-cells = <0>; + irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; - reg = <0x4d>; + reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 7dad4523de..d4b3769a27 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -172,15 +172,13 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ - #clock-cells = <0>; + irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; - reg = <0x43>; + reg = <0x43>; /* pmbus / i2c 0x13 */ }; - irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ - #clock-cells = <0>; + irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; - reg = <0x4d>; + reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index d16bf8ac7a..63e285fe9a 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -327,18 +327,15 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ - #clock-cells = <0>; + irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; - irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ - #clock-cells = <0>; + irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; - irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ - #clock-cells = <0>; + irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 75ecd7a5c2..118a2de96b 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -351,13 +351,11 @@ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ - irps5401_44: irps54012@44 { /* IRPS5401 - u53 */ - #clock-cells = <0>; + irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; - irps5401_45: irps54012@45 { /* IRPS5401 - u55 */ - #clock-cells = <0>; + irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index f3b5edfeb4..e454bfcba7 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -355,13 +355,11 @@ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ - irps5401_44: irps54012@44 { /* IRPS5401 - u53 */ - #clock-cells = <0>; + irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; - irps5401_45: irps54012@45 { /* IRPS5401 - u55 */ - #clock-cells = <0>; + irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index c62d414aac..020548ac6c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -158,6 +158,10 @@ void erratum_a010315(void); bool soc_has_dp_ddr(void); bool soc_has_aiop(void); + +#ifdef CONFIG_GIC_V3_ITS +int ls_gic_rd_tables_init(void *blob); +#endif #endif #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index df9f1835c9..4bccfbe6e1 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -226,6 +226,10 @@ compatible = "denx,u-boot-acpi-test"; }; + acpi-test2 { + compatible = "denx,u-boot-acpi-test"; + }; + clocks { clk_fixed: clk-fixed { compatible = "fixed-clock"; diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h index f4ce72d566..f95ddb058a 100644 --- a/arch/sandbox/include/asm/global_data.h +++ b/arch/sandbox/include/asm/global_data.h @@ -13,6 +13,7 @@ struct arch_global_data { uint8_t *ram_buf; /* emulated RAM buffer */ void *text_base; /* pointer to base of text region */ + ulong acpi_start; /* Start address of ACPI tables */ }; #include <asm-generic/global_data.h> diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index 17cf1682ad..7ef169b147 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -566,6 +566,8 @@ int arch_fsp_init_r(void) struct udevice *dev, *itss; int ret; + if (!ll_boot_init()) + return 0; /* * This must be called before any devices are probed. Put any probing * into arch_fsps_preinit() above. diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c index 37e0424b5e..0f04c4f8e9 100644 --- a/arch/x86/cpu/coreboot/tables.c +++ b/arch/x86/cpu/coreboot/tables.c @@ -115,20 +115,11 @@ __weak void cb_parse_unhandled(u32 tag, unsigned char *ptr) static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) { + unsigned char *ptr = addr; struct cb_header *header; - unsigned char *ptr = (unsigned char *)addr; int i; - for (i = 0; i < len; i += 16, ptr += 16) { - header = (struct cb_header *)ptr; - if (!strncmp((const char *)header->signature, "LBIO", 4)) - break; - } - - /* We walked the entire space and didn't find anything. */ - if (i >= len) - return -1; - + header = (struct cb_header *)ptr; if (!header->table_bytes) return 0; @@ -231,10 +222,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header((void *)0x00000000, 0x1000, info); + long addr; + int ret; - if (ret != 1) - ret = cb_parse_header((void *)0x000f0000, 0x1000, info); + addr = locate_coreboot_table(); + if (addr < 0) + return addr; + ret = cb_parse_header((void *)addr, 0x1000, info); - return (ret == 1) ? 0 : -1; + return ret == 1 ? 0 : -ENOENT; } diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index cec04b481b..8526e856d7 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -239,8 +239,10 @@ int cpu_init_r(void) struct udevice *dev; int ret; - if (!ll_boot_init()) + if (!ll_boot_init()) { + uclass_first_device(UCLASS_PCI, &dev); return 0; + } ret = x86_init_cpus(); if (ret) diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index c8da7f10e9..0312a26bbb 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -447,10 +447,37 @@ int x86_cpu_init_f(void) return 0; } +long detect_coreboot_table_at(ulong start, ulong size) +{ + u32 *ptr, *end; + + size /= 4; + for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) { + if (*ptr == 0x4f49424c) /* "LBIO" */ + return (long)ptr; + } + + return -ENOENT; +} + +long locate_coreboot_table(void) +{ + long addr; + + /* We look for LBIO in the first 4K of RAM and again at 960KB */ + addr = detect_coreboot_table_at(0x0, 0x1000); + if (addr < 0) + addr = detect_coreboot_table_at(0xf0000, 0x1000); + + return addr; +} + int x86_cpu_reinit_f(void) { setup_identity(); setup_pci_ram_top(); + if (locate_coreboot_table() >= 0) + gd->flags |= GD_FLG_SKIP_LL_INIT; return 0; } diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index 4c7e9ea215..e67a116ac1 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -264,6 +264,9 @@ int interrupt_init(void) struct udevice *dev; int ret; + if (!ll_boot_init()) + return 0; + /* Try to set up the interrupt router, but don't require one */ ret = irq_first_device_type(X86_IRQT_BASE, &dev); if (ret && ret != -ENODEV) @@ -295,8 +298,7 @@ int interrupt_init(void) * TODO(sjg@chromium.org): But we don't handle these correctly when * booted from EFI. */ - if (ll_boot_init()) - enable_interrupts(); + enable_interrupts(); #endif return 0; diff --git a/arch/x86/cpu/start_from_spl.S b/arch/x86/cpu/start_from_spl.S index 22cab2dd6c..905c825cdc 100644 --- a/arch/x86/cpu/start_from_spl.S +++ b/arch/x86/cpu/start_from_spl.S @@ -14,18 +14,30 @@ .globl _start .type _start, @function _start: - /* Set up memory using the existing stack */ + /* + * If running from coreboot, CAR is no-longer available. Use the + * existing stack, which is large enough. + */ + call locate_coreboot_table + cmp $0, %eax + jge use_existing_stack + movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %eax #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %eax #endif + jmp 2f /* - * We don't subject CONFIG_DCACHE_RAM_MRC_VAR_SIZE since memory is + * We don't subtract CONFIG_DCACHE_RAM_MRC_VAR_SIZE since memory is * already set up. This has the happy side-effect of putting gd in a * new place separate from SPL, so the memset() in * board_init_f_init_reserve() does not cause any problems (otherwise * it would zero out the gd and crash) */ + /* Set up memory using the existing stack */ +use_existing_stack: + mov %esp, %eax +2: call board_init_f_alloc_reserve mov %eax, %esp diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 61de0077d7..268284f43c 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -343,4 +343,11 @@ void *high_table_malloc(size_t bytes); */ void write_coreboot_table(u32 addr, struct memory_area *cfg_tables); +/** + * locate_coreboot_table() - Try to find coreboot tables at standard locations + * + * @return address of table that was found, or -ve error number + */ +long locate_coreboot_table(void); + #endif diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index f4c1839104..4aee2f3e8c 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -123,6 +123,7 @@ struct arch_global_data { #ifdef CONFIG_FSP_VERSION2 struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */ #endif + ulong acpi_start; /* Start address of ACPI tables */ }; #endif diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 9346e165d8..13f1409de8 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -10,6 +10,7 @@ #include <cpu.h> #include <dm.h> #include <dm/uclass-internal.h> +#include <mapmem.h> #include <serial.h> #include <version.h> #include <acpi/acpi_table.h> @@ -19,6 +20,7 @@ #include <asm/mpspec.h> #include <asm/tables.h> #include <asm/arch/global_nvs.h> +#include <dm/acpi.h> /* * IASL compiles the dsdt entries and writes the hex values @@ -29,139 +31,6 @@ extern const unsigned char AmlCode[]; /* ACPI RSDP address to be used in boot parameters */ static ulong acpi_rsdp_addr; -static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, - struct acpi_xsdt *xsdt) -{ - memset(rsdp, 0, sizeof(struct acpi_rsdp)); - - memcpy(rsdp->signature, RSDP_SIG, 8); - memcpy(rsdp->oem_id, OEM_ID, 6); - - rsdp->length = sizeof(struct acpi_rsdp); - rsdp->rsdt_address = (u32)rsdt; - - /* - * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2 - * - * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2. - * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR - * revision 0) - */ - if (xsdt == NULL) { - rsdp->revision = ACPI_RSDP_REV_ACPI_1_0; - } else { - rsdp->xsdt_address = (u64)(u32)xsdt; - rsdp->revision = ACPI_RSDP_REV_ACPI_2_0; - } - - /* Calculate checksums */ - rsdp->checksum = table_compute_checksum((void *)rsdp, 20); - rsdp->ext_checksum = table_compute_checksum((void *)rsdp, - sizeof(struct acpi_rsdp)); -} - -void acpi_fill_header(struct acpi_table_header *header, char *signature) -{ - memcpy(header->signature, signature, 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, OEM_TABLE_ID, 8); - header->oem_revision = U_BOOT_BUILD_DATE; - memcpy(header->aslc_id, ASLC_ID, 4); -} - -static void acpi_write_rsdt(struct acpi_rsdt *rsdt) -{ - struct acpi_table_header *header = &(rsdt->header); - - /* Fill out header fields */ - acpi_fill_header(header, "RSDT"); - header->length = sizeof(struct acpi_rsdt); - header->revision = 1; - - /* Entries are filled in later, we come with an empty set */ - - /* Fix checksum */ - header->checksum = table_compute_checksum((void *)rsdt, - sizeof(struct acpi_rsdt)); -} - -static void acpi_write_xsdt(struct acpi_xsdt *xsdt) -{ - struct acpi_table_header *header = &(xsdt->header); - - /* Fill out header fields */ - acpi_fill_header(header, "XSDT"); - header->length = sizeof(struct acpi_xsdt); - header->revision = 1; - - /* Entries are filled in later, we come with an empty set */ - - /* Fix checksum */ - header->checksum = table_compute_checksum((void *)xsdt, - sizeof(struct acpi_xsdt)); -} - -/** - * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length - * and checksum. - */ -static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) -{ - int i, entries_num; - struct acpi_rsdt *rsdt; - struct acpi_xsdt *xsdt; - - /* The RSDT is mandatory while the XSDT is not */ - rsdt = (struct acpi_rsdt *)rsdp->rsdt_address; - - /* This should always be MAX_ACPI_TABLES */ - entries_num = ARRAY_SIZE(rsdt->entry); - - for (i = 0; i < entries_num; i++) { - if (rsdt->entry[i] == 0) - break; - } - - if (i >= entries_num) { - debug("ACPI: Error: too many tables\n"); - return; - } - - /* Add table to the RSDT */ - rsdt->entry[i] = (u32)table; - - /* Fix RSDT length or the kernel will assume invalid entries */ - rsdt->header.length = sizeof(struct acpi_table_header) + - sizeof(u32) * (i + 1); - - /* Re-calculate checksum */ - rsdt->header.checksum = 0; - rsdt->header.checksum = table_compute_checksum((u8 *)rsdt, - rsdt->header.length); - - /* The RSDT is mandatory while the XSDT is not */ - if (!rsdp->xsdt_address) - return; - - /* - * And now the same thing for the XSDT. We use the same index as for - * now we want the XSDT and RSDT to always be in sync in U-Boot - */ - xsdt = (struct acpi_xsdt *)((u32)rsdp->xsdt_address); - - /* Add table to the XSDT */ - xsdt->entry[i] = (u64)(u32)table; - - /* Fix XSDT length */ - xsdt->header.length = sizeof(struct acpi_table_header) + - sizeof(u64) * (i + 1); - - /* Re-calculate checksum */ - xsdt->header.checksum = 0; - xsdt->header.checksum = table_compute_checksum((u8 *)xsdt, - xsdt->header.length); -} - static void acpi_create_facs(struct acpi_facs *facs) { memset((void *)facs, 0, sizeof(struct acpi_facs)); @@ -487,12 +356,9 @@ static void acpi_create_spcr(struct acpi_spcr *spcr) /* * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c */ -ulong write_acpi_tables(ulong start) +ulong write_acpi_tables(ulong start_addr) { - u32 current; - struct acpi_rsdp *rsdp; - struct acpi_rsdt *rsdt; - struct acpi_xsdt *xsdt; + struct acpi_ctx sctx, *ctx = &sctx; struct acpi_facs *facs; struct acpi_table_header *dsdt; struct acpi_fadt *fadt; @@ -500,60 +366,39 @@ ulong write_acpi_tables(ulong start) struct acpi_madt *madt; struct acpi_csrt *csrt; struct acpi_spcr *spcr; + void *start; + ulong addr; int i; - current = start; + start = map_sysmem(start_addr, 0); - /* Align ACPI tables to 16 byte */ - current = ALIGN(current, 16); + debug("ACPI: Writing ACPI tables at %lx\n", start_addr); - debug("ACPI: Writing ACPI tables at %lx\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (struct acpi_rsdp *)current; - current += sizeof(struct acpi_rsdp); - current = ALIGN(current, 16); - rsdt = (struct acpi_rsdt *)current; - current += sizeof(struct acpi_rsdt); - current = ALIGN(current, 16); - xsdt = (struct acpi_xsdt *)current; - current += sizeof(struct acpi_xsdt); - /* - * Per ACPI spec, the FACS table address must be aligned to a 64 byte - * boundary (Windows checks this, but Linux does not). - */ - current = ALIGN(current, 64); - - /* clear all table memory */ - memset((void *)start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); + acpi_setup_base_tables(ctx, start); debug("ACPI: * FACS\n"); - facs = (struct acpi_facs *)current; - current += sizeof(struct acpi_facs); - current = ALIGN(current, 16); + facs = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_facs)); acpi_create_facs(facs); debug("ACPI: * DSDT\n"); - dsdt = (struct acpi_table_header *)current; + dsdt = ctx->current; memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header)); - current += sizeof(struct acpi_table_header); - memcpy((char *)current, + acpi_inc(ctx, sizeof(struct acpi_table_header)); + memcpy(ctx->current, (char *)&AmlCode + sizeof(struct acpi_table_header), dsdt->length - sizeof(struct acpi_table_header)); - current += dsdt->length - sizeof(struct acpi_table_header); - current = ALIGN(current, 16); + acpi_inc_align(ctx, dsdt->length - sizeof(struct acpi_table_header)); /* Pack GNVS into the ACPI table area */ for (i = 0; i < dsdt->length; i++) { u32 *gnvs = (u32 *)((u32)dsdt + i); if (*gnvs == ACPI_GNVS_ADDR) { - debug("Fix up global NVS in DSDT to 0x%08x\n", current); - *gnvs = current; + ulong addr = (ulong)map_to_sysmem(ctx->current); + + debug("Fix up global NVS in DSDT to %#08lx\n", addr); + *gnvs = addr; break; } } @@ -563,51 +408,48 @@ ulong write_acpi_tables(ulong start) dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length); /* Fill in platform-specific global NVS variables */ - acpi_create_gnvs((struct acpi_global_nvs *)current); - current += sizeof(struct acpi_global_nvs); - current = ALIGN(current, 16); + acpi_create_gnvs(ctx->current); + acpi_inc_align(ctx, sizeof(struct acpi_global_nvs)); debug("ACPI: * FADT\n"); - fadt = (struct acpi_fadt *)current; - current += sizeof(struct acpi_fadt); - current = ALIGN(current, 16); + fadt = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_fadt)); acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); + acpi_add_table(ctx, fadt); debug("ACPI: * MADT\n"); - madt = (struct acpi_madt *)current; + madt = ctx->current; acpi_create_madt(madt); - current += madt->header.length; - acpi_add_table(rsdp, madt); - current = ALIGN(current, 16); + acpi_inc_align(ctx, madt->header.length); + acpi_add_table(ctx, madt); debug("ACPI: * MCFG\n"); - mcfg = (struct acpi_mcfg *)current; + mcfg = ctx->current; acpi_create_mcfg(mcfg); - current += mcfg->header.length; - acpi_add_table(rsdp, mcfg); - current = ALIGN(current, 16); + acpi_inc_align(ctx, mcfg->header.length); + acpi_add_table(ctx, mcfg); debug("ACPI: * CSRT\n"); - csrt = (struct acpi_csrt *)current; + csrt = ctx->current; acpi_create_csrt(csrt); - current += csrt->header.length; - acpi_add_table(rsdp, csrt); - current = ALIGN(current, 16); + acpi_inc_align(ctx, csrt->header.length); + acpi_add_table(ctx, csrt); debug("ACPI: * SPCR\n"); - spcr = (struct acpi_spcr *)current; + spcr = ctx->current; acpi_create_spcr(spcr); - current += spcr->header.length; - acpi_add_table(rsdp, spcr); - current = ALIGN(current, 16); + acpi_inc_align(ctx, spcr->header.length); + acpi_add_table(ctx, spcr); + + acpi_write_dev_tables(ctx); - debug("current = %x\n", current); + addr = map_to_sysmem(ctx->current); + debug("current = %lx\n", addr); - acpi_rsdp_addr = (unsigned long)rsdp; + acpi_rsdp_addr = (unsigned long)ctx->rsdp; debug("ACPI: done\n"); - return current; + return addr; } ulong acpi_get_rsdp_addr(void) diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 9ce0ddf0d3..15e82de2fe 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -44,6 +44,14 @@ int dram_init_banksize(void) phys_addr_t low_end; uint bank; + if (!ll_boot_init()) { + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = gd->ram_size; + + mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); + return 0; + } + low_end = 0; for (bank = 1, hdr = gd->arch.hob_list; bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr); diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 226c7e66b3..98b762209f 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -78,6 +78,9 @@ static int fsp_video_probe(struct udevice *dev) struct vesa_mode_info *vesa = &mode_info.vesa; int ret; + if (!ll_boot_init()) + return 0; + printf("Video: "); /* Initialize vesa_mode_info structure */ diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index c8f2c09b6a..3869c53c5f 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -12,11 +12,18 @@ #include <asm/fsp/fsp_support.h> #include <asm/fsp2/fsp_api.h> #include <asm/fsp2/fsp_internal.h> +#include <linux/sizes.h> int dram_init(void) { int ret; + if (!ll_boot_init()) { + /* Use a small and safe amount of 1GB */ + gd->ram_size = SZ_1G; + + return 0; + } if (spl_phase() == PHASE_SPL) { #ifdef CONFIG_HAVE_ACPI_RESUME bool s3wake = gd->arch.prev_sleep_state == ACPI_S3; @@ -68,6 +75,9 @@ int dram_init(void) ulong board_get_usable_ram_top(ulong total_size) { + if (!ll_boot_init()) + return gd->ram_size; + #if CONFIG_IS_ENABLED(HANDOFF) struct spl_handoff *ho = gd->spl_handoff; diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index da9bd6b45c..c7dc2ea257 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -23,7 +23,7 @@ int arch_cpu_init_dm(void) int ret; /* Make sure pads are set up early in U-Boot */ - if (spl_phase() != PHASE_BOARD_F) + if (!ll_boot_init() || spl_phase() != PHASE_BOARD_F) return 0; /* Probe all pinctrl devices to set up the pads */ diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 5bb55e256f..d906b528b3 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -30,6 +30,9 @@ int init_cache_f_r(void) return ret; } + if (!ll_boot_init()) + return 0; + /* Initialise the CPU cache(s) */ return init_cache(); } |