diff options
Diffstat (limited to 'arch')
69 files changed, 480 insertions, 151 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 50369d5983..0cb97207db 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -109,12 +109,30 @@ config CPU_BIG_ENDIAN Build kernel for Big Endian Mode of ARC CPU config SYS_ICACHE_OFF - bool "Do not use Instruction Cache" + bool "Do not enable icache" default n + help + Do not enable instruction cache in U-Boot. + +config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default SYS_ICACHE_OFF + help + Do not enable instruction cache in SPL. config SYS_DCACHE_OFF - bool "Do not use Data Cache" + bool "Do not enable dcache" default n + help + Do not enable data cache in U-Boot. + +config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default SYS_DCACHE_OFF + help + Do not enable data cache in SPL. menuconfig ARC_DBG bool "ARC debugging" diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 84959b41bd..8c744f5be7 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -16,7 +16,7 @@ ENTRY(_start) lr r5, [ARC_BCR_IC_BUILD] breq r5, 0, 1f ; I$ doesn't exist lr r5, [ARC_AUX_IC_CTRL] -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) bclr r5, r5, 0 ; 0 - Enable, 1 is Disable #else bset r5, r5, 0 ; I$ exists, but is not used @@ -37,7 +37,7 @@ ENTRY(_start) breq r5, 0, 1f ; D$ doesn't exist lr r5, [ARC_AUX_DC_CTRL] bclr r5, r5, 6 ; Invalidate (discard w/o wback) -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) bclr r5, r5, 0 ; Enable (+Inv) #else bset r5, r5, 0 ; Disable (+Inv) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3c4af1f299..00be3d1721 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -74,6 +74,32 @@ config ARM_ASM_UNIFIED config THUMB2_KERNEL bool +config SYS_ICACHE_OFF + bool "Do not enable icache" + default n + help + Do not enable instruction cache in U-Boot. + +config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default SYS_ICACHE_OFF + help + Do not enable instruction cache in SPL. + +config SYS_DCACHE_OFF + bool "Do not enable dcache" + default n + help + Do not enable data cache in U-Boot. + +config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default SYS_DCACHE_OFF + help + Do not enable data cache in SPL. + config SYS_ARM_CACHE_CP15 bool "CP15 based cache enabling support" help diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c index 41feeefec1..8aee1539a9 100644 --- a/arch/arm/cpu/arm11/cpu.c +++ b/arch/arm/cpu/arm11/cpu.c @@ -51,7 +51,7 @@ static void cache_flush(void) asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i)); } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void invalidate_dcache_all(void) { asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); @@ -87,7 +87,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop) asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); } -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ void invalidate_dcache_all(void) { } @@ -95,15 +95,15 @@ void invalidate_dcache_all(void) void flush_dcache_all(void) { } -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ -#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) void enable_caches(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) dcache_enable(); #endif } diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 22a55f52e0..16eea693d1 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -6,7 +6,7 @@ #include <linux/types.h> #include <common.h> -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void invalidate_dcache_all(void) { asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); @@ -46,7 +46,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop) asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0)); } -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ void invalidate_dcache_all(void) { } @@ -54,7 +54,7 @@ void invalidate_dcache_all(void) void flush_dcache_all(void) { } -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ /* * Stub implementations for l2 cache operations @@ -66,7 +66,7 @@ __weak void l2_cache_disable(void) {} __weak void invalidate_l2_cache(void) {} #endif -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) /* Invalidate entire I-cache and branch predictor array */ void invalidate_icache_all(void) { @@ -80,10 +80,10 @@ void invalidate_icache_all(void) {} void enable_caches(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) dcache_enable(); #endif } diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index c3f1ee1fd1..d7cffe8b69 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -44,7 +44,7 @@ int cleanup_before_linux (void) /* flush I/D-cache */ static void cache_flush (void) { -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) unsigned long i = 0; asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 1045673292..ff592ba810 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -84,7 +84,7 @@ flush_dcache: /* * disable MMU and D cache - * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined + * enable I cache if SYS_ICACHE_OFF is not defined */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ @@ -95,7 +95,7 @@ flush_dcache: bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ #endif orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ #endif mcr p15, 0, r0, c1, c0, 0 diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 99484c2636..0dc4ebf694 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -12,7 +12,7 @@ #define ARMV7_DCACHE_INVAL_RANGE 1 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2 -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) /* Asm functions from cache_v7_asm.S */ void v7_flush_dcache_all(void); @@ -149,7 +149,7 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) flush_dcache_range(start, stop); v7_inval_tlb(); } -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ void invalidate_dcache_all(void) { } @@ -177,9 +177,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) void arm_init_domains(void) { } -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) /* Invalidate entire I-cache and branch predictor array */ void invalidate_icache_all(void) { diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c index 8bf06a3e48..70431ecf6b 100644 --- a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c @@ -5,7 +5,7 @@ #include <common.h> -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c index 8783893cf6..10e7488879 100644 --- a/arch/arm/cpu/armv7/kona-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c @@ -6,7 +6,7 @@ #include <common.h> #include <linux/sizes.h> -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 7c4018ed11..ecf9e86985 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) /* * Bit[1] of the descriptor indicates the descriptor type, @@ -215,7 +215,7 @@ void enable_caches(void) invalidate_dcache_all(); set_cr(get_cr() | CR_C); } -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ uint get_svr(void) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 0cb6dd39cc..dcb4195d7b 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -97,7 +97,7 @@ ENTRY(c_runtime_cpu_setup) /* * If I-cache is enabled invalidate it */ -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) mcr p15, 0, r0, c7, c5, 0 @ invalidate icache mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB @@ -155,7 +155,7 @@ ENTRY(cpu_init_cp15) bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB -#ifdef CONFIG_SYS_ICACHE_OFF +#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF) bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache #else orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 90fa695e98..f962903484 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -360,7 +360,7 @@ int get_clocks(void) return 0; } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c index 815e623c29..1106bead41 100644 --- a/arch/arm/cpu/armv7m/cache.c +++ b/arch/arm/cpu/armv7m/cache.c @@ -54,7 +54,7 @@ enum cache_action { FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */ }; -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) struct dcache_config { u32 ways; u32 sets; @@ -292,7 +292,7 @@ void invalidate_dcache_all(void) } #endif -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) void invalidate_icache_all(void) { @@ -349,10 +349,10 @@ int icache_status(void) void enable_caches(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) dcache_enable(); #endif } diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 9ca397e73c..e500e722e5 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) /* * With 4k page granule, a virtual address is split into 4 lookup parts @@ -657,7 +657,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) __asm_invalidate_tlb_all(); } -#else /* CONFIG_SYS_DCACHE_OFF */ +#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ /* * For SPL builds, we may want to not have dcache enabled. Any real U-Boot @@ -694,9 +694,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, { } -#endif /* CONFIG_SYS_DCACHE_OFF */ +#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) void icache_enable(void) { @@ -720,7 +720,7 @@ void invalidate_icache_all(void) __asm_invalidate_l3_icache(); } -#else /* CONFIG_SYS_ICACHE_OFF */ +#else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */ void icache_enable(void) { @@ -739,7 +739,7 @@ void invalidate_icache_all(void) { } -#endif /* CONFIG_SYS_ICACHE_OFF */ +#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */ /* * Enable dCache & iCache, whether cache is actually enabled diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 978d46b32f..12d709e23e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -388,7 +388,7 @@ void cpu_name(char *name) strcpy(name, "unknown"); } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) /* * To start MMU before DDR is available, we create MMU table in SRAM. * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three @@ -611,7 +611,7 @@ void enable_caches(void) icache_enable(); dcache_enable(); } -#endif /* CONFIG_SYS_DCACHE_OFF */ +#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ #ifdef CONFIG_TFABOOT enum boot_src __get_boot_src(u32 porsr1) diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c index 1fa6841eaf..b4cb67a66a 100644 --- a/arch/arm/cpu/armv8/s32v234/cpu.c +++ b/arch/arm/cpu/armv8/s32v234/cpu.c @@ -16,7 +16,7 @@ u32 cpu_mask(void) return readl(MC_ME_CS); } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #define S32V234_IRAM_BASE 0x3e800000UL #define S32V234_IRAM_SIZE 0x800000UL diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c index 8b932b10e1..5cd4a9524b 100644 --- a/arch/arm/cpu/pxa/cache.c +++ b/arch/arm/cpu/pxa/cache.c @@ -6,7 +6,7 @@ #include <linux/types.h> #include <common.h> -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void invalidate_dcache_all(void) { /* Flush/Invalidate I cache */ @@ -35,7 +35,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop) { return invalidate_dcache_range(start, stop); } -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ void invalidate_dcache_all(void) { } @@ -43,7 +43,7 @@ void invalidate_dcache_all(void) void flush_dcache_all(void) { } -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ /* * Stub implementations for l2 cache operations diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index b9fd41ece2..0b28f0a3ef 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -286,10 +286,10 @@ void reset_cpu(ulong ignored) void enable_caches(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) dcache_enable(); #endif } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 83058c4452..0ec7bc987d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -296,6 +296,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ + socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_is1.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_dbm_soc1.dtb \ diff --git a/arch/arm/dts/armada-370-xp.dtsi b/arch/arm/dts/armada-370-xp.dtsi index e4c35d4e98..50fc0be9f7 100644 --- a/arch/arm/dts/armada-370-xp.dtsi +++ b/arch/arm/dts/armada-370-xp.dtsi @@ -102,6 +102,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + u-boot,dm-pre-reloc; rtc: rtc@10300 { compatible = "marvell,orion-rtc"; diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi index 4b2eaeea2e..175af38018 100644 --- a/arch/arm/dts/bcm63158.dtsi +++ b/arch/arm/dts/bcm63158.dtsi @@ -66,6 +66,12 @@ clock-frequency = <0xbebc200>; u-boot,dm-pre-reloc; }; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; }; ubus { @@ -92,13 +98,13 @@ wdt1: watchdog@ff800480 { compatible = "brcm,bcm6345-wdt"; reg = <0x0 0xff800480 0x0 0x14>; - clocks = <&periph_osc>; + clocks = <&refclk50mhz>; }; wdt2: watchdog@ff8004c0 { compatible = "brcm,bcm6345-wdt"; reg = <0x0 0xff8004c0 0x0 0x14>; - clocks = <&periph_osc>; + clocks = <&refclk50mhz>; }; wdt-reboot { diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi index 76ba0ea167..91f7787eb9 100644 --- a/arch/arm/dts/bcm6858.dtsi +++ b/arch/arm/dts/bcm6858.dtsi @@ -66,6 +66,12 @@ clock-frequency = <200000000>; u-boot,dm-pre-reloc; }; + + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; }; ubus { @@ -92,13 +98,13 @@ wdt1: watchdog@ff802780 { compatible = "brcm,bcm6345-wdt"; reg = <0x0 0xff802780 0x0 0x14>; - clocks = <&periph_osc>; + clocks = <&refclk50mhz>; }; wdt2: watchdog@ff8027c0 { compatible = "brcm,bcm6345-wdt"; reg = <0x0 0xff8027c0 0x0 0x14>; - clocks = <&periph_osc>; + clocks = <&refclk50mhz>; }; wdt-reboot { diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi new file mode 100644 index 0000000000..ef215230c2 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 + +/ { + chosen { + u-boot,dm-pre-reloc; + }; + + clocks { + u-boot,dm-pre-reloc; + + altera_arria10_hps_eosc1 { + u-boot,dm-pre-reloc; + }; + + altera_arria10_hps_cb_intosc_ls { + u-boot,dm-pre-reloc; + }; + + altera_arria10_hps_f2h_free { + u-boot,dm-pre-reloc; + }; + }; + + clock_manager@0xffd04000 { + u-boot,dm-pre-reloc; + + mainpll { + u-boot,dm-pre-reloc; + }; + + perpll { + u-boot,dm-pre-reloc; + }; + + alteragrp { + u-boot,dm-pre-reloc; + }; + }; + + pinmux@0xffd07000 { + u-boot,dm-pre-reloc; + + shared { + u-boot,dm-pre-reloc; + }; + + dedicated { + u-boot,dm-pre-reloc; + }; + + dedicated_cfg { + u-boot,dm-pre-reloc; + }; + + fpga { + u-boot,dm-pre-reloc; + }; + }; + + noc@0xffd10000 { + u-boot,dm-pre-reloc; + + firewall { + u-boot,dm-pre-reloc; + }; + }; + + fpgabridge@0 { + u-boot,dm-pre-reloc; + }; + + fpgabridge@1 { + u-boot,dm-pre-reloc; + }; + + fpgabridge@2 { + u-boot,dm-pre-reloc; + }; + + fpgabridge@3 { + u-boot,dm-pre-reloc; + }; + + fpgabridge@4 { + u-boot,dm-pre-reloc; + }; + + fpgabridge@5 { + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi index 42e888548e..6e5578d7bd 100644 --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -14,7 +14,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ -#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi" + +#include "socfpga_arria10.dtsi" / { model = "Altera SOCFPGA Arria 10"; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index cc761967c7..d6b6c2ddc0 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -17,6 +17,8 @@ /dts-v1/; #include "socfpga_arria10_socdk.dtsi" +#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi" +#include "socfpga_arria10_handoff_u-boot.dtsi" / { chosen { diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi index 39009654d9..0446fd441e 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi @@ -11,8 +11,6 @@ *</auto-generated> */ -#include "socfpga_arria10.dtsi" - / { #address-cells = <1>; #size-cells = <1>; @@ -24,13 +22,11 @@ /* Clock sources */ clocks { - u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; /* Clock source: altera_arria10_hps_eosc1 */ altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -39,7 +35,6 @@ /* Clock source: altera_arria10_hps_cb_intosc_ls */ altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <60000000>; @@ -48,7 +43,6 @@ /* Clock source: altera_arria10_hps_f2h_free */ altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free { - u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; @@ -62,14 +56,12 @@ * Binding: device */ i_clk_mgr: clock_manager@0xffd04000 { - u-boot,dm-pre-reloc; compatible = "altr,socfpga-a10-clk-init"; reg = <0xffd04000 0x00000200>; reg-names = "soc_clock_manager_OCP_SLV"; /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */ mainpll { - u-boot,dm-pre-reloc; vco0-psrc = <0>; /* Field: vco0.psrc */ vco1-denom = <1>; /* Field: vco1.denom */ vco1-numer = <191>; /* Field: vco1.numer */ @@ -98,7 +90,6 @@ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */ perpll { - u-boot,dm-pre-reloc; vco0-psrc = <0>; /* Field: vco0.psrc */ vco1-denom = <1>; /* Field: vco1.denom */ vco1-numer = <159>; /* Field: vco1.numer */ @@ -124,7 +115,6 @@ /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */ alteragrp { - u-boot,dm-pre-reloc; nocclk = <0x0384000b>; /* Register: nocclk */ mpuclk = <0x03840001>; /* Register: mpuclk */ }; @@ -136,7 +126,6 @@ * Binding: pinmux */ i_io48_pin_mux: pinmux@0xffd07000 { - u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "pinctrl-single"; @@ -145,7 +134,6 @@ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */ shared { - u-boot,dm-pre-reloc; reg = <0xffd07000 0x00000200>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x0000000f>; @@ -202,7 +190,6 @@ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */ dedicated { - u-boot,dm-pre-reloc; reg = <0xffd07200 0x00000200>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x0000000f>; @@ -225,7 +212,6 @@ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */ dedicated_cfg { - u-boot,dm-pre-reloc; reg = <0xffd07200 0x00000200>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x003f3f3f>; @@ -252,7 +238,6 @@ /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */ fpga { - u-boot,dm-pre-reloc; reg = <0xffd07400 0x00000100>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x00000001>; @@ -283,13 +268,11 @@ * Binding: device */ i_noc: noc@0xffd10000 { - u-boot,dm-pre-reloc; compatible = "altr,socfpga-a10-noc"; reg = <0xffd10000 0x00008000>; reg-names = "mpu_m0"; firewall { - u-boot,dm-pre-reloc; /* * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit diff --git a/arch/arm/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/dts/socfpga_cyclone5_mcv.dtsi new file mode 100644 index 0000000000..bd92806ffc --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_mcv.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Aries/DENX MCV"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1 GiB */ + }; +}; + +&mmc0 { /* On-SoM eMMC */ + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi new file mode 100644 index 0000000000..eea453b8ad --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * Copyright (C) 2019 Wolfgang Grandegger <wg@aries-embedded.de> + */ + +#include "socfpga-common-u-boot.dtsi" + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts new file mode 100644 index 0000000000..ceaec29770 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + */ + +#include "socfpga_cyclone5_mcv.dtsi" + +/ { + model = "Aries/DENX MCV EVK"; + compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga"; + + aliases { + ethernet0 = &gmac0; + stmpe-i2c0 = &stmpe1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + status = "okay"; +}; + +&gpio0 { /* GPIO 0 ... 28 */ + status = "okay"; +}; + +&gpio1 { /* GPIO 29 ... 57 */ + status = "okay"; +}; + +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + stmpe1: stmpe811@41 { + compatible = "st,stmpe811"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + id = <0>; + blocks = <0x5>; + irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */ + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + ts,sample-time = <4>; + ts,mod-12b = <1>; + ts,ref-sel = <0>; + ts,adc-freq = <1>; + ts,ave-ctrl = <1>; + ts,touch-det-delay = <3>; + ts,settling = <4>; + ts,fraction-z = <7>; + ts,i-drive = <1>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index c3ee5f0c7b..a81b1061df 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -35,7 +35,7 @@ struct arch_global_data { unsigned int tbl; unsigned long lastinc; unsigned long long timer_reset_value; -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) unsigned long tlb_addr; unsigned long tlb_size; #if defined(CONFIG_ARM64) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 0688f1e6a6..b2913e8165 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -10,7 +10,7 @@ #include <linux/compiler.h> #include <asm/armv7_mpu.h> -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) DECLARE_GLOBAL_DATA_PTR; @@ -246,7 +246,7 @@ static void cache_disable(uint32_t cache_bit) } #endif -#ifdef CONFIG_SYS_ICACHE_OFF +#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF) void icache_enable (void) { return; @@ -278,7 +278,7 @@ int icache_status(void) } #endif -#ifdef CONFIG_SYS_DCACHE_OFF +#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void dcache_enable (void) { return; diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 565fbbe109..449544d11c 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -87,7 +87,7 @@ void noncached_init(void) noncached_end = end; noncached_next = start; -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF); #endif } diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index 589e16c5ad..2ae9a43b4e 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -25,7 +25,7 @@ void reset_cpu(ulong addr) #endif } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index 75e1f54c6a..a605942503 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -37,7 +37,7 @@ static void enable_ca7_smp(void) } } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 2c425357b5..53f9a8735a 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -446,7 +446,7 @@ void enable_caches(void) dcache_enable(); } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) u64 get_page_table_size(void) { u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); diff --git a/arch/arm/mach-imx/mx5/soc.c b/arch/arm/mach-imx/mx5/soc.c index 43d6c08b42..bbb335e275 100644 --- a/arch/arm/mach-imx/mx5/soc.c +++ b/arch/arm/mach-imx/mx5/soc.c @@ -62,7 +62,7 @@ u32 __weak get_board_rev(void) } #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index f43b3dcbfa..3dee300d77 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -204,7 +204,7 @@ void reset_cpu(ulong addr) void enable_caches(void) { -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); #endif diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 893bd3f763..b6cf629c4f 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -26,12 +26,6 @@ #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ -/* - * Disable the dcache. Currently the network driver (mvgbe.c) and USB - * EHCI driver (ehci-marvell.c) and possibly others rely on the data - * cache being disabled. - */ -#define CONFIG_SYS_DCACHE_OFF /* * By default kwbimage.cfg from board specific folder is used diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c index 26a215a8b1..186f6c048a 100644 --- a/arch/arm/mach-mediatek/mt8516/init.c +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -14,14 +14,10 @@ #include <asm/armv8/mmu.h> #include <asm/sections.h> #include <dm/uclass.h> -#include <linux/io.h> #include <dt-bindings/clock/mt8516-clk.h> DECLARE_GLOBAL_DATA_PTR; -#define WDOG_SWRST 0x10007014 -#define WDOG_SWRST_KEY 0x1209 - int dram_init(void) { int ret; @@ -87,10 +83,7 @@ int mtk_soc_early_init(void) void reset_cpu(ulong addr) { - while (1) { - writel(WDOG_SWRST_KEY, WDOG_SWRST); - mdelay(5); - } + psci_system_reset(); } int print_cpuinfo(void) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 0777a0c998..bb01eab80e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o endif endif -ifeq ($(CONFIG_SYS_DCACHE_OFF),) +ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),) obj-y += omap-cache.o endif diff --git a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S index 6dc92a6bfa..32de9d3d4f 100644 --- a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S +++ b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S @@ -16,7 +16,7 @@ .arch_extension sec -#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) .global flush_dcache_range #endif @@ -79,7 +79,7 @@ ENTRY(omap_smc_sec_cpu1) push {r4, r5, lr} ldr r4, =omap_smc_sec_cpu1_args stm r4, {r0,r1,r2,r3} @ Save args to memory -#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) mov r0, r4 mov r1, #CONFIG_SYS_CACHELINE_SIZE add r1, r0, r1 @ dcache is not enabled on CPU1, so @@ -109,7 +109,7 @@ ENDPROC(omap_smc_sec_cpu1) */ .section .data omap_smc_sec_cpu1_args: -#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) .balign CONFIG_SYS_CACHELINE_SIZE .rept CONFIG_SYS_CACHELINE_SIZE/4 .word 0 diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 600a31280c..b45d3ee544 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -333,7 +333,7 @@ int secure_tee_install(u32 addr) debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0); debug("tee_file_size = %d\n", tee_file_size); -#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) flush_dcache_range( rounddown((u32)loadptr, ARCH_DMA_MINALIGN), roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN)); @@ -356,7 +356,7 @@ int secure_tee_install(u32 addr) /* Reuse the tee_info buffer for SMC params */ smc_cpu1_params = (u32 *)&tee_info; smc_cpu1_params[0] = 0; -#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params + roundup(sizeof(u32), ARCH_DMA_MINALIGN)); #endif diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index b0686ed203..784a2a28d5 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -17,7 +17,7 @@ int arch_cpu_init(void) /* R-Car Gen3 D-cache is enabled in memmap-gen3.c */ #ifndef CONFIG_RCAR_GEN3 -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { dcache_enable(); diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c index 2094a4336d..e6ea0e9a6a 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/rk3036-board.c @@ -48,7 +48,7 @@ int dram_init(void) } #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c index b1c66382e3..fa71685af8 100644 --- a/arch/arm/mach-rockchip/rk3128-board.c +++ b/arch/arm/mach-rockchip/rk3128-board.c @@ -57,7 +57,7 @@ int dram_init_banksize(void) return 0; } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index e03759f789..80d8c4241e 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -75,7 +75,7 @@ err: #endif } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c index 6170c76f8b..e7a1e54874 100644 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -58,7 +58,7 @@ int dram_init_banksize(void) return 0; } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 41e9786d46..e2de5b2fdd 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -186,7 +186,7 @@ err: #endif } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c index 33596f628c..66aeb3ffcc 100644 --- a/arch/arm/mach-rockchip/rv1108/rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/rv1108.c @@ -6,7 +6,7 @@ #include <common.h> -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c index 12c9d7ce3a..0b879b545d 100644 --- a/arch/arm/mach-s5pc1xx/cache.c +++ b/arch/arm/mach-s5pc1xx/cache.c @@ -9,7 +9,7 @@ #include <common.h> -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { dcache_enable(); diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index ea316d09d7..48f02f08d4 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -64,6 +64,10 @@ choice prompt "Altera SOCFPGA board select" optional +config TARGET_SOCFPGA_ARIES_MCVEVK + bool "Aries MCVEVK (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_ARRIA10_SOCDK bool "Altera SOCFPGA SoCDK (Arria 10)" select TARGET_SOCFPGA_ARRIA10 @@ -128,6 +132,7 @@ config SYS_BOARD default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "is1" if TARGET_SOCFPGA_IS1 + default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 @@ -139,6 +144,7 @@ config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK + default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA @@ -159,6 +165,7 @@ config SYS_CONFIG_NAME default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "socfpga_is1" if TARGET_SOCFPGA_IS1 + default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h index 5e490d182e..f4dcb14623 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h @@ -8,7 +8,6 @@ #include <dt-bindings/reset/altr,rst-mgr.h> -void reset_deassert_peripherals_handoff(void); void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h); void socfpga_bridges_reset(int enable); diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h index b93bbaf537..452147b017 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h @@ -8,7 +8,6 @@ #define _RESET_MANAGER_S10_ void reset_cpu(ulong addr); -void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); void socfpga_bridges_reset(int enable); diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index d887f0201f..db1983dc31 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -48,10 +48,10 @@ int dram_init(void) void enable_caches(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) dcache_enable(); #endif } diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index 89a384b59c..9a32f5abfe 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -61,14 +61,6 @@ void socfpga_per_reset_all(void) writel(0xffffffff, &reset_manager_base->per2_mod_reset); } -/* - * Release peripherals from reset based on handoff - */ -void reset_deassert_peripherals_handoff(void) -{ - writel(0, &reset_manager_base->per_mod_reset); -} - #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08 #define L3REGS_REMAP_OCRAM_MASK 0x01 diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 39753a13c4..499a84aff5 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -95,17 +95,6 @@ void socfpga_bridges_reset(int enable) } /* - * Release peripherals from reset based on handoff - */ -void reset_deassert_peripherals_handoff(void) -{ - writel(0, &reset_manager_base->per1modrst); - /* Enable OCP first */ - writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst); - writel(0, &reset_manager_base->per0modrst); -} - -/* * Return non-zero if the CPU has been warm reset */ int cpu_has_been_warmreset(void) diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index bd2a9fe5ae..1a60cdc897 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -175,8 +175,7 @@ void board_init_f(ulong dummy) sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0); - /* De-assert reset for peripherals and bridges based on handoff */ - reset_deassert_peripherals_handoff(); + /* Set bridges handoff value */ socfpga_bridges_set_handoff_regs(true, true, true); debug("Unfreezing/Thaw all I/O banks\n"); diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index c6dd7b8e54..7f5b633e01 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -300,7 +300,7 @@ void reset_cpu(ulong addr) #endif } -#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index f8fc042a1d..4e159075d3 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -226,7 +226,7 @@ U_BOOT_DEVICE(ns16550_com1) = { }; #endif -#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index a3422cd5cf..e5f557716b 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -83,7 +83,7 @@ void reset_cpu(ulong addr) ; } -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig index d72ff46113..b6f16bf124 100644 --- a/arch/nds32/Kconfig +++ b/arch/nds32/Kconfig @@ -16,6 +16,32 @@ config TARGET_ADP_AE3XX endchoice +config SYS_ICACHE_OFF + bool "Do not enable icache" + default n + help + Do not enable instruction cache in U-Boot. + +config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default SYS_ICACHE_OFF + help + Do not enable instruction cache in SPL. + +config SYS_DCACHE_OFF + bool "Do not enable dcache" + default n + help + Do not enable data cache in U-Boot. + +config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default SYS_DCACHE_OFF + help + Do not enable data cache in SPL. + source "board/AndesTech/adp-ag101p/Kconfig" source "board/AndesTech/adp-ae3xx/Kconfig" diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index cf966e2132..691888157f 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -129,7 +129,7 @@ set_ivb: mfsr $r1, $mr8 and $r1, $r1, $r0 mtsr $r1, $mr8 -#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) /* * MMU_CTL NTC0 Cacheable/Write-Back */ @@ -139,7 +139,7 @@ set_ivb: mtsr $r1, $mr0 #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_ARCH_MAP_SYSMEM /* * MMU_CTL NTC1 Non-cacheable @@ -158,14 +158,14 @@ set_ivb: #endif #endif -#if !defined(CONFIG_SYS_ICACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) li $r0, 0x1 mfsr $r1, $mr8 or $r1, $r1, $r0 mtsr $r1, $mr8 #endif -#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) li $r0, 0x2 mfsr $r1, $mr8 or $r1, $r1, $r0 diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c index 9ab30d1965..27065136dd 100644 --- a/arch/nds32/lib/cache.c +++ b/arch/nds32/lib/cache.c @@ -6,7 +6,7 @@ */ #include <common.h> -#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) static inline unsigned long CACHE_SET(unsigned char cache) { if (cache == ICACHE) @@ -38,7 +38,7 @@ static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) } #endif -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) void invalidate_icache_all(void) { unsigned long end, line_size; @@ -133,7 +133,7 @@ int icache_status(void) #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void dcache_wbinval_all(void) { unsigned long end, line_size; diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 362f3cdc65..0d04d91ad4 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -19,6 +19,32 @@ config TARGET_SIFIVE_FU540 endchoice +config SYS_ICACHE_OFF + bool "Do not enable icache" + default n + help + Do not enable instruction cache in U-Boot. + +config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default SYS_ICACHE_OFF + help + Do not enable instruction cache in SPL. + +config SYS_DCACHE_OFF + bool "Do not enable dcache" + default n + help + Do not enable data cache in U-Boot. + +config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default SYS_DCACHE_OFF + help + Do not enable data cache in SPL. + # board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 228fc55f56..cd95058d9d 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -30,7 +30,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) void icache_enable(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "csrr t1, mcache_ctl\n\t" @@ -43,7 +43,7 @@ void icache_enable(void) void icache_disable(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "fence.i\n\t" @@ -57,7 +57,7 @@ void icache_disable(void) void dcache_enable(void) { -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "csrr t1, mcache_ctl\n\t" @@ -70,7 +70,7 @@ void dcache_enable(void) void dcache_disable(void) { -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "fence\n\t" diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c index bc18b710c9..37e0424b5e 100644 --- a/arch/x86/cpu/coreboot/tables.c +++ b/arch/x86/cpu/coreboot/tables.c @@ -109,6 +109,10 @@ static void cb_parse_string(unsigned char *ptr, char **info) *info = (char *)((struct cb_string *)ptr)->string; } +__weak void cb_parse_unhandled(u32 tag, unsigned char *ptr) +{ +} + static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) { struct cb_header *header; @@ -211,6 +215,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_VBNV: cb_parse_vbnv(ptr, info); break; + default: + cb_parse_unhandled(rec->tag, ptr); + break; } ptr += rec->size; diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 2ba7132c20..6de31e8c1e 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -16,6 +16,32 @@ config TARGET_XTFPGA endchoice +config SYS_ICACHE_OFF + bool "Do not enable icache" + default n + help + Do not enable instruction cache in U-Boot. + +config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default SYS_ICACHE_OFF + help + Do not enable instruction cache in SPL. + +config SYS_DCACHE_OFF + bool "Do not enable dcache" + default n + help + Do not enable data cache in U-Boot. + +config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default SYS_DCACHE_OFF + help + Do not enable data cache in SPL. + source "board/cadence/xtfpga/Kconfig" endmenu diff --git a/arch/xtensa/cpu/start.S b/arch/xtensa/cpu/start.S index 66acb4c610..38d2fa2fe1 100644 --- a/arch/xtensa/cpu/start.S +++ b/arch/xtensa/cpu/start.S @@ -164,19 +164,19 @@ _start: * enable data/instruction cache for relocated image. */ #if XCHAL_HAVE_SPANNING_WAY && \ - (!defined(CONFIG_SYS_DCACHE_OFF) || \ - !defined(CONFIG_SYS_ICACHE_OFF)) + !(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \ + CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) srli a7, a4, 29 slli a7, a7, 29 addi a7, a7, XCHAL_SPANNING_WAY -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) rdtlb1 a8, a7 srli a8, a8, 4 slli a8, a8, 4 addi a8, a8, CA_WRITEBACK wdtlb a8, a7 #endif -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) ritlb1 a8, a7 srli a8, a8, 4 slli a8, a8, 4 |