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-rw-r--r--arch/arm/include/asm/arch-mediatek/reset.h2
-rw-r--r--arch/arm/mach-imx/cpu.c1
-rw-r--r--arch/arm/mach-k3/sysfw-loader.c1
-rw-r--r--arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c1
-rw-r--r--arch/mips/Kconfig6
-rw-r--r--arch/mips/dts/mrvl,cn73xx.dtsi66
-rw-r--r--arch/mips/dts/mrvl,octeon-ebb7304.dts21
-rw-r--r--arch/mips/mach-mscc/include/mach/jr2/jr2.h3
-rw-r--r--arch/mips/mach-mscc/include/mach/luton/luton.h3
-rw-r--r--arch/mips/mach-mscc/include/mach/ocelot/ocelot.h3
-rw-r--r--arch/mips/mach-mscc/include/mach/serval/serval.h3
-rw-r--r--arch/mips/mach-mscc/include/mach/servalt/servalt.h3
-rw-r--r--arch/riscv/dts/fu540-c000-u-boot.dtsi12
-rw-r--r--arch/riscv/include/asm/arch-fu540/reset.h13
-rw-r--r--arch/x86/cpu/ivybridge/sdram.c1
15 files changed, 120 insertions, 19 deletions
diff --git a/arch/arm/include/asm/arch-mediatek/reset.h b/arch/arm/include/asm/arch-mediatek/reset.h
index 9704666d24..4ba0bad94e 100644
--- a/arch/arm/include/asm/arch-mediatek/reset.h
+++ b/arch/arm/include/asm/arch-mediatek/reset.h
@@ -6,7 +6,7 @@
#ifndef __MEDIATEK_RESET_H
#define __MEDIATEK_RESET_H
-#include <dm.h>
+struct udevice;
int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 694c26d35f..fe8d5947cc 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -8,6 +8,7 @@
#include <bootm.h>
#include <common.h>
+#include <dm.h>
#include <init.h>
#include <log.h>
#include <net.h>
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 513be09c68..96be069ee8 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <image.h>
#include <log.h>
#include <spl.h>
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
index 70940f01f3..8aad4be467 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <console.h>
+#include <dm.h>
#include <dfu.h>
#include <malloc.h>
#include <serial.h>
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 997e145450..e0f6b6c4b3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -112,9 +112,11 @@ config ARCH_OCTEON
select DISPLAY_CPUINFO
select DMA_ADDR_T_64BIT
select DM
- select DM_SERIAL
- select DM_GPIO
select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_SERIAL
+ select DM_SPI
select MIPS_L2_CACHE
select MIPS_MACH_EARLY_INIT
select MIPS_TUNE_OCTEON3
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index a7bd55f8ad..f5ad4a6213 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/clock/octeon-clock.h>
+
/ {
#address-cells = <2>;
#size-cells = <2>;
@@ -38,6 +40,38 @@
#size-cells = <1>;
};
+ clk: clock {
+ compatible = "mrvl,octeon-clk";
+ #clock-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
+ gpio: gpio-controller@1070000000800 {
+ #gpio-cells = <2>;
+ compatible = "cavium,octeon-7890-gpio";
+ reg = <0x10700 0x00000800 0x0 0x100>;
+ gpio-controller;
+ nr-gpios = <32>;
+ /* Interrupts are specified by two parts:
+ * 1) GPIO pin number (0..15)
+ * 2) Triggering (1 - edge rising
+ * 2 - edge falling
+ * 4 - level active high
+ * 8 - level active low)
+ */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ /* The GPIO pins connect to 16 consecutive CUI bits */
+ interrupts = <0x03000 4>, <0x03001 4>,
+ <0x03002 4>, <0x03003 4>,
+ <0x03004 4>, <0x03005 4>,
+ <0x03006 4>, <0x03007 4>,
+ <0x03008 4>, <0x03009 4>,
+ <0x0300a 4>, <0x0300b 4>,
+ <0x0300c 4>, <0x0300d 4>,
+ <0x0300e 4>, <0x0300f 4>;
+ };
+
reset: reset@1180006001600 {
compatible = "mrvl,cn7xxx-rst";
reg = <0x11800 0x06001600 0x0 0x200>;
@@ -60,5 +94,37 @@
reg-shift = <3>;
interrupts = <0x08040 4>;
};
+
+ i2c0: i2c@1180000001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cavium,octeon-7890-twsi";
+ reg = <0x11800 0x00001000 0x0 0x200>;
+ /* INT_ST, INT_TS, INT_CORE */
+ interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>;
+ clock-frequency = <100000>;
+ clocks = <&clk OCTEON_CLK_IO>;
+ };
+
+ i2c1: i2c@1180000001200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cavium,octeon-7890-twsi";
+ reg = <0x11800 0x00001200 0x0 0x200>;
+ /* INT_ST, INT_TS, INT_CORE */
+ interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>;
+ clock-frequency = <100000>;
+ clocks = <&clk OCTEON_CLK_IO>;
+ };
+
+ spi: spi@1070000001000 {
+ compatible = "cavium,octeon-3010-spi";
+ reg = <0x10700 0x00001000 0x0 0x100>;
+ interrupts = <0x05001 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <25000000>;
+ clocks = <&clk OCTEON_CLK_IO>;
+ };
};
};
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts
index 4e9c2de7d4..6b2e5e84bc 100644
--- a/arch/mips/dts/mrvl,octeon-ebb7304.dts
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -5,7 +5,7 @@
/dts-v1/;
-/include/ "mrvl,cn73xx.dtsi"
+#include "mrvl,cn73xx.dtsi"
/ {
model = "cavium,ebb7304";
@@ -13,6 +13,7 @@
aliases {
serial0 = &uart0;
+ spi0 = &spi;
};
chosen {
@@ -94,3 +95,21 @@
&uart0 {
clock-frequency = <1200000000>;
};
+
+&i2c0 {
+ u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ clock-frequency = <100000>;
+};
+
+&i2c1 {
+ u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ clock-frequency = <100000>;
+};
+
+&spi {
+ flash@0 {
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
+ spi-max-frequency = <2000000>;
+ reg = <0>;
+ };
+};
diff --git a/arch/mips/mach-mscc/include/mach/jr2/jr2.h b/arch/mips/mach-mscc/include/mach/jr2/jr2.h
index 67244f63fa..3a779e7035 100644
--- a/arch/mips/mach-mscc/include/mach/jr2/jr2.h
+++ b/arch/mips/mach-mscc/include/mach/jr2/jr2.h
@@ -8,9 +8,6 @@
#ifndef _MSCC_JR2_H_
#define _MSCC_JR2_H_
-#include <linux/bitops.h>
-#include <dm.h>
-
/*
* Target offset base(s)
*/
diff --git a/arch/mips/mach-mscc/include/mach/luton/luton.h b/arch/mips/mach-mscc/include/mach/luton/luton.h
index 19f02ede66..dda665fc15 100644
--- a/arch/mips/mach-mscc/include/mach/luton/luton.h
+++ b/arch/mips/mach-mscc/include/mach/luton/luton.h
@@ -8,9 +8,6 @@
#ifndef _MSCC_OCELOT_H_
#define _MSCC_OCELOT_H_
-#include <linux/bitops.h>
-#include <dm.h>
-
/*
* Target offset base(s)
*/
diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
index 2cb2135d37..72b07c33cd 100644
--- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
+++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
@@ -8,9 +8,6 @@
#ifndef _MSCC_OCELOT_H_
#define _MSCC_OCELOT_H_
-#include <linux/bitops.h>
-#include <dm.h>
-
/*
* Target offset base(s)
*/
diff --git a/arch/mips/mach-mscc/include/mach/serval/serval.h b/arch/mips/mach-mscc/include/mach/serval/serval.h
index 763d18fe62..a78c6e59bb 100644
--- a/arch/mips/mach-mscc/include/mach/serval/serval.h
+++ b/arch/mips/mach-mscc/include/mach/serval/serval.h
@@ -8,9 +8,6 @@
#ifndef _MSCC_SERVAL_H_
#define _MSCC_SERVAL_H_
-#include <linux/bitops.h>
-#include <dm.h>
-
/*
* Target offset base(s)
*/
diff --git a/arch/mips/mach-mscc/include/mach/servalt/servalt.h b/arch/mips/mach-mscc/include/mach/servalt/servalt.h
index 9015bc7dad..4d7d0886dd 100644
--- a/arch/mips/mach-mscc/include/mach/servalt/servalt.h
+++ b/arch/mips/mach-mscc/include/mach/servalt/servalt.h
@@ -8,9 +8,6 @@
#ifndef _MSCC_SERVALT_H_
#define _MSCC_SERVALT_H_
-#include <linux/bitops.h>
-#include <dm.h>
-
/*
* Target offset base(s)
*/
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index afdb4f4402..5302677ee4 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -3,6 +3,8 @@
* (C) Copyright 2019 SiFive, Inc
*/
+#include <dt-bindings/reset/sifive-fu540-prci.h>
+
/ {
cpus {
assigned-clocks = <&prci PRCI_CLK_COREPLL>;
@@ -59,6 +61,16 @@
reg = <0x0 0x2000000 0x0 0xc0000>;
u-boot,dm-spl;
};
+ prci: clock-controller@10000000 {
+ #reset-cells = <1>;
+ resets = <&prci PRCI_RST_DDR_CTRL_N>,
+ <&prci PRCI_RST_DDR_AXI_N>,
+ <&prci PRCI_RST_DDR_AHB_N>,
+ <&prci PRCI_RST_DDR_PHY_N>,
+ <&prci PRCI_RST_GEMGXL_N>;
+ reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
+ "ddr_phy", "gemgxl_reset";
+ };
dmc: dmc@100b0000 {
compatible = "sifive,fu540-c000-ddr";
reg = <0x0 0x100b0000 0x0 0x0800
diff --git a/arch/riscv/include/asm/arch-fu540/reset.h b/arch/riscv/include/asm/arch-fu540/reset.h
new file mode 100644
index 0000000000..e42797a395
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/reset.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 SiFive, Inc.
+ *
+ * Author: Sagar Kadam <sagar.kadam@sifive.com>
+ */
+
+#ifndef __RESET_SIFIVE_H
+#define __RESET_SIFIVE_H
+
+int sifive_reset_bind(struct udevice *dev, ulong count);
+
+#endif
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 99bc48021e..dd6b8753de 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <init.h>
generated by cgit (git 2.34.1) at 2025-01-09 16:20:32 +0000