diff options
Diffstat (limited to 'arch')
25 files changed, 159 insertions, 54 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 54a9b00d4c..ba1f7bac77 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -27,6 +27,12 @@ #define ARC_AUX_IC_PTAG 0x1E #endif #define ARC_BCR_IC_BUILD 0x77 +#define AUX_AUX_CACHE_LIMIT 0x5D +#define ARC_AUX_NON_VOLATILE_LIMIT 0x5E + +/* ICCM and DCCM auxiliary registers */ +#define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */ +#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */ /* Timer related auxiliary registers */ #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ @@ -72,6 +78,9 @@ /* gcc builtin sr needs reg param to be long immediate */ #define write_aux_reg(reg_immed, val) \ __builtin_arc_sr((unsigned int)val, reg_immed) + +/* ARCNUM [15:8] - field to identify each core in a multi-core system */ +#define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8) #endif /* __ASSEMBLY__ */ #endif /* _ASM_ARC_ARCREGS_H */ diff --git a/arch/arc/include/asm/gpio.h b/arch/arc/include/asm/gpio.h new file mode 100644 index 0000000000..306ab4c9f2 --- /dev/null +++ b/arch/arc/include/asm/gpio.h @@ -0,0 +1 @@ +#include <asm-generic/gpio.h> diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index d8741fe959..1073e1570f 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -32,15 +32,15 @@ * relocation but will be used after being zeroed. */ int l1_line_sz __section(".data"); -int dcache_exists __section(".data"); -int icache_exists __section(".data"); +bool dcache_exists __section(".data") = false; +bool icache_exists __section(".data") = false; #define CACHE_LINE_MASK (~(l1_line_sz - 1)) #ifdef CONFIG_ISA_ARCV2 int slc_line_sz __section(".data"); -int slc_exists __section(".data"); -int ioc_exists __section(".data"); +bool slc_exists __section(".data") = false; +bool ioc_exists __section(".data") = false; static unsigned int __before_slc_op(const int op) { @@ -152,7 +152,7 @@ static void read_decode_cache_bcr_arcv2(void) sbcr.word = read_aux_reg(ARC_BCR_SLC); if (sbcr.fields.ver) { slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); - slc_exists = 1; + slc_exists = true; slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; } @@ -169,7 +169,7 @@ static void read_decode_cache_bcr_arcv2(void) cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); if (cbcr.fields.c) - ioc_exists = 1; + ioc_exists = true; } #endif @@ -190,7 +190,7 @@ void read_decode_cache_bcr(void) ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); if (ibcr.fields.ver) { - icache_exists = 1; + icache_exists = true; l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; if (!ic_line_sz) panic("Instruction exists but line length is 0\n"); @@ -198,7 +198,7 @@ void read_decode_cache_bcr(void) dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); if (dbcr.fields.ver){ - dcache_exists = 1; + dcache_exists = true; l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; if (!dc_line_sz) panic("Data cache exists but line length is 0\n"); diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e50ba930a1..73909952d0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -850,6 +850,7 @@ config TARGET_LS2080AQDS select SUPPORT_SPL select ARCH_MISC_INIT imply SCSI + imply SCSI_AHCI help Support for Freescale LS2080AQDS platform The LS2080A Development System (QDS) is a high-performance @@ -865,6 +866,7 @@ config TARGET_LS2080ARDB select SUPPORT_SPL select ARCH_MISC_INIT imply SCSI + imply SCSI_AHCI help Support for Freescale LS2080ARDB platform. The LS2080A Reference design board (RDB) is a high-performance @@ -926,6 +928,7 @@ config TARGET_LS1012ARDB select ARM64 select BOARD_LATE_INIT imply SCSI + imply SCSI_AHCI help Support for Freescale LS1012ARDB platform. The LS1012A Reference design board (RDB) is a high-performance diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 20e2b1a50a..635358e328 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -20,6 +20,7 @@ config ARCH_LS1021A select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE imply SCSI + imply SCSI_AHCI imply CMD_PCI menu "LS102xA architecture" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5daf79e919..66bc32cc85 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -5,6 +5,10 @@ config ARCH_LS1012A select SYS_FSL_DDR_BE select SYS_FSL_MMDC select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A009008 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F @@ -31,6 +35,7 @@ config ARCH_LS1043A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F imply SCSI + imply SCSI_AHCI imply CMD_PCI config ARCH_LS1046A @@ -57,6 +62,7 @@ config ARCH_LS1046A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F imply SCSI + imply SCSI_AHCI config ARCH_LS1088A bool @@ -244,6 +250,7 @@ config SYS_LS_PPA_ESBC_ADDR default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A + default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A default 0x680000 if SYS_LS_PPA_FW_IN_MMC default 0x680000 if SYS_LS_PPA_FW_IN_NAND help diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ab5d76ea3b..d08262971e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -29,6 +29,7 @@ #include <fsl_ddr.h> #endif #include <asm/arch/clock.h> +#include <hwconfig.h> DECLARE_GLOBAL_DATA_PTR; @@ -494,6 +495,41 @@ static inline int check_psci(void) return 0; } +static void config_core_prefetch(void) +{ + char *buf = NULL; + char buffer[HWCONFIG_BUFFER_SIZE]; + const char *prefetch_arg = NULL; + size_t arglen; + unsigned int mask; + struct pt_regs regs; + + if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; + + prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable", + &arglen, buf); + + if (prefetch_arg) { + mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff; + if (mask & 0x1) { + printf("Core0 prefetch can't be disabled\n"); + return; + } + +#define SIP_PREFETCH_DISABLE_64 0xC200FF13 + regs.regs[0] = SIP_PREFETCH_DISABLE_64; + regs.regs[1] = mask; + smc_call(®s); + + if (regs.regs[0]) + printf("Prefetch disable config failed for mask "); + else + printf("Prefetch disable config passed for mask "); + printf("0x%x\n", mask); + } +} + int arch_early_init_r(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 @@ -521,6 +557,8 @@ int arch_early_init_r(void) fsl_rgmii_init(); #endif + config_core_prefetch(); + #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.core_prefetch b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.core_prefetch new file mode 100644 index 0000000000..85cf6abd6d --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.core_prefetch @@ -0,0 +1,20 @@ +Core instruction prefetch disable +--------------------------------- +To disable instruction prefetch of core; hwconfig needs to be updated. +for e.g. +setenv hwconfig 'fsl_ddr:bank_intlv=auto;core_prefetch:disable=0x02' + +Here 0x02 can be replaced with any valid value except Mask[0] bit. It +represents 64 bit mask. The 64-bit Mask has one bit for each core. +Mask[0] = core0 +Mask[1] = core1 +Mask[2] = core2 +etc +If the bit is set ('b1) in the mask, then prefetch is disabled for +that core when it is released from reset. + +core0 prefetch should not be disabled i.e. Mask[0] should never be set. +Setting Mask[0] may lead to undefined behavior. + +Once disabled, prefetch remains disabled until the next reset. +There is no function to re-enable prefetch. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 497a4b541d..ae57c0e31d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -66,10 +66,13 @@ static void erratum_a009008(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1); +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2); set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3); +#endif #elif defined(CONFIG_ARCH_LS2080A) set_usb_txvreftune(scfg, SCFG_USB3PRM1CR); #endif @@ -87,17 +90,21 @@ static void erratum_a009798(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1); +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2); set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3); +#endif #elif defined(CONFIG_ARCH_LS2080A) set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR); #endif #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ } -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset) { scfg_clrsetbits32(scfg + offset / 4, @@ -109,17 +116,21 @@ static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset) static void erratum_a008997(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008997 -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1); +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); #endif +#endif #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ } -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ @@ -139,16 +150,18 @@ static void erratum_a008997(void) static void erratum_a009007(void) { -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1; PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); - +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) usb_phy = (void __iomem *)SCFG_USB_PHY2; PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); usb_phy = (void __iomem *)SCFG_USB_PHY3; PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); +#endif #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) void __iomem *dcsr = (void __iomem *)DCSR_BASE; diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ff0fc47021..940461137e 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -80,8 +80,6 @@ /* SATA */ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 #define CONFIG_SYS_SCSI_MAX_LUN 1 diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h index e671c143ac..6d0023d7b8 100644 --- a/arch/arm/include/asm/arch-pxa/hardware.h +++ b/arch/arm/include/asm/arch-pxa/hardware.h @@ -79,33 +79,4 @@ #endif - -/* - * Implementation specifics - */ - -#ifdef CONFIG_ARCH_LUBBOCK -#include "lubbock.h" -#endif - -#ifdef CONFIG_ARCH_PXA_IDP -#include "idp.h" -#endif - -#ifdef CONFIG_ARCH_PXA_CERF -#include "cerf.h" -#endif - -#ifdef CONFIG_ARCH_CSB226 -#include "csb226.h" -#endif - -#ifdef CONFIG_ARCH_INNOKOM -#include "innokom.h" -#endif - -#ifdef CONFIG_ARCH_PLEB -#include "pleb.h" -#endif - #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index ccefce0b20..9cb70552fe 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -120,8 +120,9 @@ relocation_return: #endif /* !CONFIG_SPL_BUILD */ #if defined(CONFIG_SPL_BUILD) bl spl_relocate_stack_gd /* may return NULL */ - /* set up gd here, outside any C code */ - mov x18, x0 + /* set up gd here, outside any C code, if new stack is returned */ + cmp x0, #0 + csel x18, x0, x18, ne /* * Perform 'sp = (x0 != NULL) ? x0 : sp' while working * around the constraint that conditional moves can not diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index ba6007186e..efa4e7b6e2 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -97,7 +97,6 @@ */ #ifdef CONFIG_IDE #define __io -#define CONFIG_MVSATA_IDE #define CONFIG_IDE_PREINIT #define CONFIG_MVSATA_IDE_USE_PORT1 /* Needs byte-swapping for ATA data register */ diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 76633bcd49..5cd0897dff 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -27,3 +27,4 @@ endif obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-base-ld20.o diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index 3aa42f8bfd..385f54dfc3 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -5,8 +5,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/delay.h> +#include <linux/kernel.h> #include <linux/errno.h> #include <linux/io.h> #include <linux/sizes.h> @@ -18,7 +20,6 @@ #define SC_PLLCTRL_SSC_EN BIT(31) #define SC_PLLCTRL2_NRSTDS BIT(28) #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) -#define SC_PLLCTRL3_REGI_SHIFT 16 #define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16) /* PLL type: VPLL27 */ @@ -41,13 +42,17 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, if (freq != UNIPHIER_PLL_FREQ_DEFAULT) { tmp = readl(base); /* SSCPLLCTRL */ tmp &= ~SC_PLLCTRL_SSC_DK_MASK; - tmp |= (487 * freq * ssc_rate / divn / 512) & - SC_PLLCTRL_SSC_DK_MASK; + tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK, + DIV_ROUND_CLOSEST(487UL * freq * ssc_rate, + divn * 512)); writel(tmp, base); tmp = readl(base + 4); tmp &= ~SC_PLLCTRL2_SSC_JK_MASK; - tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK; + tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK, + DIV_ROUND_CLOSEST(21431887UL * freq, + divn * 512)); + writel(tmp, base + 4); udelay(50); } @@ -90,7 +95,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) tmp = readl(base + 8); /* SSCPLLCTRL3 */ tmp &= ~SC_PLLCTRL3_REGI_MASK; - tmp |= regi << SC_PLLCTRL3_REGI_SHIFT; + tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); writel(tmp, base + 8); iounmap(base); diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index a3779734c1..05d29d2fd9 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -55,6 +55,7 @@ config TARGET_MPC837XEMDS bool "Support MPC837XEMDS" select BOARD_EARLY_INIT_F imply CMD_SATA + imply FSL_SATA config TARGET_MPC837XERDB bool "Support MPC837XERDB" diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 92187d371b..5df8175f1e 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -92,6 +92,7 @@ config TARGET_MPC8536DS # Use DDR3 controller with DDR2 DIMMs on this board select SYS_FSL_DDRC_GEN3 imply CMD_SATA + imply FSL_SATA config TARGET_MPC8541CDS bool "Support MPC8541CDS" @@ -148,6 +149,7 @@ config TARGET_P1022DS select SUPPORT_SPL select SUPPORT_TPL imply CMD_SATA + imply FSL_SATA config TARGET_P1023RDB bool "Support P1023RDB" @@ -209,6 +211,7 @@ config TARGET_P1025RDB select ARCH_P1025 imply CMD_EEPROM imply CMD_SATA + imply SATA_SIL config TARGET_P2020RDB bool "Support P2020RDB-PC" @@ -217,6 +220,7 @@ config TARGET_P2020RDB select ARCH_P2020 imply CMD_EEPROM imply CMD_SATA + imply SATA_SIL config TARGET_P1_TWR bool "Support p1_twr" @@ -228,6 +232,7 @@ config TARGET_P2041RDB select BOARD_LATE_INIT if CHAIN_OF_TRUST select PHYS_64BIT imply CMD_SATA + imply FSL_SATA config TARGET_QEMU_PPCE500 bool "Support qemu-ppce500" @@ -242,6 +247,7 @@ config TARGET_T1024QDS select PHYS_64BIT imply CMD_EEPROM imply CMD_SATA + imply FSL_SATA config TARGET_T1023RDB bool "Support T1023RDB" @@ -640,6 +646,7 @@ config ARCH_P1010 imply CMD_SATA imply CMD_PCI imply CMD_REGINFO + imply FSL_SATA config ARCH_P1011 bool @@ -672,6 +679,7 @@ config ARCH_P1020 imply CMD_SATA imply CMD_PCI imply CMD_REGINFO + imply SATA_SIL config ARCH_P1021 bool @@ -690,6 +698,7 @@ config ARCH_P1021 imply CMD_NAND imply CMD_SATA imply CMD_REGINFO + imply SATA_SIL config ARCH_P1022 bool @@ -737,6 +746,7 @@ config ARCH_P1024 imply CMD_SATA imply CMD_PCI imply CMD_REGINFO + imply SATA_SIL config ARCH_P1025 bool @@ -821,6 +831,7 @@ config ARCH_P3041 imply CMD_NAND imply CMD_SATA imply CMD_REGINFO + imply FSL_SATA config ARCH_P4080 bool @@ -858,6 +869,7 @@ config ARCH_P4080 select FSL_ELBC imply CMD_SATA imply CMD_REGINFO + imply SATA_SIL config ARCH_P5020 bool @@ -881,6 +893,7 @@ config ARCH_P5020 select FSL_ELBC imply CMD_SATA imply CMD_REGINFO + imply FSL_SATA config ARCH_P5040 bool @@ -904,6 +917,7 @@ config ARCH_P5040 select FSL_ELBC imply CMD_SATA imply CMD_REGINFO + imply FSL_SATA config ARCH_QEMU_E500 bool @@ -970,6 +984,7 @@ config ARCH_T1040 imply CMD_NAND imply CMD_SATA imply CMD_REGINFO + imply FSL_SATA config ARCH_T1042 bool @@ -992,6 +1007,7 @@ config ARCH_T1042 imply CMD_NAND imply CMD_SATA imply CMD_REGINFO + imply FSL_SATA config ARCH_T2080 bool @@ -1017,6 +1033,7 @@ config ARCH_T2080 imply CMD_SATA imply CMD_NAND imply CMD_REGINFO + imply FSL_SATA config ARCH_T2081 bool @@ -1063,6 +1080,7 @@ config ARCH_T4160 imply CMD_SATA imply CMD_NAND imply CMD_REGINFO + imply FSL_SATA config ARCH_T4240 bool @@ -1090,6 +1108,7 @@ config ARCH_T4240 imply CMD_SATA imply CMD_NAND imply CMD_REGINFO + imply FSL_SATA config BOOKE bool diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index c524957b6c..9dd90a1b30 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -421,6 +421,17 @@ int os_get_filesize(const char *fname, loff_t *size) return 0; } +void os_putc(int ch) +{ + putchar(ch); +} + +void os_puts(const char *str) +{ + while (*str) + os_putc(*str++); +} + int os_write_ram_buf(const char *fname) { struct sandbox_state *state = state_get_current(); diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig index 1d876b1927..f47bedaf8d 100644 --- a/arch/x86/cpu/baytrail/Kconfig +++ b/arch/x86/cpu/baytrail/Kconfig @@ -19,6 +19,7 @@ config INTEL_BAYTRAIL imply MMC_SDHCI imply MMC_SDHCI_SDMA imply SCSI + imply SCSI_AHCI imply SPI_FLASH imply SYS_NS16550 imply USB diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig index 31ac279c56..042ad2bf51 100644 --- a/arch/x86/cpu/braswell/Kconfig +++ b/arch/x86/cpu/braswell/Kconfig @@ -19,6 +19,7 @@ config INTEL_BRASWELL imply MMC_SDHCI imply MMC_SDHCI_SDMA imply SCSI + imply SCSI_AHCI imply SPI_FLASH imply SYS_NS16550 imply USB diff --git a/arch/x86/cpu/broadwell/Kconfig b/arch/x86/cpu/broadwell/Kconfig index bc2dba2bd7..42018dc127 100644 --- a/arch/x86/cpu/broadwell/Kconfig +++ b/arch/x86/cpu/broadwell/Kconfig @@ -13,6 +13,7 @@ config INTEL_BROADWELL imply ICH_SPI imply INTEL_BROADWELL_GPIO imply SCSI + imply SCSI_AHCI imply SPI_FLASH imply USB imply USB_EHCI_HCD diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 60eb45f9d0..fa3b64f2bb 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -10,6 +10,7 @@ config SYS_COREBOOT imply MMC_PCI imply MMC_SDHCI imply MMC_SDHCI_SDMA + imply SCSI_AHCI imply SPI_FLASH imply SYS_NS16550 imply USB diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index c214ea0efe..85ea6c91f3 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -14,6 +14,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE imply ICH_SPI imply INTEL_ICH6_GPIO imply SCSI + imply SCSI_AHCI imply SPI_FLASH imply USB imply USB_EHCI_HCD diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index 81444f3d9e..0a801aabea 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -9,6 +9,7 @@ config QEMU select ARCH_EARLY_INIT_R imply AHCI_PCI imply E1000 + imply SCSI_AHCI imply SYS_NS16550 imply USB imply USB_EHCI_HCD diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig index 835de85268..460ede00bc 100644 --- a/arch/x86/cpu/queensbay/Kconfig +++ b/arch/x86/cpu/queensbay/Kconfig @@ -18,6 +18,7 @@ config INTEL_QUEENSBAY imply MMC_SDHCI_SDMA imply PCH_GBE imply SCSI + imply SCSI_AHCI imply SPI_FLASH imply SYS_NS16550 imply USB |