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-rw-r--r--arch/sandbox/dts/test.dts41
-rw-r--r--arch/sandbox/include/asm/test.h12
2 files changed, 51 insertions, 2 deletions
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 137679abea..7035646195 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -14,7 +14,9 @@
i2c0 = "/i2c@0";
mmc0 = "/mmc0";
mmc1 = "/mmc1";
- pci0 = &pci;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
remoteproc1 = &rproc_1;
remoteproc2 = &rproc_2;
rtc0 = &rtc_0;
@@ -295,13 +297,48 @@
compatible = "sandbox,mmc";
};
- pci: pci-controller {
+ pci0: pci-controller0 {
compatible = "sandbox,pci";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
0x01000000 0 0x20000000 0x20000000 0 0x2000>;
+ pci@0,0 {
+ compatible = "pci-generic";
+ reg = <0x0000 0 0 0 0>;
+ emul@0,0 {
+ compatible = "sandbox,swap-case";
+ };
+ };
+ pci@1f,0 {
+ compatible = "pci-generic";
+ reg = <0xf800 0 0 0 0>;
+ emul@1f,0 {
+ compatible = "sandbox,swap-case";
+ };
+ };
+ };
+
+ pci1: pci-controller1 {
+ compatible = "sandbox,pci";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
+ 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
+ sandbox,dev-info = <0x08 0x00 0x1234 0x5678
+ 0x0c 0x00 0x1234 0x5678>;
+ };
+
+ pci2: pci-controller2 {
+ compatible = "sandbox,pci";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
+ 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
+ sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
pci@1f,0 {
compatible = "pci-generic";
reg = <0xf800 0 0 0 0>;
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index 08863bf3a9..c8ae52b248 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -16,6 +16,18 @@
#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
+#define PCI_CAP_ID_PM_OFFSET 0x50
+#define PCI_CAP_ID_EXP_OFFSET 0x60
+#define PCI_CAP_ID_MSIX_OFFSET 0x70
+
+#define PCI_EXT_CAP_ID_ERR_OFFSET 0x100
+#define PCI_EXT_CAP_ID_VC_OFFSET 0x200
+#define PCI_EXT_CAP_ID_DSN_OFFSET 0x300
+
+/* Useful for PCI_VDEVICE() macro */
+#define PCI_VENDOR_ID_SANDBOX SANDBOX_PCI_VENDOR_ID
+#define SWAP_CASE_DRV_DATA 0x55aa
+
#define SANDBOX_CLK_RATE 32768
/* System controller driver data */