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-rw-r--r--arch/arm/Kconfig25
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/cpu/armv7/arch_timer.c22
-rw-r--r--arch/arm/dts/Makefile3
-rw-r--r--arch/arm/dts/stm32f746-disco.dts70
-rw-r--r--arch/arm/dts/stm32f746.dtsi9
-rw-r--r--arch/arm/dts/stm32mp15-ddr.dtsi155
-rw-r--r--arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi122
-rw-r--r--arch/arm/dts/stm32mp157-u-boot.dtsi134
-rw-r--r--arch/arm/dts/stm32mp157.dtsi303
-rw-r--r--arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi133
-rw-r--r--arch/arm/dts/stm32mp157c-ed1.dts167
-rw-r--r--arch/arm/mach-stm32mp/Kconfig43
-rw-r--r--arch/arm/mach-stm32mp/Makefile10
-rw-r--r--arch/arm/mach-stm32mp/config.mk14
-rw-r--r--arch/arm/mach-stm32mp/cpu.c139
-rw-r--r--arch/arm/mach-stm32mp/dram_init.c34
-rw-r--r--arch/arm/mach-stm32mp/include/mach/ddr.h12
-rw-r--r--arch/arm/mach-stm32mp/include/mach/gpio.h115
-rw-r--r--arch/arm/mach-stm32mp/include/mach/stm32.h27
-rw-r--r--arch/arm/mach-stm32mp/spl.c60
21 files changed, 1577 insertions, 21 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 95553bee9d..b8f7a982d9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1132,7 +1132,7 @@ config ARCH_UNIPHIER
(formerly, System LSI Business Division of Panasonic Corporation)
config STM32
- bool "Support STM32"
+ bool "Support STMicroelectronics STM32 MCU with cortex M"
select CPU_V7M
select DM
select DM_SERIAL
@@ -1150,6 +1150,27 @@ config ARCH_STI
Support for STMicroelectronics STiH407/10 SoC family.
This SoC is used on Linaro 96Board STiH410-B2260
+config ARCH_STM32MP
+ bool "Support STMicroelectronics STM32MP Socs with cortex A"
+ select BOARD_LATE_INIT
+ select CLK
+ select DM
+ select DM_GPIO
+ select DM_RESET
+ select DM_SERIAL
+ select OF_CONTROL
+ select OF_LIBFDT
+ select PINCTRL
+ select REGMAP
+ select SUPPORT_SPL
+ select SYSCON
+ select SYS_THUMB_BUILD
+ help
+ Support for STM32MP SoC family developed by STMicroelectronics,
+ MPUs based on ARM cortex A core
+ U-BOOT is running in DDR and SPL support is the unsecure First Stage
+ BootLoader (FSBL)
+
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
select OF_CONTROL
@@ -1262,6 +1283,8 @@ source "arch/arm/mach-sti/Kconfig"
source "arch/arm/mach-stm32/Kconfig"
+source "arch/arm/mach-stm32mp/Kconfig"
+
source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5881fdc8e2..4fa8b38397 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -72,6 +72,7 @@ machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_RMOBILE) += rmobile
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_STM32) += stm32
+machine-$(CONFIG_ARCH_STM32MP) += stm32mp
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_ZYNQ) += zynq
diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
index 30915d28aa..545c518506 100644
--- a/arch/arm/cpu/armv7/arch_timer.c
+++ b/arch/arm/cpu/armv7/arch_timer.c
@@ -17,7 +17,7 @@ int timer_init(void)
gd->arch.tbl = 0;
gd->arch.tbu = 0;
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+ gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
return 0;
}
@@ -34,27 +34,9 @@ unsigned long long get_ticks(void)
}
-ulong get_timer(ulong base)
-{
- return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
-}
-
ulong timer_get_boot_us(void)
{
- return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long endtime;
-
- endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
- 1000UL);
-
- endtime += get_ticks();
-
- while (get_ticks() < endtime)
- ;
+ return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / 1000000);
}
ulong get_tbclk(void)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83e13ec915..7dd1dffae5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -500,6 +500,9 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
+dtb-$(CONFIG_TARGET_STM32MP1) += \
+ stm32mp157c-ed1.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 9e8d2a045c..e47f762e54 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -89,6 +89,37 @@
compatible = "st,button1";
button-gpio = <&gpioi 11 0>;
};
+
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpiok 3 0>;
+ status = "okay";
+ };
+
+ panel-rgb@0 {
+ compatible = "simple-panel";
+ backlight = <&backlight>;
+ enable-gpios = <&gpioi 12 0>;
+ status = "okay";
+
+ display-timings {
+ timing@0 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <2>;
+ hback-porch = <2>;
+ hsync-len = <41>;
+ vfront-porch = <2>;
+ vback-porch = <2>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <0>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
};
&clk_hse {
@@ -183,6 +214,40 @@
slew-rate = <2>;
};
};
+
+ ltdc_pins: ltdc@0 {
+ pins {
+ pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
+ <STM32F746_PG12_FUNC_LCD_B4>,
+ <STM32F746_PI9_FUNC_LCD_VSYNC>,
+ <STM32F746_PI10_FUNC_LCD_HSYNC>,
+ <STM32F746_PI14_FUNC_LCD_CLK>,
+ <STM32F746_PI15_FUNC_LCD_R0>,
+ <STM32F746_PJ0_FUNC_LCD_R1>,
+ <STM32F746_PJ1_FUNC_LCD_R2>,
+ <STM32F746_PJ2_FUNC_LCD_R3>,
+ <STM32F746_PJ3_FUNC_LCD_R4>,
+ <STM32F746_PJ4_FUNC_LCD_R5>,
+ <STM32F746_PJ5_FUNC_LCD_R6>,
+ <STM32F746_PJ6_FUNC_LCD_R7>,
+ <STM32F746_PJ7_FUNC_LCD_G0>,
+ <STM32F746_PJ8_FUNC_LCD_G1>,
+ <STM32F746_PJ9_FUNC_LCD_G2>,
+ <STM32F746_PJ10_FUNC_LCD_G3>,
+ <STM32F746_PJ11_FUNC_LCD_G4>,
+ <STM32F746_PJ13_FUNC_LCD_B1>,
+ <STM32F746_PJ14_FUNC_LCD_B2>,
+ <STM32F746_PJ15_FUNC_LCD_B3>,
+ <STM32F746_PK0_FUNC_LCD_G5>,
+ <STM32F746_PK1_FUNC_LCD_G6>,
+ <STM32F746_PK2_FUNC_LCD_G7>,
+ <STM32F746_PK4_FUNC_LCD_B5>,
+ <STM32F746_PK5_FUNC_LCD_B6>,
+ <STM32F746_PK6_FUNC_LCD_B7>,
+ <STM32F746_PK7_FUNC_LCD_DE>;
+ slew-rate = <2>;
+ };
+ };
};
&usart1 {
@@ -250,3 +315,8 @@
bus-width = <4>;
max-frequency = <25000000>;
};
+
+&ltdc {
+ status = "okay";
+ pinctrl-0 = <&ltdc_pins>;
+};
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 8c6fa133e0..8581df9a27 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -330,6 +330,15 @@
interrupts = <50>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
+
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+ u-boot,dm-pre-reloc;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
new file mode 100644
index 0000000000..ddfa0794d9
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr.dtsi
@@ -0,0 +1,155 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+/ {
+ soc {
+ ddr: ddr@0x5A003000{
+ u-boot,dm-pre-reloc;
+
+ compatible = "st,stm32mp1-ddr";
+
+ reg = <0x5A003000 0x550
+ 0x5A004000 0x234>;
+
+ clocks = <&rcc_clk AXIDCG>,
+ <&rcc_clk DDRC1>,
+ <&rcc_clk DDRC2>,
+ <&rcc_clk DDRPHYC>,
+ <&rcc_clk DDRCAPB>,
+ <&rcc_clk DDRPHYCAPB>;
+
+ clock-names = "axidcg",
+ "ddrc1",
+ "ddrc2",
+ "ddrphyc",
+ "ddrcapb",
+ "ddrphycapb";
+
+ st,mem-name = DDR_MEM_NAME;
+ st,mem-speed = <DDR_MEM_SPEED>;
+ st,mem-size = <DDR_MEM_SIZE>;
+
+ st,ctl-reg = <
+ DDR_MSTR
+ DDR_MRCTRL0
+ DDR_MRCTRL1
+ DDR_DERATEEN
+ DDR_DERATEINT
+ DDR_PWRCTL
+ DDR_PWRTMG
+ DDR_HWLPCTL
+ DDR_RFSHCTL0
+ DDR_RFSHCTL3
+ DDR_CRCPARCTL0
+ DDR_ZQCTL0
+ DDR_DFITMG0
+ DDR_DFITMG1
+ DDR_DFILPCFG0
+ DDR_DFIUPD0
+ DDR_DFIUPD1
+ DDR_DFIUPD2
+ DDR_DFIPHYMSTR
+ DDR_ODTMAP
+ DDR_DBG0
+ DDR_DBG1
+ DDR_DBGCMD
+ DDR_POISONCFG
+ DDR_PCCFG
+ >;
+
+ st,ctl-timing = <
+ DDR_RFSHTMG
+ DDR_DRAMTMG0
+ DDR_DRAMTMG1
+ DDR_DRAMTMG2
+ DDR_DRAMTMG3
+ DDR_DRAMTMG4
+ DDR_DRAMTMG5
+ DDR_DRAMTMG6
+ DDR_DRAMTMG7
+ DDR_DRAMTMG8
+ DDR_DRAMTMG14
+ DDR_ODTCFG
+ >;
+
+ st,ctl-map = <
+ DDR_ADDRMAP1
+ DDR_ADDRMAP2
+ DDR_ADDRMAP3
+ DDR_ADDRMAP4
+ DDR_ADDRMAP5
+ DDR_ADDRMAP6
+ DDR_ADDRMAP9
+ DDR_ADDRMAP10
+ DDR_ADDRMAP11
+ >;
+
+ st,ctl-perf = <
+ DDR_SCHED
+ DDR_SCHED1
+ DDR_PERFHPR1
+ DDR_PERFLPR1
+ DDR_PERFWR1
+ DDR_PCFGR_0
+ DDR_PCFGW_0
+ DDR_PCFGQOS0_0
+ DDR_PCFGQOS1_0
+ DDR_PCFGWQOS0_0
+ DDR_PCFGWQOS1_0
+ DDR_PCFGR_1
+ DDR_PCFGW_1
+ DDR_PCFGQOS0_1
+ DDR_PCFGQOS1_1
+ DDR_PCFGWQOS0_1
+ DDR_PCFGWQOS1_1
+ >;
+
+ st,phy-reg = <
+ DDR_PGCR
+ DDR_ACIOCR
+ DDR_DXCCR
+ DDR_DSGCR
+ DDR_DCR
+ DDR_ODTCR
+ DDR_ZQ0CR1
+ DDR_DX0GCR
+ DDR_DX1GCR
+ DDR_DX2GCR
+ DDR_DX3GCR
+ >;
+
+ st,phy-timing = <
+ DDR_PTR0
+ DDR_PTR1
+ DDR_PTR2
+ DDR_DTPR0
+ DDR_DTPR1
+ DDR_DTPR2
+ DDR_MR0
+ DDR_MR1
+ DDR_MR2
+ DDR_MR3
+ >;
+
+ st,phy-cal = <
+ DDR_DX0DLLCR
+ DDR_DX0DQTR
+ DDR_DX0DQSTR
+ DDR_DX1DLLCR
+ DDR_DX1DQTR
+ DDR_DX1DQSTR
+ DDR_DX2DLLCR
+ DDR_DX2DQTR
+ DDR_DX2DQSTR
+ DDR_DX3DLLCR
+ DDR_DX3DQTR
+ DDR_DX3DQSTR
+ >;
+
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
new file mode 100644
index 0000000000..352e470fa9
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+/* STM32MP157C ED1 and ED2 BOARD configuration
+ * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
+ * Reference used NT5CC256M16DP-DI from NANYA
+ *
+ * DDR type / Platform DDR3/3L
+ * freq 533MHz
+ * width 32
+ * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
+ * DDR density 8
+ * timing mode optimized
+ * Scheduling/QoS options : type = 2
+ * address mapping : RBC
+ */
+
+#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
+#define DDR_MEM_SPEED 533
+#define DDR_MEM_SIZE 0x40000000
+
+#define DDR_MSTR 0x00040401
+#define DDR_MRCTRL0 0x00000010
+#define DDR_MRCTRL1 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00800000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x00000000
+#define DDR_RFSHCTL0 0x00210000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0081008B
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_DRAMTMG0 0x121B2414
+#define DDR_DRAMTMG1 0x000A041C
+#define DDR_DRAMTMG2 0x0608090F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x08040608
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x00001005
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_ZQCTL0 0xC2000040
+#define DDR_DFITMG0 0x02060105
+#define DDR_DFITMG1 0x00000202
+#define DDR_DFILPCFG0 0x07000000
+#define DDR_DFIUPD0 0xC0400003
+#define DDR_DFIUPD1 0x00000000
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIPHYMSTR 0x00000000
+#define DDR_ADDRMAP1 0x00080808
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x00000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x07070707
+#define DDR_ADDRMAP6 0x0F070707
+#define DDR_ADDRMAP9 0x00000000
+#define DDR_ADDRMAP10 0x00000000
+#define DDR_ADDRMAP11 0x00000000
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00001201
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x01000001
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000010
+#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGW_0 0x00000000
+#define DDR_PCFGQOS0_0 0x02100B03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100B03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGW_1 0x00000000
+#define DDR_PCFGQOS0_1 0x02100B03
+#define DDR_PCFGQOS1_1 0x00800100
+#define DDR_PCFGWQOS0_1 0x01100B03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022AA5B
+#define DDR_PTR1 0x04841104
+#define DDR_PTR2 0x042DA068
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x00000C40
+#define DDR_DSGCR 0xF200001F
+#define DDR_DCR 0x0000000B
+#define DDR_DTPR0 0x38D488D0
+#define DDR_DTPR1 0x098B00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x00000840
+#define DDR_MR1 0x00000000
+#define DDR_MR2 0x00000208
+#define DDR_MR3 0x00000000
+#define DDR_ODTCR 0x00010000
+#define DDR_ZQ0CR1 0x0000005B
+#define DDR_DX0GCR 0x0000CE81
+#define DDR_DX0DLLCR 0x40000000
+#define DDR_DX0DQTR 0xFFFFFFFF
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0x0000CE81
+#define DDR_DX1DLLCR 0x40000000
+#define DDR_DX1DQTR 0xFFFFFFFF
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0x0000CE81
+#define DDR_DX2DLLCR 0x40000000
+#define DDR_DX2DQTR 0xFFFFFFFF
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0x0000CE81
+#define DDR_DX3DLLCR 0x40000000
+#define DDR_DX3DQTR 0xFFFFFFFF
+#define DDR_DX3DQSTR 0x3DB02000
+
+#include "stm32mp15-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi
new file mode 100644
index 0000000000..d374b2bc08
--- /dev/null
+++ b/arch/arm/dts/stm32mp157-u-boot.dtsi
@@ -0,0 +1,134 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+/ {
+ aliases {
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ gpio25 = &gpioz;
+ };
+
+ config {
+ u-boot,dm-pre-reloc;
+ };
+
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&clk_hsi {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_hse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_lsi {
+ u-boot,dm-pre-reloc;
+};
+
+&clk_csi {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc_rst {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_z {
+ u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
+
+&gpioz {
+ compatible = "st,stm32-gpio";
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
new file mode 100644
index 0000000000..32d3984259
--- /dev/null
+++ b/arch/arm/dts/stm32mp157.dtsi
@@ -0,0 +1,303 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/reset-controller/stm32mp1-resets.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ aliases {
+ serial3 = &uart4;
+ };
+
+ intc: interrupt-controller@a0021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xa0021000 0x1000>,
+ <0xa0022000 0x2000>;
+ };
+
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk_lsi: clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_csi: clk-csi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ uart4: serial@40010000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc_clk UART4_K>;
+ status = "disabled";
+ };
+
+ rcc: rcc@50000000 {
+ compatible = "syscon", "simple-mfd";
+
+ reg = <0x50000000 0x1000>;
+
+ rcc_clk: rcc-clk@50000000 {
+ #clock-cells = <1>;
+ compatible = "st,stm32mp1-rcc-clk";
+ };
+
+ rcc_rst: rcc-reset@50000000 {
+ #reset-cells = <1>;
+ compatible = "st,stm32mp1-rcc-rst";
+ };
+ };
+
+ pinctrl: pin-controller {
+ compatible = "st,stm32mp157-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x50002000 0xa400>;
+ pins-are-numbered;
+
+ gpioa: gpio@50002000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc_clk GPIOA>;
+ st,bank-name = "GPIOA";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ status = "disabled";
+ };
+
+ gpiob: gpio@50003000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc_clk GPIOB>;
+ st,bank-name = "GPIOB";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ status = "disabled";
+ };
+
+ gpioc: gpio@50004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc_clk GPIOC>;
+ st,bank-name = "GPIOC";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ status = "disabled";
+ };
+
+ gpiod: gpio@50005000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x400>;
+ clocks = <&rcc_clk GPIOD>;
+ st,bank-name = "GPIOD";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ status = "disabled";
+ };
+
+ gpioe: gpio@50006000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x400>;
+ clocks = <&rcc_clk GPIOE>;
+ st,bank-name = "GPIOE";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ status = "disabled";
+ };
+
+ gpiof: gpio@50007000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x400>;
+ clocks = <&rcc_clk GPIOF>;
+ st,bank-name = "GPIOF";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ status = "disabled";
+ };
+
+ gpiog: gpio@50008000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x6000 0x400>;
+ clocks = <&rcc_clk GPIOG>;
+ st,bank-name = "GPIOG";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ status = "disabled";
+ };
+
+ gpioh: gpio@50009000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x7000 0x400>;
+ clocks = <&rcc_clk GPIOH>;
+ st,bank-name = "GPIOH";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ status = "disabled";
+ };
+
+ gpioi: gpio@5000a000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x8000 0x400>;
+ clocks = <&rcc_clk GPIOI>;
+ st,bank-name = "GPIOI";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ status = "disabled";
+ };
+
+ gpioj: gpio@5000b000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x9000 0x400>;
+ clocks = <&rcc_clk GPIOJ>;
+ st,bank-name = "GPIOJ";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ status = "disabled";
+ };
+
+ gpiok: gpio@5000c000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa000 0x400>;
+ clocks = <&rcc_clk GPIOK>;
+ st,bank-name = "GPIOK";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ status = "disabled";
+ };
+ };
+
+ pinctrl_z: pin-controller-z {
+ compatible = "st,stm32mp157-z-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x54004000 0x400>;
+ pins-are-numbered;
+
+ gpioz: gpio@54004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&rcc_clk GPIOZ>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ status = "disabled";
+ };
+ };
+
+ sdmmc1: sdmmc@58005000 {
+ compatible = "st,stm32-sdmmc2";
+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+ reg-names = "sdmmc", "delay";
+ clocks = <&rcc_clk SDMMC1_K>;
+ resets = <&rcc_rst SDMMC1_R>;
+ st,idma = <1>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@5c002000 {
+ compatible = "st,stm32f7-i2c";
+ reg = <0x5c002000 0x400>;
+ interrupt-names = "event", "error", "wakeup";
+ clocks = <&rcc_clk I2C4_K>;
+ resets = <&rcc_rst I2C4_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wakeup-source;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
new file mode 100644
index 0000000000..94d27fb398
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -0,0 +1,133 @@
+/*
+ * Copyright : STMicroelectronics 2018
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc1;
+ i2c3 = &i2c4;
+ };
+};
+
+&uart4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&i2c4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&uart4 {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c4 {
+ u-boot,dm-pre-reloc;
+};
+
+&pmic {
+ u-boot,dm-pre-reloc;
+};
+
+/* CLOCK init */
+&rcc_clk {
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+
+ st,pkcs = <
+ CLK_CKPER_DISABLED
+ CLK_SDMMC12_PLL3R
+ CLK_I2C46_PCLK5
+ CLK_I2C12_PCLK1
+ CLK_I2C35_PCLK1
+ CLK_UART1_PCLK5
+ CLK_UART24_PCLK1
+ CLK_UART35_PCLK1
+ CLK_UART6_PCLK2
+ CLK_UART78_PCLK1
+ >;
+
+ /* VCO = 1300.0 MHz => P = 650 (CPU) */
+ pll1: st,pll@0 {
+ cfg = < 2 80 0 0 0 PQR(1,0,0) >;
+ frac = < 0x800 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+ pll2: st,pll@1 {
+ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+ frac = < 0x1400 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */
+ pll3: st,pll@2 {
+ cfg = < 3 128 3 20 7 PQR(1,1,1) >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
+ pll4: st,pll@3 {
+ cfg = < 5 126 8 8 8 PQR(1,1,1) >;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+/* SPL part **************************************/
+/* MMC1 boot */
+&sdmmc1_b4_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc1_dir_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
new file mode 100644
index 0000000000..4b20fabb71
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+/ {
+ model = "STMicroelectronics STM32MP157C pmic eval daughter";
+ compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
+
+ chosen {
+ bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram";
+ stdout-path = "serial3:115200n8";
+ };
+
+ memory {
+ reg = <0xC0000000 0x40000000>;
+ };
+};
+
+&gpioa {
+ status = "okay";
+};
+
+&gpiob {
+ status = "okay";
+};
+
+&gpioc {
+ status = "okay";
+};
+
+&gpiod {
+ status = "okay";
+};
+
+&gpioe {
+ status = "okay";
+};
+
+&gpiof {
+ status = "okay";
+};
+
+&gpiog {
+ status = "okay";
+};
+
+&gpioh {
+ status = "okay";
+};
+
+&gpioi {
+ status = "okay";
+};
+
+&gpioj {
+ status = "okay";
+};
+
+&gpiok {
+ status = "okay";
+};
+
+&gpioz {
+ status = "okay";
+};
+
+&pinctrl {
+ uart4_pins_a: uart4@0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_pins_a: sdmmc1-b4@0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_dir_pins_a: sdmmc1-dir@0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
+ <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+};
+
+&pinctrl_z {
+ i2c4_pins_a: i2c4@0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ pmic: stpmu1@33 {
+ compatible = "st,stpmu1";
+ reg = <0x33>;
+ interrupts = <0 2>;
+ interrupt-parent = <&gpioa>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+ broken-cd;
+ st,dirpol;
+ st,negedge;
+ st,pin-ckin;
+ bus-width = <4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
new file mode 100644
index 0000000000..8c755f8e64
--- /dev/null
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -0,0 +1,43 @@
+if ARCH_STM32MP
+
+config SPL
+ select SPL_BOARD_INIT
+ select SPL_CLK
+ select SPL_DM
+ select SPL_DM_SEQ_ALIAS
+ select SPL_FRAMEWORK
+ select SPL_GPIO_SUPPORT
+ select SPL_LIBCOMMON_SUPPORT
+ select SPL_LIBGENERIC_SUPPORT
+ select SPL_OF_CONTROL
+ select SPL_OF_TRANSLATE
+ select SPL_PINCTRL
+ select SPL_REGMAP
+ select SPL_RESET_SUPPORT
+ select SPL_SERIAL_SUPPORT
+ select SPL_SYSCON
+ imply SPL_LIBDISK_SUPPORT
+
+config SYS_SOC
+ default "stm32mp"
+
+config TARGET_STM32MP1
+ bool "Support stm32mp1xx"
+ select CPU_V7
+ select PINCTRL_STM32
+ select STM32_RESET
+ help
+ target STMicroelectronics SOC STM32MP1 family
+ STMicroelectronics MPU with core ARMv7
+
+config SYS_TEXT_BASE
+ prompt "U-Boot base address"
+ default 0xC0100000
+ help
+ configure the U-Boot base address
+ when DDR driver is used:
+ DDR + 1MB (0xC0100000)
+
+source "board/st/stm32mp1/Kconfig"
+
+endif
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
new file mode 100644
index 0000000000..4620869b36
--- /dev/null
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+obj-y += cpu.o
+obj-y += dram_init.o
+
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/arch/arm/mach-stm32mp/config.mk b/arch/arm/mach-stm32mp/config.mk
new file mode 100644
index 0000000000..34e59c61ac
--- /dev/null
+++ b/arch/arm/mach-stm32mp/config.mk
@@ -0,0 +1,14 @@
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+#
+
+ALL-$(CONFIG_SPL_BUILD) += spl/u-boot-spl.stm32
+
+MKIMAGEFLAGS_u-boot-spl.stm32 = -T stm32image -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE)
+
+spl/u-boot-spl.stm32: MKIMAGEOUTPUT = spl/u-boot-spl.stm32.log
+
+spl/u-boot-spl.stm32: spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
new file mode 100644
index 0000000000..7c43dc1294
--- /dev/null
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+#include <common.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+/**********************************************
+ * Security init
+ *********************************************/
+#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
+#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
+
+#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
+#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
+#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
+
+#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
+
+#define PWR_CR1 (STM32_PWR_BASE + 0x00)
+#define PWR_CR1_DBP BIT(8)
+
+#define RCC_TZCR (STM32_RCC_BASE + 0x00)
+#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
+#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
+
+#define RCC_BDCR_VSWRST BIT(31)
+#define RCC_BDCR_RTCSRC GENMASK(17, 16)
+
+static void security_init(void)
+{
+ /* Disable the backup domain write protection */
+ /* the protection is enable at each reset by hardware */
+ /* And must be disable by software */
+ setbits_le32(PWR_CR1, PWR_CR1_DBP);
+
+ while (!(readl(PWR_CR1) & PWR_CR1_DBP))
+ ;
+
+ /* If RTC clock isn't enable so this is a cold boot then we need
+ * to reset the backup domain
+ */
+ if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
+ setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
+ while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
+ ;
+ clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
+ }
+
+ /* allow non secure access in Write/Read for all peripheral */
+ writel(GENMASK(25, 0), ETZPC_DECPROT0);
+
+ /* Open SYSRAM for no secure access */
+ writel(0x0, ETZPC_TZMA1_SIZE);
+
+ /* enable TZC1 TZC2 clock */
+ writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
+
+ /* Region 0 set to no access by default */
+ /* bit 0 / 16 => nsaid0 read/write Enable
+ * bit 1 / 17 => nsaid1 read/write Enable
+ * ...
+ * bit 15 / 31 => nsaid15 read/write Enable
+ */
+ writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
+ /* bit 30 / 31 => Secure Global Enable : write/read */
+ /* bit 0 / 1 => Region Enable for filter 0/1 */
+ writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
+
+ /* Enable Filter 0 and 1 */
+ setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
+
+ /* RCC trust zone deactivated */
+ writel(0x0, RCC_TZCR);
+
+ /* TAMP: deactivate the internal tamper
+ * Bit 23 ITAMP8E: monotonic counter overflow
+ * Bit 20 ITAMP5E: RTC calendar overflow
+ * Bit 19 ITAMP4E: HSE monitoring
+ * Bit 18 ITAMP3E: LSE monitoring
+ * Bit 16 ITAMP1E: RTC power domain supply monitoring
+ */
+ writel(0x0, TAMP_CR1);
+}
+
+/**********************************************
+ * Debug init
+ *********************************************/
+#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
+#define RCC_DBGCFGR_DBGCKEN BIT(8)
+
+#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
+#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
+
+static void dbgmcu_init(void)
+{
+ setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+
+ /* Freeze IWDG2 if Cortex-A7 is in debug mode */
+ setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
+}
+#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
+
+int arch_cpu_init(void)
+{
+ /* early armv7 timer init: needed for polling */
+ timer_init();
+
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ dbgmcu_init();
+
+ security_init();
+#endif
+
+ return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ printf("CPU: STM32MP15x\n");
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
new file mode 100644
index 0000000000..ecb4c988d2
--- /dev/null
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("RAM init failed: %d\n", ret);
+ return ret;
+ }
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("Cannot get RAM size: %d\n", ret);
+ return ret;
+ }
+ debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+
+ gd->ram_size = ram.size;
+
+ return 0;
+}
diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h
new file mode 100644
index 0000000000..b635001df8
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/ddr.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef __MACH_STM32MP_DDR_H_
+#define __MACH_STM32MP_DDR_H_
+
+int board_ddr_power_init(void);
+
+#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/gpio.h b/arch/arm/mach-stm32mp/include/mach/gpio.h
new file mode 100644
index 0000000000..5952557792
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/gpio.h
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+#include <asm/gpio.h>
+
+enum stm32_gpio_port {
+ STM32_GPIO_PORT_A = 0,
+ STM32_GPIO_PORT_B,
+ STM32_GPIO_PORT_C,
+ STM32_GPIO_PORT_D,
+ STM32_GPIO_PORT_E,
+ STM32_GPIO_PORT_F,
+ STM32_GPIO_PORT_G,
+ STM32_GPIO_PORT_H,
+ STM32_GPIO_PORT_I
+};
+
+enum stm32_gpio_pin {
+ STM32_GPIO_PIN_0 = 0,
+ STM32_GPIO_PIN_1,
+ STM32_GPIO_PIN_2,
+ STM32_GPIO_PIN_3,
+ STM32_GPIO_PIN_4,
+ STM32_GPIO_PIN_5,
+ STM32_GPIO_PIN_6,
+ STM32_GPIO_PIN_7,
+ STM32_GPIO_PIN_8,
+ STM32_GPIO_PIN_9,
+ STM32_GPIO_PIN_10,
+ STM32_GPIO_PIN_11,
+ STM32_GPIO_PIN_12,
+ STM32_GPIO_PIN_13,
+ STM32_GPIO_PIN_14,
+ STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_mode {
+ STM32_GPIO_MODE_IN = 0,
+ STM32_GPIO_MODE_OUT,
+ STM32_GPIO_MODE_AF,
+ STM32_GPIO_MODE_AN
+};
+
+enum stm32_gpio_otype {
+ STM32_GPIO_OTYPE_PP = 0,
+ STM32_GPIO_OTYPE_OD
+};
+
+enum stm32_gpio_speed {
+ STM32_GPIO_SPEED_2M = 0,
+ STM32_GPIO_SPEED_25M,
+ STM32_GPIO_SPEED_50M,
+ STM32_GPIO_SPEED_100M
+};
+
+enum stm32_gpio_pupd {
+ STM32_GPIO_PUPD_NO = 0,
+ STM32_GPIO_PUPD_UP,
+ STM32_GPIO_PUPD_DOWN
+};
+
+enum stm32_gpio_af {
+ STM32_GPIO_AF0 = 0,
+ STM32_GPIO_AF1,
+ STM32_GPIO_AF2,
+ STM32_GPIO_AF3,
+ STM32_GPIO_AF4,
+ STM32_GPIO_AF5,
+ STM32_GPIO_AF6,
+ STM32_GPIO_AF7,
+ STM32_GPIO_AF8,
+ STM32_GPIO_AF9,
+ STM32_GPIO_AF10,
+ STM32_GPIO_AF11,
+ STM32_GPIO_AF12,
+ STM32_GPIO_AF13,
+ STM32_GPIO_AF14,
+ STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+ enum stm32_gpio_port port;
+ enum stm32_gpio_pin pin;
+};
+
+struct stm32_gpio_ctl {
+ enum stm32_gpio_mode mode;
+ enum stm32_gpio_otype otype;
+ enum stm32_gpio_speed speed;
+ enum stm32_gpio_pupd pupd;
+ enum stm32_gpio_af af;
+};
+
+struct stm32_gpio_regs {
+ u32 moder; /* GPIO port mode */
+ u32 otyper; /* GPIO port output type */
+ u32 ospeedr; /* GPIO port output speed */
+ u32 pupdr; /* GPIO port pull-up/pull-down */
+ u32 idr; /* GPIO port input data */
+ u32 odr; /* GPIO port output data */
+ u32 bsrr; /* GPIO port bit set/reset */
+ u32 lckr; /* GPIO port configuration lock */
+ u32 afr[2]; /* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+ struct stm32_gpio_regs *regs;
+};
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
new file mode 100644
index 0000000000..ffbe0b1034
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef _MACH_STM32_H_
+#define _MACH_STM32_H_
+
+/*
+ * Peripheral memory map
+ * only address used before device tree parsing
+ */
+#define STM32_RCC_BASE 0x50000000
+#define STM32_PWR_BASE 0x50001000
+#define STM32_DBGMCU_BASE 0x50081000
+#define STM32_TZC_BASE 0x5C006000
+#define STM32_ETZPC_BASE 0x5C007000
+#define STM32_TAMP_BASE 0x5C00A000
+
+#define STM32_SYSRAM_BASE 0x2FFC0000
+#define STM32_SYSRAM_SIZE SZ_256K
+
+#define STM32_DDR_BASE 0xC0000000
+#define STM32_DDR_SIZE SZ_1G
+
+#endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
new file mode 100644
index 0000000000..8f5962a935
--- /dev/null
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+ return MMCSD_MODE_RAW;
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ arch_cpu_init();
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (ret) {
+ debug("Clock init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_RESET, 0, &dev);
+ if (ret) {
+ debug("Reset init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ return;
+ }
+
+ /* enable console uart printing */
+ preloader_console_init();
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return;
+ }
+}
generated by cgit (git 2.34.1) at 2024-12-27 10:33:38 +0000