diff options
Diffstat (limited to 'arch')
71 files changed, 2412 insertions, 161 deletions
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index a5f54330e3..b349b13f49 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -19,7 +19,9 @@ endif obj-y += cache.o obj-y += tlb.o obj-y += transition.o +ifndef CONFIG_ARMV8_PSCI obj-y += fwcall.o +endif obj-y += cpu-dt.o obj-$(CONFIG_ARM_SMCCC) += smccc-call.o diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index 9957c2974b..b0aca1b72a 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -28,7 +28,6 @@ static void hvc_call(struct pt_regs *args) "ldr x4, %4\n" "ldr x5, %5\n" "ldr x6, %6\n" - "ldr x7, %7\n" "hvc #0\n" "str x0, %0\n" "str x1, %1\n" @@ -37,7 +36,7 @@ static void hvc_call(struct pt_regs *args) : "+m" (args->regs[0]), "+m" (args->regs[1]), "+m" (args->regs[2]), "+m" (args->regs[3]) : "m" (args->regs[4]), "m" (args->regs[5]), - "m" (args->regs[6]), "m" (args->regs[7]) + "m" (args->regs[6]) : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index 358df8fee9..7ffc8dbadb 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -8,6 +8,7 @@ #include <config.h> #include <linux/linkage.h> #include <asm/psci.h> +#include <asm/secure.h> /* Default PSCI function, return -1, Not Implemented */ #define PSCI_DEFAULT(__fn) \ @@ -19,8 +20,8 @@ /* PSCI function and ID table definition*/ #define PSCI_TABLE(__id, __fn) \ - .word __id; \ - .word __fn + .quad __id; \ + .quad __fn .pushsection ._secure.text, "ax" @@ -132,33 +133,52 @@ PSCI_TABLE(0, 0) /* Caller must put PSCI function-ID table base in x9 */ handle_psci: psci_enter -1: ldr x10, [x9] /* Load PSCI function table */ - ubfx x11, x10, #32, #32 - ubfx x10, x10, #0, #32 +1: ldr x10, [x9] /* Load PSCI function table */ cbz x10, 3f /* If reach the end, bail out */ cmp x10, x0 b.eq 2f /* PSCI function found */ - add x9, x9, #8 /* If not match, try next entry */ + add x9, x9, #16 /* If not match, try next entry */ b 1b -2: blr x11 /* Call PSCI function */ +2: ldr x11, [x9, #8] /* Load PSCI function */ + blr x11 /* Call PSCI function */ psci_return 3: mov x0, #ARM_PSCI_RET_NI psci_return -unknown_smc_id: - ldr x0, =0xFFFFFFFF +/* + * Handle SiP service functions defined in SiP service function table. + * Use DECLARE_SECURE_SVC(_name, _id, _fn) to add platform specific SiP + * service function into the SiP service function table. + * SiP service function table is located in '._secure_svc_tbl_entries' section, + * which is next to '._secure.text' section. + */ +handle_svc: + adr x9, __secure_svc_tbl_start + adr x10, __secure_svc_tbl_end + subs x12, x10, x9 /* Get number of entries in table */ + b.eq 2f /* Make sure SiP function table is not empty */ + psci_enter +1: ldr x10, [x9] /* Load SiP function table */ + ldr x11, [x9, #8] + cmp w10, w0 + b.eq 2b /* SiP service function found */ + add x9, x9, #SECURE_SVC_TBL_OFFSET /* Move to next entry */ + subs x12, x12, #SECURE_SVC_TBL_OFFSET + b.eq 3b /* If reach the end, bail out */ + b 1b +2: ldr x0, =0xFFFFFFFF eret handle_smc32: /* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */ ldr w9, =0x8400001F cmp w0, w9 - b.gt unknown_smc_id + b.gt handle_svc ldr w9, =0x84000000 cmp w0, w9 - b.lt unknown_smc_id + b.lt handle_svc adr x9, _psci_32_table b handle_psci @@ -171,10 +191,10 @@ handle_smc64: /* SMC function ID 0xC4000000-0xC400001F: 64 bits PSCI */ ldr x9, =0xC400001F cmp x0, x9 - b.gt unknown_smc_id + b.gt handle_svc ldr x9, =0xC4000000 cmp x0, x9 - b.lt unknown_smc_id + b.lt handle_svc adr x9, _psci_64_table b handle_psci diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index 53de80f745..2554980595 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -58,6 +58,10 @@ SECTIONS AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) { *(._secure.text) + . = ALIGN(8); + __secure_svc_tbl_start = .; + KEEP(*(._secure_svc_tbl_entries)) + __secure_svc_tbl_end = .; } .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text)) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0aee8dfde0..1452fd2189 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -97,11 +97,15 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ meson-gxbb-odroidc2.dtb \ meson-gxbb-nanopi-k2.dtb \ + meson-gxbb-p200.dtb \ + meson-gxbb-p201.dtb \ meson-gxl-s905x-p212.dtb \ + meson-gxl-s805x-libretech-ac.dtb \ meson-gxl-s905x-libretech-cc.dtb \ meson-gxl-s905x-khadas-vim.dtb \ meson-gxm-khadas-vim2.dtb \ - meson-axg-s400.dtb + meson-axg-s400.dtb \ + meson-g12a-u200.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ @@ -657,6 +661,9 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \ at91-sama5d27_som1_ek.dtb +dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \ + at91-sama5d2_icp.dtb + dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ sama5d31ek.dtb \ sama5d33ek.dtb \ diff --git a/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi b/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi new file mode 100644 index 0000000000..347fa813e9 --- /dev/null +++ b/arch/arm/dts/at91-sama5d2_icp-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * at91-sama5d2_icp-for-uboot.dtsi - Device Tree file for SAMA5D2 ICP board + * SAMA5D2 Industrial Connectivity Platform + * + * Copyright (c) 2019, Microchip Technology Inc. and its subsidiaries + * 2019, Eugen Hristev <eugen.hristev@microchip.com> + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + }; +}; + +&sdmmc0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { /* mikrobus1 uart */ + u-boot,dm-pre-reloc; +}; + +&pinctrl_sdmmc0_default { + u-boot,dm-pre-reloc; +}; + +&pinctrl_mikrobus1_uart { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts new file mode 100644 index 0000000000..cae8748268 --- /dev/null +++ b/arch/arm/dts/at91-sama5d2_icp.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2 ICP board + * SAMA5D2 Industrial Connectivity Board + * + * Copyright (c) 2018, Microchip Technology Inc. + * 2018, Eugen Hristev <eugen.hristev@microchip.com> + */ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" + +/ { + model = "Microchip SAMA5D2 ICP"; + compatible = "atmel,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart0; + i2c1 = &i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ahb { + + sdmmc0: sdio-host@a0000000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; + }; + + apb { + uart0: serial@f801c000 { /* mikrobus1 uart */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_uart>; + status = "okay"; + }; + + macb0: ethernet@f8008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>; + phy-mode = "internal"; + status = "okay"; + }; + + i2c1: i2c@fc028000 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c32"; + reg = <0x53>; + pagesize = <16>; + }; + }; + pioA: gpio@fc038000 { + status = "okay"; + pinctrl { + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD19__TWD1>, + <PIN_PD20__TWCK1>; + bias-disable; + }; + + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PD1__GRXCK>, + <PIN_PD2__GTXER>, + <PIN_PD5__GRX2>, + <PIN_PD6__GRX3>, + <PIN_PD7__GTX2>, + <PIN_PD8__GTX3>, + <PIN_PD9__GTXCK>, + <PIN_PD10__GTXEN>, + <PIN_PD11__GRXDV>, + <PIN_PD12__GRXER>, + <PIN_PD13__GRX0>, + <PIN_PD14__GRX1>, + <PIN_PD15__GTX0>, + <PIN_PD16__GTX1>, + <PIN_PD17__GMDC>, + <PIN_PD18__GMDIO>; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PD3__GPIO>; + bias-disable; + }; + + pinctrl_macb0_rst: macb0_sw_rst { + pinmux = <PIN_PD4__GPIO>; + bias-pull-up; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA0__SDMMC0_CK>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + }; + + pinctrl_mikrobus1_uart: mikrobus1_uart { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi index 476ad1dad2..800d96eb2f 100644 --- a/arch/arm/dts/at91sam9260.dtsi +++ b/arch/arm/dts/at91sam9260.dtsi @@ -437,7 +437,7 @@ u-boot,dm-pre-reloc; }; - pinctrl@fffff400 { + pinctrl: pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; @@ -978,7 +978,7 @@ }; }; - rtc@fffffd20 { + rtc: rtc@fffffd20 { compatible = "atmel,at91sam9260-rtt"; reg = <0xfffffd20 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; @@ -986,7 +986,7 @@ status = "disabled"; }; - watchdog@fffffd40 { + watchdog: watchdog@fffffd40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi index 4f41f62738..4b2eaeea2e 100644 --- a/arch/arm/dts/bcm63158.dtsi +++ b/arch/arm/dts/bcm63158.dtsi @@ -82,6 +82,13 @@ status = "disabled"; }; + leds: led-controller@ff800800 { + compatible = "brcm,bcm6858-leds"; + reg = <0x0 0xff800800 0x0 0xe4>; + + status = "disabled"; + }; + wdt1: watchdog@ff800480 { compatible = "brcm,bcm6345-wdt"; reg = <0x0 0xff800480 0x0 0x14>; @@ -178,5 +185,18 @@ status = "disabled"; }; + + nand: nand-controller@ff801800 { + compatible = "brcm,nand-bcm63158", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x0 0xff801800 0x0 0x180>, + <0x0 0xff802000 0x0 0x10>, + <0x0 0xff801c00 0x0 0x200>; + parameter-page-big-endian = <0>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi index 5d5e64db08..76ba0ea167 100644 --- a/arch/arm/dts/bcm6858.dtsi +++ b/arch/arm/dts/bcm6858.dtsi @@ -82,6 +82,13 @@ status = "disabled"; }; + leds: led-controller@ff800800 { + compatible = "brcm,bcm6858-leds"; + reg = <0x0 0xff800800 0x0 0xe4>; + + status = "disabled"; + }; + wdt1: watchdog@ff802780 { compatible = "brcm,bcm6345-wdt"; reg = <0x0 0xff802780 0x0 0x14>; @@ -178,5 +185,18 @@ status = "disabled"; }; + + nand: nand-controller@ff801800 { + compatible = "brcm,nand-bcm6858", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x0 0xff801800 0x0 0x180>, + <0x0 0xff802000 0x0 0x10>, + <0x0 0xff801c00 0x0 0x200>; + parameter-page-big-endian = <0>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts index b5c825b052..85659440da 100644 --- a/arch/arm/dts/bcm963158.dts +++ b/arch/arm/dts/bcm963158.dts @@ -61,3 +61,67 @@ &gpio7 { status = "okay"; }; + +&nand { + status = "okay"; + write-protect = <0>; + #address-cells = <1>; + #size-cells = <0>; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + }; +}; + +&leds { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + brcm,serial-led-en-pol; + brcm,serial-led-data-ppol; + + led@16 { + reg = <16>; + label = "red:dsl2"; + }; + + led@17 { + reg = <17>; + label = "green:dsl1"; + }; + + led@18 { + reg = <18>; + label = "green:fxs2"; + }; + + led@19 { + reg = <19>; + label = "green:fxs1"; + }; + + led@26 { + reg = <26>; + label = "green:wan1_act"; + }; + + led@27 { + reg = <27>; + label = "green:wps"; + }; + + led@28 { + reg = <28>; + active-low; + label = "green:aggregate_act"; + }; + + led@29 { + reg = <29>; + label = "green:aggregate_link"; + }; +}; diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts index 15febb030f..861e9891a7 100644 --- a/arch/arm/dts/bcm968580xref.dts +++ b/arch/arm/dts/bcm968580xref.dts @@ -61,3 +61,66 @@ &gpio7 { status = "okay"; }; + +&nand { + status = "okay"; + write-protect = <0>; + #address-cells = <1>; + #size-cells = <0>; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + }; +}; + +&leds { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + brcm,serial-led-en-pol; + brcm,serial-led-data-ppol; + + led@2 { + reg = <2>; + label = "green:inet"; + }; + + led@5 { + reg = <5>; + label = "red:alarm"; + }; + + led@8 { + reg = <8>; + label = "green:wlan_link"; + }; + + led@11 { + reg = <11>; + label = "green:fxs1"; + }; + + led@14 { + reg = <14>; + label = "green:fxs2"; + }; + + led@15 { + reg = <15>; + label = "green:usb0"; + }; + + led@16 { + reg = <16>; + label = "green:usb1"; + }; + + led@17 { + reg = <17>; + label = "green:wps"; + }; +}; diff --git a/arch/arm/dts/hi3798cv200-u-boot.dtsi b/arch/arm/dts/hi3798cv200-u-boot.dtsi index 7844c5208c..2de06d9529 100644 --- a/arch/arm/dts/hi3798cv200-u-boot.dtsi +++ b/arch/arm/dts/hi3798cv200-u-boot.dtsi @@ -8,7 +8,15 @@ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> */ +#include <dt-bindings/reset/ti-syscon.h> + &soc { + rst: reset-controller@8a22000 { + compatible = "hisilicon,hi3798cv200-reset"; + reg = <0x8a22000 0x1000>; + #reset-cells = <3>; + }; + usb2: ehci@9890000 { compatible = "generic-ehci"; reg = <0x9890000 0x100>; @@ -16,6 +24,12 @@ }; }; +&gmac1 { + resets = <&rst 0xcc 9 ASSERT_SET>, + <&rst 0xcc 11 ASSERT_SET>, + <&rst 0xcc 13 DEASSERT_SET>; +}; + &uart0 { clock = <75000000>; status = "okay"; diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts new file mode 100644 index 0000000000..c44dbdddf2 --- /dev/null +++ b/arch/arm/dts/meson-g12a-u200.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "meson-g12a.dtsi" + +/ { + compatible = "amlogic,u200", "amlogic,g12a"; + model = "Amlogic Meson G12A U200 Development Board"; + + aliases { + serial0 = &uart_AO; + }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; +}; + +&uart_AO { + status = "okay"; +}; + diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi new file mode 100644 index 0000000000..17c6217f8a --- /dev/null +++ b/arch/arm/dts/meson-g12a.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "amlogic,g12a"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + apb: bus@ff600000 { + compatible = "simple-bus"; + reg = <0x0 0xff600000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; + + periphs: bus@34400 { + compatible = "simple-bus"; + reg = <0x0 0x34400 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; + }; + + hiu: bus@3c000 { + compatible = "simple-bus"; + reg = <0x0 0x3c000 0x0 0x1400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; + + hhi: system-controller@0 { + compatible = "amlogic,meson-gx-hhi-sysctrl", + "simple-mfd", "syscon"; + reg = <0 0 0 0x400>; + + clkc: clock-controller { + compatible = "amlogic,g12a-clkc"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + }; + }; + }; + + aobus: bus@ff800000 { + compatible = "simple-bus"; + reg = <0x0 0xff800000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; + + uart_AO: serial@3000 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x3000 0x0 0x18>; + interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x4000 0x0 0x18>; + interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + cbus: bus@ffd00000 { + compatible = "simple-bus"; + reg = <0x0 0xffd00000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; + + clk_msr: clock-measure@18000 { + compatible = "amlogic,meson-g12a-clk-measure"; + reg = <0x0 0x18000 0x0 0x10>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + +}; diff --git a/arch/arm/dts/meson-gxbb-p200-u-boot.dtsi b/arch/arm/dts/meson-gxbb-p200-u-boot.dtsi new file mode 100644 index 0000000000..c35158d7e9 --- /dev/null +++ b/arch/arm/dts/meson-gxbb-p200-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include "meson-gx-u-boot.dtsi" diff --git a/arch/arm/dts/meson-gxbb-p200.dts b/arch/arm/dts/meson-gxbb-p200.dts new file mode 100644 index 0000000000..9d2406a7c4 --- /dev/null +++ b/arch/arm/dts/meson-gxbb-p200.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Andreas Färber + * Copyright (c) 2016 BayLibre, Inc. + * Author: Kevin Hilman <khilman@kernel.org> + */ + +/dts-v1/; + +#include "meson-gxbb-p20x.dtsi" +#include <dt-bindings/input/input.h> + +/ { + compatible = "amlogic,p200", "amlogic,meson-gxbb"; + model = "Amlogic Meson GXBB P200 Development Board"; + + avdd18_usb_adc: regulator-avdd18_usb_adc { + compatible = "regulator-fixed"; + regulator-name = "AVDD18_USB_ADC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + adc_keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-home { + label = "Home"; + linux,code = <KEY_HOME>; + press-threshold-microvolt = <900000>; /* 50% */ + }; + + button-esc { + label = "Esc"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <684000>; /* 38% */ + }; + + button-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <468000>; /* 26% */ + }; + + button-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <252000>; /* 14% */ + }; + + button-menu { + label = "Menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <0>; /* 0% */ + }; + }; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + amlogic,tx-delay-ns = <2>; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@3 { + /* Micrel KSZ9031 (0x00221620) */ + reg = <3>; + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_15 */ + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c_B { + status = "okay"; + pinctrl-0 = <&i2c_b_pins>; + pinctrl-names = "default"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avdd18_usb_adc>; +}; diff --git a/arch/arm/dts/meson-gxbb-p201-u-boot.dtsi b/arch/arm/dts/meson-gxbb-p201-u-boot.dtsi new file mode 100644 index 0000000000..c35158d7e9 --- /dev/null +++ b/arch/arm/dts/meson-gxbb-p201-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include "meson-gx-u-boot.dtsi" diff --git a/arch/arm/dts/meson-gxbb-p201.dts b/arch/arm/dts/meson-gxbb-p201.dts new file mode 100644 index 0000000000..56e0dd1ff5 --- /dev/null +++ b/arch/arm/dts/meson-gxbb-p201.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Andreas Färber + * Copyright (c) 2016 BayLibre, Inc. + * Author: Kevin Hilman <khilman@kernel.org> + */ + +/dts-v1/; + +#include "meson-gxbb-p20x.dtsi" + +/ { + compatible = "amlogic,p201", "amlogic,meson-gxbb"; + model = "Amlogic Meson GXBB P201 Development Board"; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rmii_pins>; + pinctrl-names = "default"; + phy-mode = "rmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; +}; diff --git a/arch/arm/dts/meson-gxbb-p20x.dtsi b/arch/arm/dts/meson-gxbb-p20x.dtsi new file mode 100644 index 0000000000..0be0f2a5d2 --- /dev/null +++ b/arch/arm/dts/meson-gxbb-p20x.dtsi @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Andreas Färber + * Copyright (c) 2016 BayLibre, Inc. + * Author: Kevin Hilman <khilman@kernel.org> + */ + +#include "meson-gxbb.dtsi" + +/ { + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + usb_pwr: regulator-usb-pwrs { + compatible = "regulator-fixed"; + + regulator-name = "USB_PWR"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + /* signal name in schematic: USB_PWR_EN */ + gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vddio_card: gpio-regulator { + compatible = "regulator-gpio"; + + regulator-name = "VDDIO_CARD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + + /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ + states = <1800000 0 + 3300000 1>; + + regulator-settling-time-up-us = <10000>; + regulator-settling-time-down-us = <150000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + cvbs_connector: cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_card>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb0_phy { + status = "okay"; + phy-supply = <&usb_pwr>; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts new file mode 100644 index 0000000000..82b1c48511 --- /dev/null +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * Author: Jerome Brunet <jbrunet@baylibre.com> + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> + +#include "meson-gxl-s905x.dtsi" + +/ { + compatible = "libretech,aml-s805x-ac", "amlogic,s805x", + "amlogic,meson-gxl"; + model = "Libre Computer Board AML-S805X-AC"; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + spi0 = &spifc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cvbs-connector { + /* + * The pads are present but no connector is soldered on + * 2J2, so keep this off by default. + */ + status = "disabled"; + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + dc_5v: regulator-dc_5v { + compatible = "regulator-fixed"; + regulator-name = "DC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + vcck: regulator-vcck { + compatible = "regulator-fixed"; + regulator-name = "VCCK"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_5v>; + + /* + * This is controlled by GPIOAO_9 we reserve this but + * claiming it as done below reset the board anyway + * Need to investigate this + * + * gpio = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; + * enable-active-high; + */ + regulator-always-on; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_5v>; + regulator-always-on; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +ðmac { + status = "okay"; +}; + +&internal_phy { + pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&gpio_ao { + gpio-line-names = "UART TX", + "UART RX", + "7J1 Header Pin31", + "", "", "", "", + "IR In", + "HDMI CEC", + "5V VCCK Regulator", + /* GPIO_TEST_N */ + ""; +}; + +&gpio { + gpio-line-names = /* Bank GPIOZ */ + "", "", "", "", "", "", "", + "", "", "", "", "", "", "", + "Eth Link LED", "Eth Activity LED", + /* Bank GPIOH */ + "HDMI HPD", "HDMI SDA", "HDMI SCL", + "", "7J1 Header Pin13", + "7J1 Header Pin15", + "7J1 Header Pin7", + "7J1 Header Pin12", + "7J1 Header Pin16", + "7J1 Header Pin18", + /* Bank BOOT */ + "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", + "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", + "eMMC Clk", "eMMC Reset", "eMMC CMD", + "SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk", + "", "SPI NOR Chip Select", + /* Bank CARD */ + "", "", "", "", "", "", "", + /* Bank GPIODV */ + "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", + "7J1 Header Pin27", "7J1 Header Pin28", "", + "7J1 Header Pin29", + "VCCK Regulator", "VDDEE Regulator", + /* Bank GPIOX */ + "7J1 Header Pin22", "7J1 Header Pin26", + "7J1 Header Pin36", "7J1 Header Pin38", + "7J1 Header Pin40", "7J1 Header Pin37", + "7J1 Header Pin33", "7J1 Header Pin35", + "7J1 Header Pin19", "7J1 Header Pin21", + "7J1 Header Pin24", "7J1 Header Pin23", + "7J1 Header Pin8", "7J1 Header Pin10", + "", "", "7J1 Header Pin32", "", "", + /* Bank GPIOCLK */ + "", ""; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&spifc { + status = "okay"; + pinctrl-0 = <&nor_pins>; + pinctrl-names = "default"; + + w25q32: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <3000000>; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi index 8f0bb3c44b..d5c3d78aaf 100644 --- a/arch/arm/dts/meson-gxl.dtsi +++ b/arch/arm/dts/meson-gxl.dtsi @@ -75,6 +75,10 @@ }; }; +&efuse { + clocks = <&clkc CLKID_EFUSE>; +}; + ðmac { reg = <0x0 0xc9410000 0x0 0x10000 0x0 0xc8834540 0x0 0x4>; @@ -112,6 +116,7 @@ mux { groups = "uart_tx_ao_a", "uart_rx_ao_a"; function = "uart_ao"; + bias-disable; }; }; @@ -120,6 +125,7 @@ groups = "uart_cts_ao_a", "uart_rts_ao_a"; function = "uart_ao"; + bias-disable; }; }; @@ -127,6 +133,7 @@ mux { groups = "uart_tx_ao_b", "uart_rx_ao_b"; function = "uart_ao_b"; + bias-disable; }; }; @@ -134,6 +141,7 @@ mux { groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; function = "uart_ao_b"; + bias-disable; }; }; @@ -142,6 +150,7 @@ groups = "uart_cts_ao_b", "uart_rts_ao_b"; function = "uart_ao_b"; + bias-disable; }; }; @@ -149,6 +158,7 @@ mux { groups = "remote_input_ao"; function = "remote_input_ao"; + bias-disable; }; }; @@ -157,6 +167,7 @@ groups = "i2c_sck_ao", "i2c_sda_ao"; function = "i2c_ao"; + bias-disable; }; }; @@ -164,6 +175,7 @@ mux { groups = "pwm_ao_a_3"; function = "pwm_ao_a"; + bias-disable; }; }; @@ -171,6 +183,7 @@ mux { groups = "pwm_ao_a_8"; function = "pwm_ao_a"; + bias-disable; }; }; @@ -178,6 +191,7 @@ mux { groups = "pwm_ao_b"; function = "pwm_ao_b"; + bias-disable; }; }; @@ -185,6 +199,7 @@ mux { groups = "pwm_ao_b_6"; function = "pwm_ao_b"; + bias-disable; }; }; @@ -192,6 +207,7 @@ mux { groups = "i2s_out_ch23_ao"; function = "i2s_out_ao"; + bias-disable; }; }; @@ -199,6 +215,7 @@ mux { groups = "i2s_out_ch45_ao"; function = "i2s_out_ao"; + bias-disable; }; }; @@ -206,6 +223,7 @@ mux { groups = "spdif_out_ao_6"; function = "spdif_out_ao"; + bias-disable; }; }; @@ -213,6 +231,7 @@ mux { groups = "spdif_out_ao_9"; function = "spdif_out_ao"; + bias-disable; }; }; @@ -220,6 +239,7 @@ mux { groups = "ao_cec"; function = "cec_ao"; + bias-disable; }; }; @@ -227,6 +247,7 @@ mux { groups = "ee_cec"; function = "cec_ao"; + bias-disable; }; }; }; @@ -239,6 +260,8 @@ &clkc_AO { compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; &gpio_intc { @@ -263,6 +286,8 @@ clkc: clock-controller { compatible = "amlogic,gxl-clkc"; #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; }; }; @@ -306,6 +331,7 @@ "emmc_cmd", "emmc_clk"; function = "emmc"; + bias-disable; }; }; @@ -313,6 +339,7 @@ mux { groups = "emmc_ds"; function = "emmc"; + bias-disable; }; }; @@ -320,9 +347,6 @@ mux { groups = "BOOT_8"; function = "gpio_periphs"; - }; - cfg-pull-down { - pins = "BOOT_8"; bias-pull-down; }; }; @@ -334,6 +358,7 @@ "nor_c", "nor_cs"; function = "nor"; + bias-disable; }; }; @@ -343,6 +368,7 @@ "spi_mosi", "spi_sclk"; function = "spi"; + bias-disable; }; }; @@ -350,6 +376,7 @@ mux { groups = "spi_ss0"; function = "spi"; + bias-disable; }; }; @@ -362,6 +389,7 @@ "sdcard_cmd", "sdcard_clk"; function = "sdcard"; + bias-disable; }; }; @@ -369,9 +397,6 @@ mux { groups = "CARD_2"; function = "gpio_periphs"; - }; - cfg-pull-down { - pins = "CARD_2"; bias-pull-down; }; }; @@ -385,6 +410,7 @@ "sdio_cmd", "sdio_clk"; function = "sdio"; + bias-disable; }; }; @@ -392,9 +418,6 @@ mux { groups = "GPIOX_4"; function = "gpio_periphs"; - }; - cfg-pull-down { - pins = "GPIOX_4"; bias-pull-down; }; }; @@ -403,6 +426,7 @@ mux { groups = "sdio_irq"; function = "sdio"; + bias-disable; }; }; @@ -411,6 +435,7 @@ groups = "uart_tx_a", "uart_rx_a"; function = "uart_a"; + bias-disable; }; }; @@ -419,6 +444,7 @@ groups = "uart_cts_a", "uart_rts_a"; function = "uart_a"; + bias-disable; }; }; @@ -427,6 +453,7 @@ groups = "uart_tx_b", "uart_rx_b"; function = "uart_b"; + bias-disable; }; }; @@ -435,6 +462,7 @@ groups = "uart_cts_b", "uart_rts_b"; function = "uart_b"; + bias-disable; }; }; @@ -443,6 +471,7 @@ groups = "uart_tx_c", "uart_rx_c"; function = "uart_c"; + bias-disable; }; }; @@ -451,6 +480,7 @@ groups = "uart_cts_c", "uart_rts_c"; function = "uart_c"; + bias-disable; }; }; @@ -459,6 +489,7 @@ groups = "i2c_sck_a", "i2c_sda_a"; function = "i2c_a"; + bias-disable; }; }; @@ -467,6 +498,7 @@ groups = "i2c_sck_b", "i2c_sda_b"; function = "i2c_b"; + bias-disable; }; }; @@ -475,6 +507,7 @@ groups = "i2c_sck_c", "i2c_sda_c"; function = "i2c_c"; + bias-disable; }; }; @@ -495,6 +528,7 @@ "eth_txd2", "eth_txd3"; function = "eth"; + bias-disable; }; }; @@ -502,6 +536,7 @@ mux { groups = "eth_link_led"; function = "eth_led"; + bias-disable; }; }; @@ -516,6 +551,7 @@ mux { groups = "pwm_a"; function = "pwm_a"; + bias-disable; }; }; @@ -523,6 +559,7 @@ mux { groups = "pwm_b"; function = "pwm_b"; + bias-disable; }; }; @@ -530,6 +567,7 @@ mux { groups = "pwm_c"; function = "pwm_c"; + bias-disable; }; }; @@ -537,6 +575,7 @@ mux { groups = "pwm_d"; function = "pwm_d"; + bias-disable; }; }; @@ -544,6 +583,7 @@ mux { groups = "pwm_e"; function = "pwm_e"; + bias-disable; }; }; @@ -551,6 +591,7 @@ mux { groups = "pwm_f_clk"; function = "pwm_f"; + bias-disable; }; }; @@ -558,6 +599,7 @@ mux { groups = "pwm_f_x"; function = "pwm_f"; + bias-disable; }; }; @@ -565,6 +607,7 @@ mux { groups = "hdmi_hpd"; function = "hdmi_hpd"; + bias-disable; }; }; @@ -572,6 +615,7 @@ mux { groups = "hdmi_sda", "hdmi_scl"; function = "hdmi_i2c"; + bias-disable; }; }; @@ -579,6 +623,7 @@ mux { groups = "i2s_am_clk"; function = "i2s_out"; + bias-disable; }; }; @@ -586,6 +631,7 @@ mux { groups = "i2s_out_ao_clk"; function = "i2s_out"; + bias-disable; }; }; @@ -593,6 +639,7 @@ mux { groups = "i2s_out_lr_clk"; function = "i2s_out"; + bias-disable; }; }; @@ -600,12 +647,14 @@ mux { groups = "i2s_out_ch01"; function = "i2s_out"; + bias-disable; }; }; i2sout_ch23_z_pins: i2sout_ch23_z { mux { groups = "i2sout_ch23_z"; function = "i2s_out"; + bias-disable; }; }; @@ -613,6 +662,7 @@ mux { groups = "i2sout_ch45_z"; function = "i2s_out"; + bias-disable; }; }; @@ -620,6 +670,7 @@ mux { groups = "i2sout_ch67_z"; function = "i2s_out"; + bias-disable; }; }; @@ -627,6 +678,7 @@ mux { groups = "spdif_out_h"; function = "spdif_out"; + bias-disable; }; }; }; diff --git a/arch/arm/dts/mt8516-u-boot.dtsi b/arch/arm/dts/mt8516-u-boot.dtsi new file mode 100644 index 0000000000..3c0d843f35 --- /dev/null +++ b/arch/arm/dts/mt8516-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 BayLibre, SAS + * Author: Fabien Parent <fparent@baylibre.com> + */ + +&infracfg { + u-boot,dm-pre-reloc; +}; + +&topckgen_ { + u-boot,dm-pre-reloc; +}; + +&topckgen_cg { + u-boot,dm-pre-reloc; +}; + +&apmixedsys { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/mt8516.dtsi b/arch/arm/dts/mt8516.dtsi new file mode 100644 index 0000000000..1c33582086 --- /dev/null +++ b/arch/arm/dts/mt8516.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 BayLibre, SAS + * Author: Fabien Parent <fparent@baylibre.com> + */ + +#include <dt-bindings/clock/mt8516-clk.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "mediatek,mt8516"; + interrupt-parent = <&sysirq>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt8516-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0>; + clock-frequency = <1300000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + clock-frequency = <1300000000>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + clock-frequency = <1300000000>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + clock-frequency = <1300000000>; + }; + }; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt8516-topckgen"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + topckgen_cg: clock-controller-cg@10000000 { + compatible = "mediatek,mt8516-topckgen-cg"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + infracfg: clock-controller@10001000 { + compatible = "mediatek,mt8516-infracfg"; + reg = <0x10001000 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: clock-controller@10018000 { + compatible = "mediatek,mt8516-apmixedsys"; + reg = <0x10018000 0x710>; + #clock-cells = <1>; + }; + + gic: interrupt-controller@10310000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10310000 0x1000>, + <0x10320000 0x1000>, + <0x10340000 0x2000>, + <0x10360000 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + sysirq: interrupt-controller@10200620 { + compatible = "mediatek,sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200620 0x20>; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,wdt"; + reg = <0x10007000 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>; + #reset-cells = <1>; + status = "disabled"; + }; + + pinctrl: pinctrl@10005000 { + compatible = "mediatek,mt8516-pinctrl"; + reg = <0x10005000 0x1000>; + + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + mmc0: mmc@11120000 { + compatible = "mediatek,mt8516-mmc"; + reg = <0x11120000 0x1000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen_cg CLK_TOP_MSDC0>, + <&topckgen CLK_TOP_AHB_INFRA_SEL>, + <&topckgen_cg CLK_TOP_MSDC0_INFRA>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + uart0: serial@11005000 { + compatible = "mediatek,hsuart"; + reg = <0x11005000 0x1000>; + reg-shift = <2>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART0_SEL>, + <&topckgen_cg CLK_TOP_UART0>; + clock-names = "baud","bus"; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi new file mode 100644 index 0000000000..322c858c4b --- /dev/null +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (c) 2019 Simon Goldschmidt + */ +/{ + soc { + u-boot,dm-pre-reloc; + }; +}; + +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 2458d6707d..51a6a51b53 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -84,6 +84,7 @@ #dma-requests = <32>; clocks = <&l4_main_clk>; clock-names = "apb_pclk"; + resets = <&rst DMA_RESET>; }; }; @@ -100,6 +101,7 @@ reg = <0xffc00000 0x1000>; interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; clocks = <&can0_clk>; + resets = <&rst CAN0_RESET>; status = "disabled"; }; @@ -108,6 +110,7 @@ reg = <0xffc01000 0x1000>; interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; clocks = <&can1_clk>; + resets = <&rst CAN1_RESET>; status = "disabled"; }; @@ -585,6 +588,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff708000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO0_RESET>; status = "disabled"; porta: gpio-controller@0 { @@ -605,6 +609,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff709000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO1_RESET>; status = "disabled"; portb: gpio-controller@0 { @@ -625,6 +630,7 @@ compatible = "snps,dw-apb-gpio"; reg = <0xff70a000 0x1000>; clocks = <&l4_mp_clk>; + resets = <&rst GPIO2_RESET>; status = "disabled"; portc: gpio-controller@0 { @@ -735,6 +741,7 @@ #size-cells = <0>; clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; + resets = <&rst SDMMC_RESET>; status = "disabled"; }; @@ -746,9 +753,9 @@ <0xffb80000 0x10000>; reg-names = "nand_data", "denali_reg"; interrupts = <0x0 0x90 0x4>; - dma-mask = <0xffffffff>; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>; status = "disabled"; }; @@ -759,7 +766,7 @@ qspi: spi@ff705000 { compatible = "cdns,qspi-nor"; - #address-cells = <1>; + #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, <0xffa00000 0x1000>; @@ -768,6 +775,7 @@ cdns,fifo-width = <4>; cdns,trigger-address = <0x00000000>; clocks = <&qspi_clk>; + resets = <&rst QSPI_RESET>; status = "disabled"; }; @@ -783,9 +791,10 @@ reg = <0xfffec000 0x100>; }; - sdr: sdr@ffc25000 { + sdr: sdr@ffc20000 { compatible = "altr,sdr-ctl", "syscon"; - reg = <0xffc25000 0x1000>; + reg = <0xffc20000 0x6000>; + resets = <&rst SDR_RESET>; }; sdramedac { @@ -802,6 +811,7 @@ interrupts = <0 154 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM0_RESET>; status = "disabled"; }; @@ -813,6 +823,7 @@ interrupts = <0 155 4>; num-cs = <4>; clocks = <&spi_m_clk>; + resets = <&rst SPIM1_RESET>; status = "disabled"; }; @@ -879,6 +890,7 @@ dmas = <&pdma 28>, <&pdma 29>; dma-names = "tx", "rx"; + resets = <&rst UART0_RESET>; }; uart1: serial1@ffc03000 { @@ -891,6 +903,7 @@ dmas = <&pdma 30>, <&pdma 31>; dma-names = "tx", "rx"; + resets = <&rst UART1_RESET>; }; usbphy0: usbphy { @@ -930,6 +943,7 @@ reg = <0xffd02000 0x1000>; interrupts = <0 171 4>; clocks = <&osc1>; + resets = <&rst L4WD0_RESET>; status = "disabled"; }; @@ -938,6 +952,7 @@ reg = <0xffd03000 0x1000>; interrupts = <0 172 4>; clocks = <&osc1>; + resets = <&rst L4WD1_RESET>; status = "disabled"; }; }; diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi index e75f2902c5..dfaff4c0f7 100644 --- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts index a387071674..6439daa525 100644 --- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts +++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts @@ -4,6 +4,7 @@ */ #include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" / { model = "Devboards.de DBM-SoC1"; @@ -24,10 +25,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi index 08d81da169..0219c6948d 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi @@ -6,14 +6,12 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index e9105743ea..b620dd8dda 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -6,6 +6,7 @@ */ #include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" / { model = "Terasic DE10-Nano"; @@ -26,10 +27,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts index 4f076bce93..ff1e61e0cb 100644 --- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts @@ -4,6 +4,7 @@ */ #include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" / { model = "Terasic DE1-SoC"; @@ -24,10 +25,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index 93e4d45ad2..2d31412923 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -4,6 +4,7 @@ */ #include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" / { model = "SoCFPGA Cyclone V IS1"; @@ -31,10 +32,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi index 2fafd7e399..7d9874cafa 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &can0 { diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi index 7ef30531f4..85cc396a70 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi index 1003115cea..0a4d54e304 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb1; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &watchdog0 { diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 93c3fa4a48..8d5d3996f6 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -76,7 +76,6 @@ &qspi { status = "okay"; - u-boot,dm-pre-reloc; flash: flash@0 { #address-cells = <1>; @@ -91,6 +90,5 @@ cdns,tchsh-ns = <4>; cdns,tslch-ns = <4>; status = "okay"; - u-boot,dm-pre-reloc; }; }; diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts index 1a18c4f3ba..bb29da6d6c 100644 --- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts @@ -4,6 +4,7 @@ */ #include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" / { model = "SoCFPGA Cyclone V SR1500"; @@ -27,10 +28,6 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; - - soc { - u-boot,dm-pre-reloc; - }; }; &gmac1 { diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index e05ca8279a..db55a4ecad 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -6,15 +6,13 @@ * Copyright (c) 2018 Simon Goldschmidt */ +#include "socfpga-common-u-boot.dtsi" + /{ aliases { spi0 = "/soc/spi@ff705000"; udc0 = &usb0; }; - - soc { - u-boot,dm-pre-reloc; - }; }; &watchdog0 { diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ee93725d64..d1ae2fabae 100644..100755 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -237,6 +237,19 @@ reg = <0xffe00000 0x100000>; }; + qspi: spi@ff8d2000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff8d2000 0x100>, + <0xff900000 0x100000>; + interrupts = <0 3 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + status = "disabled"; + }; + rst: rstmgr@ffd11000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi new file mode 100755 index 0000000000..e1cfb522bf --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +/{ + aliases { + spi0 = &qspi; + }; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index 6e8ddcd9f4..2745050810 100644..100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -36,7 +36,9 @@ memory { device_type = "memory"; - reg = <0 0 0 0x80000000>; /* 2GB */ + /* 4GB */ + reg = <0 0x00000000 0 0x80000000>, + <1 0x80000000 0 0x80000000>; u-boot,dm-pre-reloc; }; }; @@ -85,6 +87,41 @@ smplsel = <0>; }; +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00a"; + reg = <0>; + spi-max-frequency = <50000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x4000000>; + }; + + qspi_rootfs: partition@4000000 { + label = "Root Filesystem - JFFS2"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index c069875486..0aae69b0a0 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -375,6 +375,13 @@ }; }; + stusb1600_pins_a: stusb1600-0 { + pins { + pinmux = <STM32_PINMUX('I', 11, ANALOG)>; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index af7acfa037..0f32a38dc9 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -11,6 +11,7 @@ aliases { i2c3 = &i2c4; mmc0 = &sdmmc1; + usb0 = &usbotg_hs; }; config { u-boot,boot-led = "heartbeat"; @@ -190,7 +191,7 @@ }; &usbotg_hs { - usb1600; + u-boot,force-b-session-valid; hnp-srp-disable; }; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index 0882765d0c..e36773dde9 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -67,6 +67,24 @@ /delete-property/dmas; /delete-property/dma-names; + typec: stusb1600@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + pinctrl-names = "default"; + pinctrl-0 = <&stusb1600_pins_a>; + + status = "okay"; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "sink"; + power-opmode = "default"; + }; + }; + pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; @@ -249,11 +267,25 @@ status = "okay"; }; +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + &usbphyc { - vdd3v3-supply = <&vdd_usb>; status = "okay"; }; +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + &vrefbuf { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 8c0ff3c6ff..b10208f698 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -382,18 +382,10 @@ status = "okay"; }; -&usbotg_hs { - usb33d-supply = <&usb33>; -}; - &usbphyc_port0 { phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; }; &usbphyc_port1 { phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; }; diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 8b92b1fa2e..5b19e44d2f 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -12,6 +12,7 @@ i2c4 = &i2c5; pinctrl2 = &stmfx_pinctrl; spi0 = &qspi; + usb0 = &usbotg_hs; }; }; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index 7eb4bee31c..94634336a5 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -825,7 +825,7 @@ }; usbotg_hs: usb-otg@49000000 { - compatible = "snps,dwc2"; + compatible = "st,stm32mp1-hsotg", "snps,dwc2"; reg = <0x49000000 0x10000>; clocks = <&rcc USBO_K>; clock-names = "otg"; @@ -836,6 +836,7 @@ g-np-tx-fifo-size = <32>; g-tx-fifo-size = <128 128 64 64 64 64 32 32>; dr_mode = "otg"; + usb33d-supply = <&usb33>; status = "disabled"; }; @@ -1161,6 +1162,8 @@ reg = <0x5a006000 0x1000>; clocks = <&rcc USBPHY_K>; resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; status = "disabled"; usbphyc_port0: usb-phy@0 { diff --git a/arch/arm/include/asm/arch-meson/clock-g12a.h b/arch/arm/include/asm/arch-meson/clock-g12a.h new file mode 100644 index 0000000000..d52e27e008 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/clock-g12a.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> + * Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ +#ifndef _ARCH_MESON_CLOCK_G12A_H_ +#define _ARCH_MESON_CLOCK_G12A_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ + +#define HHI_MIPI_CNTL0 0x000 +#define HHI_MIPI_CNTL1 0x004 +#define HHI_MIPI_CNTL2 0x008 +#define HHI_MIPI_STS 0x00C +#define HHI_GP0_PLL_CNTL0 0x040 +#define HHI_GP0_PLL_CNTL1 0x044 +#define HHI_GP0_PLL_CNTL2 0x048 +#define HHI_GP0_PLL_CNTL3 0x04C +#define HHI_GP0_PLL_CNTL4 0x050 +#define HHI_GP0_PLL_CNTL5 0x054 +#define HHI_GP0_PLL_CNTL6 0x058 +#define HHI_GP0_PLL_STS 0x05C +#define HHI_PCIE_PLL_CNTL0 0x098 +#define HHI_PCIE_PLL_CNTL1 0x09C +#define HHI_PCIE_PLL_CNTL2 0x0A0 +#define HHI_PCIE_PLL_CNTL3 0x0A4 +#define HHI_PCIE_PLL_CNTL4 0x0A8 +#define HHI_PCIE_PLL_CNTL5 0x0AC +#define HHI_PCIE_PLL_STS 0x0B8 +#define HHI_HIFI_PLL_CNTL0 0x0D8 +#define HHI_HIFI_PLL_CNTL1 0x0DC +#define HHI_HIFI_PLL_CNTL2 0x0E0 +#define HHI_HIFI_PLL_CNTL3 0x0E4 +#define HHI_HIFI_PLL_CNTL4 0x0E8 +#define HHI_HIFI_PLL_CNTL5 0x0EC +#define HHI_HIFI_PLL_CNTL6 0x0F0 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12C +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_OTHER2 0x154 +#define HHI_VID_CLK_DIV 0x164 +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_AUD_CLK_CNTL 0x178 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1A0 +#define HHI_MALI_CLK_CNTL 0x1b0 +#define HHI_VPU_CLKC_CNTL 0x1b4 +#define HHI_VPU_CLK_CNTL 0x1bC +#define HHI_HDMI_CLK_CNTL 0x1CC +#define HHI_VDEC_CLK_CNTL 0x1E0 +#define HHI_VDEC2_CLK_CNTL 0x1E4 +#define HHI_VDEC3_CLK_CNTL 0x1E8 +#define HHI_VDEC4_CLK_CNTL 0x1EC +#define HHI_HDCP22_CLK_CNTL 0x1F0 +#define HHI_VAPBCLK_CNTL 0x1F4 +#define HHI_VPU_CLKB_CNTL 0x20C +#define HHI_GEN_CLK_CNTL 0x228 +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 +#define HHI_NAND_CLK_CNTL 0x25C +#define HHI_SD_EMMC_CLK_CNTL 0x264 +#define HHI_MPLL_CNTL0 0x278 +#define HHI_MPLL_CNTL1 0x27C +#define HHI_MPLL_CNTL2 0x280 +#define HHI_MPLL_CNTL3 0x284 +#define HHI_MPLL_CNTL4 0x288 +#define HHI_MPLL_CNTL5 0x28c +#define HHI_MPLL_CNTL6 0x290 +#define HHI_MPLL_CNTL7 0x294 +#define HHI_MPLL_CNTL8 0x298 +#define HHI_FIX_PLL_CNTL0 0x2A0 +#define HHI_FIX_PLL_CNTL1 0x2A4 +#define HHI_FIX_PLL_CNTL3 0x2AC +#define HHI_SYS_PLL_CNTL0 0x2f4 +#define HHI_SYS_PLL_CNTL1 0x2f8 +#define HHI_SYS_PLL_CNTL2 0x2fc +#define HHI_SYS_PLL_CNTL3 0x300 +#define HHI_SYS_PLL_CNTL4 0x304 +#define HHI_SYS_PLL_CNTL5 0x308 +#define HHI_SYS_PLL_CNTL6 0x30c +#define HHI_HDMI_PLL_CNTL0 0x320 +#define HHI_HDMI_PLL_CNTL1 0x324 +#define HHI_HDMI_PLL_CNTL2 0x328 +#define HHI_HDMI_PLL_CNTL3 0x32c +#define HHI_HDMI_PLL_CNTL4 0x330 +#define HHI_HDMI_PLL_CNTL5 0x334 +#define HHI_HDMI_PLL_CNTL6 0x338 +#define HHI_SPICC_CLK_CNTL 0x3dc + +#endif diff --git a/arch/arm/include/asm/arch-meson/g12a.h b/arch/arm/include/asm/arch-meson/g12a.h new file mode 100644 index 0000000000..b806667860 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/g12a.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef __G12A_H__ +#define __G12A_H__ + +#define G12A_AOBUS_BASE 0xff800000 +#define G12A_PERIPHS_BASE 0xff634400 +#define G12A_HIU_BASE 0xff63c000 +#define G12A_ETH_PHY_BASE 0xff64c000 +#define G12A_ETH_BASE 0xff3f0000 + +/* Always-On Peripherals registers */ +#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2)) + +#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90) +#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93) +#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94) +#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95) + +#define G12A_AO_BOOT_DEVICE 0xF +#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000 +#define G12A_AO_MEM_SIZE_SHIFT 16 +#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +/* Peripherals registers */ +#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2)) + +#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50) +#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51) + +#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0) +#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2) +#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10) +#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define G12A_ETH_REG_0_CLK_EN BIT(12) + +#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2)) +#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11) +#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12) +#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13) +#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14) +#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15) +#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16) +#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17) +#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18) +#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20) +#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21) +#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22) + +/* HIU registers */ +#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2)) + +#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40) + +/* Ethernet memory power domain */ +#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) + +#endif /* __G12A_H__ */ diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 12bc7fbe06..e6d27b69f9 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -123,6 +123,27 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) /* + * Relaxed I/O memory access primitives. These follow the Device memory + * ordering rules but do not guarantee any ordering relative to Normal memory + * accesses. + */ +#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) +#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ + __raw_readw(c)); __r; }) +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ + __raw_readl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \ + __raw_readq(c)); __r; }) + +#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c))) +#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \ + cpu_to_le16(v), (c))) +#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \ + cpu_to_le32(v), (c))) +#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \ + cpu_to_le64(v), (c))) + +/* * The compiler seems to be incapable of optimising constants * properly. Spell it out to the compiler in some cases. * These are only valid for small values of "off" (< 1<<12) diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h index d23044a1c3..50582c972b 100644 --- a/arch/arm/include/asm/secure.h +++ b/arch/arm/include/asm/secure.h @@ -6,6 +6,37 @@ #define __secure __attribute__ ((section ("._secure.text"))) #define __secure_data __attribute__ ((section ("._secure.data"))) +#ifndef __ASSEMBLY__ + +typedef struct secure_svc_tbl { + u32 id; +#ifdef CONFIG_ARMV8_PSCI + u8 pad[4]; +#endif + void *func; +} secure_svc_tbl_t; + +/* + * Macro to declare a SiP function service in '_secure_svc_tbl_entries' section + */ +#define DECLARE_SECURE_SVC(_name, _id, _fn) \ + static const secure_svc_tbl_t __secure_svc_ ## _name \ + __attribute__((used, section("._secure_svc_tbl_entries"))) \ + = { \ + .id = _id, \ + .func = _fn } + +#else + +#ifdef CONFIG_ARMV8_PSCI +#define SECURE_SVC_TBL_OFFSET 16 +#else +#define SECURE_SVC_TBL_OFFSET 8 + +#endif + +#endif /* __ASSEMBLY__ */ + #if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE) /* * Warning, horror ahead. diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S index 7603f52774..26d29c5324 100644 --- a/arch/arm/lib/relocate_64.S +++ b/arch/arm/lib/relocate_64.S @@ -26,9 +26,10 @@ ENTRY(relocate_code) /* * Copy u-boot from flash to RAM */ - adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */ - subs x9, x0, x1 /* x8 <- Run to copy offset */ - b.eq relocate_done /* skip relocation */ + adrp x1, __image_copy_start /* x1 <- address bits [31:12] */ + add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */ + subs x9, x0, x1 /* x9 <- Run to copy offset */ + b.eq relocate_done /* skip relocation */ /* * Don't ldr x1, __image_copy_start here, since if the code is already * running at an address other than it was linked to, that instruction @@ -42,8 +43,10 @@ ENTRY(relocate_code) ldr x1, _TEXT_BASE /* x1 <- Linked &__image_copy_start */ subs x9, x0, x1 /* x9 <- Link to copy offset */ - adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */ - adr x2, __image_copy_end /* x2 <- Run &__image_copy_end */ + adrp x1, __image_copy_start /* x1 <- address bits [31:12] */ + add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */ + adrp x2, __image_copy_end /* x2 <- address bits [31:12] */ + add x2, x2, :lo12:__image_copy_end /* x2 <- address bits [11:00] */ copy_loop: ldp x10, x11, [x1], #16 /* copy from source address [x1] */ stp x10, x11, [x0], #16 /* copy to target address [x0] */ @@ -54,8 +57,10 @@ copy_loop: /* * Fix .rela.dyn relocations */ - adr x2, __rel_dyn_start /* x2 <- Run &__rel_dyn_start */ - adr x3, __rel_dyn_end /* x3 <- Run &__rel_dyn_end */ + adrp x2, __rel_dyn_start /* x2 <- address bits [31:12] */ + add x2, x2, :lo12:__rel_dyn_start /* x2 <- address bits [11:00] */ + adrp x3, __rel_dyn_end /* x3 <- address bits [31:12] */ + add x3, x3, :lo12:__rel_dyn_end /* x3 <- address bits [11:00] */ fixloop: ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */ ldr x4, [x2], #8 /* x4 <- addend */ diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a089e9439e..c3b21b7557 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -180,6 +180,17 @@ config TARGET_SAMA5D27_SOM1_EK processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM in a single package. +config TARGET_SAMA5D2_ICP + bool "SAMA5D2 Industrial Connectivity Platform (ICP)" + select CPU_V7A + select SUPPORT_SPL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + help + The SAMA5D2 ICP embeds SAMA5D27 rev. C SoC, together with + a 64Mbit QSPI flash, 3xMikrobus connectors, 4xUSB , + EtherCat and WILC3000 devices on board. + config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" select BOARD_EARLY_INIT_F @@ -281,6 +292,7 @@ source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" +source "board/atmel/sama5d2_icp/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" source "board/atmel/sama5d4_xplained/Kconfig" diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 7a733e95df..b5e91d4a7d 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -31,6 +31,16 @@ config TARGET_MT7629 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, switch, USB3.0, PCIe, UART, SPI, I2C and PWM. +config TARGET_MT8516 + bool "MediaTek MT8516 SoC" + select ARM64 + select ARCH_MISC_INIT + help + The MediaTek MT8516 is a ARM64-based SoC with a quad-core Cortex-A35. + including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, + Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo + chip and several DDR3 and DDR4 options. + endchoice source "board/mediatek/mt7623/Kconfig" diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index b5d3a379bc..ea414dc407 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_TARGET_MT7623) += mt7623/ obj-$(CONFIG_TARGET_MT7629) += mt7629/ +obj-$(CONFIG_TARGET_MT8516) += mt8516/ diff --git a/arch/arm/mach-mediatek/mt8516/Makefile b/arch/arm/mach-mediatek/mt8516/Makefile new file mode 100644 index 0000000000..886ab7e4eb --- /dev/null +++ b/arch/arm/mach-mediatek/mt8516/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c new file mode 100644 index 0000000000..26a215a8b1 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2019 BayLibre, SAS + * Author: Fabien Parent <fparent@baylibre.com> + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/sections.h> +#include <dm/uclass.h> +#include <linux/io.h> +#include <dt-bindings/clock/mt8516-clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define WDOG_SWRST 0x10007014 +#define WDOG_SWRST_KEY 0x1209 + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int mtk_pll_early_init(void) +{ + unsigned long pll_rates[] = { + [CLK_APMIXED_ARMPLL] = 1300000000, + [CLK_APMIXED_MAINPLL] = 1501000000, + [CLK_APMIXED_UNIVPLL] = 1248000000, + [CLK_APMIXED_MMPLL] = 380000000, + }; + struct udevice *dev; + int ret, i; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(mtk_clk_apmixedsys), &dev); + if (ret) + return ret; + + /* configure default rate then enable apmixedsys */ + for (i = 0; i < ARRAY_SIZE(pll_rates); i++) { + struct clk clk = { .id = i, .dev = dev }; + + ret = clk_set_rate(&clk, pll_rates[i]); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + } + + return 0; +} + +int mtk_soc_early_init(void) +{ + int ret; + + /* initialize early clocks */ + ret = mtk_pll_early_init(); + if (ret) + return ret; + + return 0; +} + +void reset_cpu(ulong addr) +{ + while (1) { + writel(WDOG_SWRST_KEY, WDOG_SWRST); + mdelay(5); + } +} + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8516\n"); + return 0; +} + +static struct mm_region mt8516_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; +struct mm_region *mem_map = mt8516_mem_map; diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 11077bc6cc..e29e4c0acc 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -41,7 +41,13 @@ config MESON_AXG bool "AXG" select MESON64_COMMON help - Select this if your SoC is an A113X/D + Select this if your SoC is an A113X/D + +config MESON_G12A + bool "G12A" + select MESON64_COMMON + help + Select this if your SoC is an S905X/D2 endchoice @@ -61,10 +67,11 @@ config SYS_VENDOR config SYS_BOARD string "Board name" - default "odroid-c2" if MESON_GXBB + default "p200" if MESON_GXBB default "p212" if MESON_GXL default "q200" if MESON_GXM default "s400" if MESON_AXG + default "u200" if MESON_G12A default "" help This option contains information about board name. diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index b716e1a152..a9e4046f80 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -2,6 +2,7 @@ # # Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com> -obj-y += board-common.o sm.o +obj-y += board-common.o sm.o board-info.o obj-$(CONFIG_MESON_GX) += board-gx.o obj-$(CONFIG_MESON_AXG) += board-axg.o +obj-$(CONFIG_MESON_G12A) += board-g12a.o diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c new file mode 100644 index 0000000000..fc3764b960 --- /dev/null +++ b/arch/arm/mach-meson/board-g12a.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <asm/arch/boot.h> +#include <asm/arch/eth.h> +#include <asm/arch/g12a.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> +#include <phy.h> + +DECLARE_GLOBAL_DATA_PTR; + +int meson_get_boot_device(void) +{ + return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE; +} + +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_init_reserved_memory(void *fdt) +{ + u64 bl31_size, bl31_start; + u64 bl32_size, bl32_start; + u32 reg; + + /* + * Get ARM Trusted Firmware reserved memory zones in : + * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 + * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL + * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL + */ + reg = readl(G12A_AO_SEC_GP_CFG3); + + bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK) + >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; + bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; + + bl31_start = readl(G12A_AO_SEC_GP_CFG5); + bl32_start = readl(G12A_AO_SEC_GP_CFG4); + + /* Add BL31 reserved zone */ + if (bl31_start && bl31_size) + meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); + + /* Add BL32 reserved zone */ + if (bl32_start && bl32_size) + meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); +} + +phys_size_t get_effective_memsize(void) +{ + /* Size is reported in MiB, convert it in bytes */ + return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK) + >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M; +} + +static struct mm_region g12a_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = g12a_mem_map; + +static void g12a_enable_external_mdio(void) +{ + writel(0x0, ETH_PHY_CNTL2); +} + +static void g12a_enable_internal_mdio(void) +{ + /* Fire up the PHY PLL */ + writel(0x29c0040a, ETH_PLL_CNTL0); + writel(0x927e0000, ETH_PLL_CNTL1); + writel(0xac5f49e5, ETH_PLL_CNTL2); + writel(0x00000000, ETH_PLL_CNTL3); + writel(0x00000000, ETH_PLL_CNTL4); + writel(0x20200000, ETH_PLL_CNTL5); + writel(0x0000c002, ETH_PLL_CNTL6); + writel(0x00000023, ETH_PLL_CNTL7); + writel(0x39c0040a, ETH_PLL_CNTL0); + writel(0x19c0040a, ETH_PLL_CNTL0); + + /* Select the internal MDIO */ + writel(0x33000180, ETH_PHY_CNTL0); + writel(0x00074043, ETH_PHY_CNTL1); + writel(0x00000260, ETH_PHY_CNTL2); +} + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_eth_init(phy_interface_t mode, unsigned int flags) +{ + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII | + G12A_ETH_REG_0_TX_PHASE(1) | + G12A_ETH_REG_0_TX_RATIO(4) | + G12A_ETH_REG_0_PHY_CLK_EN | + G12A_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII | + G12A_ETH_REG_0_INVERT_RMII_CLK | + G12A_ETH_REG_0_CLK_EN); + + /* Use G12A RMII Internal PHY */ + if (flags & MESON_USE_INTERNAL_RMII_PHY) + g12a_enable_internal_mdio(); + else + g12a_enable_external_mdio(); + + break; + + default: + printf("Invalid Ethernet interface mode\n"); + return; + } + + /* Enable power gate */ + clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK); +} diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c new file mode 100644 index 0000000000..ba248e8ff6 --- /dev/null +++ b/arch/arm/mach-meson/board-info.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Julien Masson <jmasson@baylibre.com> + * (C) Copyright 2019 Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <linux/bitfield.h> +#include <regmap.h> +#include <syscon.h> + +#define AO_SEC_SD_CFG8 0xe0 +#define AO_SEC_SOCINFO_OFFSET AO_SEC_SD_CFG8 + +#define SOCINFO_MAJOR GENMASK(31, 24) +#define SOCINFO_PACK GENMASK(23, 16) +#define SOCINFO_MINOR GENMASK(15, 8) +#define SOCINFO_MISC GENMASK(7, 0) + +static const struct meson_gx_soc_id { + const char *name; + unsigned int id; +} soc_ids[] = { + { "GXBB", 0x1f }, + { "GXTVBB", 0x20 }, + { "GXL", 0x21 }, + { "GXM", 0x22 }, + { "TXL", 0x23 }, + { "TXLX", 0x24 }, + { "AXG", 0x25 }, + { "GXLX", 0x26 }, + { "TXHD", 0x27 }, + { "G12A", 0x28 }, + { "G12B", 0x29 }, +}; + +static const struct meson_gx_package_id { + const char *name; + unsigned int major_id; + unsigned int pack_id; + unsigned int pack_mask; +} soc_packages[] = { + { "S905", 0x1f, 0, 0x20 }, /* pack_id != 0x20 */ + { "S905H", 0x1f, 0x3, 0xf }, /* pack_id & 0xf == 0x3 */ + { "S905M", 0x1f, 0x20, 0xf0 }, /* pack_id == 0x20 */ + { "S905D", 0x21, 0, 0xf0 }, + { "S905X", 0x21, 0x80, 0xf0 }, + { "S905W", 0x21, 0xa0, 0xf0 }, + { "S905L", 0x21, 0xc0, 0xf0 }, + { "S905M2", 0x21, 0xe0, 0xf0 }, + { "S805X", 0x21, 0x30, 0xf0 }, + { "S805Y", 0x21, 0xb0, 0xf0 }, + { "S912", 0x22, 0, 0x0 }, /* Only S912 is known for GXM */ + { "962X", 0x24, 0x10, 0xf0 }, + { "962E", 0x24, 0x20, 0xf0 }, + { "A113X", 0x25, 0x37, 0xff }, + { "A113D", 0x25, 0x22, 0xff }, + { "S905D2", 0x28, 0x10, 0xf0 }, + { "S905X2", 0x28, 0x40, 0xf0 }, + { "S922X", 0x29, 0x40, 0xf0 }, +}; + +DECLARE_GLOBAL_DATA_PTR; + +static inline unsigned int socinfo_to_major(u32 socinfo) +{ + return FIELD_GET(SOCINFO_MAJOR, socinfo); +} + +static inline unsigned int socinfo_to_minor(u32 socinfo) +{ + return FIELD_GET(SOCINFO_MINOR, socinfo); +} + +static inline unsigned int socinfo_to_pack(u32 socinfo) +{ + return FIELD_GET(SOCINFO_PACK, socinfo); +} + +static inline unsigned int socinfo_to_misc(u32 socinfo) +{ + return FIELD_GET(SOCINFO_MISC, socinfo); +} + +static const char *socinfo_to_package_id(u32 socinfo) +{ + unsigned int pack = socinfo_to_pack(socinfo); + unsigned int major = socinfo_to_major(socinfo); + int i; + + for (i = 0 ; i < ARRAY_SIZE(soc_packages) ; ++i) { + if (soc_packages[i].major_id == major && + soc_packages[i].pack_id == + (pack & soc_packages[i].pack_mask)) + return soc_packages[i].name; + } + + return "Unknown"; +} + +static const char *socinfo_to_soc_id(u32 socinfo) +{ + unsigned int id = socinfo_to_major(socinfo); + int i; + + for (i = 0 ; i < ARRAY_SIZE(soc_ids) ; ++i) { + if (soc_ids[i].id == id) + return soc_ids[i].name; + } + + return "Unknown"; +} + +static void print_board_model(void) +{ + const char *model; + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + printf("Model: %s\n", model ? model : "Unknown"); +} + +int show_board_info(void) +{ + struct regmap *regmap; + int nodeoffset, ret; + ofnode node; + unsigned int socinfo; + + /* find the offset of compatible node */ + nodeoffset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, + "amlogic,meson-gx-ao-secure"); + if (nodeoffset < 0) + return 0; + + /* check if chip-id is available */ + if (!fdt_getprop(gd->fdt_blob, nodeoffset, "amlogic,has-chip-id", NULL)) + return 0; + + /* get regmap from the syscon node */ + node = offset_to_ofnode(nodeoffset); + regmap = syscon_node_to_regmap(node); + if (IS_ERR(regmap)) { + printf("%s: failed to get regmap\n", __func__); + return 0; + } + + /* read soc info */ + ret = regmap_read(regmap, AO_SEC_SOCINFO_OFFSET, &socinfo); + if (ret && !socinfo) { + printf("%s: invalid chipid value\n", __func__); + return 0; + } + + /* print board information */ + print_board_model(); + printf("Soc: Amlogic Meson %s (%s) Revision %x:%x (%x:%x)\n", + socinfo_to_soc_id(socinfo), + socinfo_to_package_id(socinfo), + socinfo_to_major(socinfo), + socinfo_to_minor(socinfo), + socinfo_to_pack(socinfo), + socinfo_to_misc(socinfo)); + + return 0; +} diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h index 31b73edabe..e186296791 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h @@ -9,6 +9,7 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +int cpu_has_been_warmreset(void); void socfpga_bridges_reset(int enable); @@ -47,6 +48,8 @@ struct socfpga_reset_manager { #define RSTMGR_MPUMODRST_CORE0 0 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 #define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 +/* Watchdogs and MPU warm reset mask */ +#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 /* * Define a reset identifier, from which a permodrst bank ID diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h index a238d5d17f..c41208591a 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h @@ -7,10 +7,6 @@ #ifndef __ASSEMBLY__ -unsigned long sdram_calculate_size(void); -int sdram_mmr_init_full(unsigned int sdr_phy_reg); -int sdram_calibration_full(void); - const struct socfpga_sdram_config *socfpga_get_sdram_config(void); void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h index ca68594445..f39206ca1e 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h @@ -22,6 +22,7 @@ int sdram_calibration_full(void); #define ECCCTRL1 0x100 #define ECCCTRL2 0x104 #define ERRINTEN 0x110 +#define ERRINTENS 0x114 #define INTMODE 0x11c #define INTSTAT 0x120 #define AUTOWB_CORRADDR 0x138 @@ -52,6 +53,10 @@ int sdram_calibration_full(void); #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f +#define DDR_HMC_ERRINTEN_INTMASK \ + (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ + DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK) + /* NOC DDR scheduler */ #define DDR_SCH_ID_COREID 0 #define DDR_SCH_ID_REVID 0x4 @@ -180,4 +185,8 @@ int sdram_calibration_full(void); #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ (((x) >> 0) & 0xFF) +/* Firewall DDR scheduler MPFE */ +#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 +#define FW_HMC_ADAPTOR_MPU_MASK BIT(0) + #endif /* _SDRAM_S10_H_ */ diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 6e11ba6cb2..9865f5b5b1 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -201,16 +201,6 @@ int arch_early_init_r(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(&altera_fpga[0]); -#ifdef CONFIG_DESIGNWARE_SPI - /* Get Designware SPI controller out of reset */ - socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); - socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); -#endif - -#ifdef CONFIG_NAND_DENALI - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); -#endif - return 0; } diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index f176c38495..f8dd787cc6 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -103,3 +103,12 @@ void reset_deassert_peripherals_handoff(void) writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst); writel(0, &reset_manager_base->per0modrst); } + +/* + * Return non-zero if the CPU has been warm reset + */ +int cpu_has_been_warmreset(void) +{ + return readl(&reset_manager_base->status) & + RSTMGR_L4WD_MPU_WARMRESET_MASK; +} diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 142b60f887..9dd0afb4bc 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -21,6 +21,7 @@ #include <debug_uart.h> #include <fdtdec.h> #include <watchdog.h> +#include <dm/uclass.h> DECLARE_GLOBAL_DATA_PTR; @@ -38,16 +39,12 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ case 0x3: /* NAND Flash (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); return BOOT_DEVICE_NAND; case 0x4: /* SD/MMC External Transceiver (1.8V) */ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); - socfpga_per_reset(SOCFPGA_RESET(DMA), 0); return BOOT_DEVICE_MMC1; case 0x6: /* QSPI Flash (1.8V) */ case 0x7: /* QSPI Flash (3.0V) */ - socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); return BOOT_DEVICE_SPI; default: printf("Invalid boot device (bsel=%08x)!\n", bsel); @@ -123,9 +120,9 @@ static void socfpga_pl310_clear(void) void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); - unsigned long sdram_size; unsigned long reg; int ret; + struct udevice *dev; /* * First C code to run. Clear fake OCRAM ECC first as SBE @@ -156,10 +153,7 @@ void board_init_f(ulong dummy) socfpga_bridges_reset(1); } - socfpga_per_reset(SOCFPGA_RESET(SDR), 0); - socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); - timer_init(); debug("Reconfigure Clock Manager\n"); @@ -181,8 +175,7 @@ void board_init_f(ulong dummy) sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0); - /* De-assert reset for peripherals and bridges based on handoff */ - reset_deassert_peripherals_handoff(); + /* De-assert reset for bridges based on handoff */ socfpga_bridges_reset(0); debug("Unfreezing/Thaw all I/O banks\n"); @@ -200,27 +193,16 @@ void board_init_f(ulong dummy) hang(); } + ret = uclass_get_device(UCLASS_RESET, 0, &dev); + if (ret) + debug("Reset init failed: %d\n", ret); + /* enable console uart printing */ preloader_console_init(); - if (sdram_mmr_init_full(0xffffffff) != 0) { - puts("SDRAM init failed.\n"); - hang(); - } - - debug("SDRAM: Calibrating PHY\n"); - /* SDRAM calibration */ - if (sdram_calibration_full() == 0) { - puts("SDRAM calibration failed.\n"); - hang(); - } - - sdram_size = sdram_calculate_size(); - debug("SDRAM: %ld MiB\n", sdram_size >> 20); - - /* Sanity check ensure correct SDRAM size specified */ - if (get_ram_size(0, sdram_size) != sdram_size) { - puts("SDRAM size check failed!\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); hang(); } diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index a3db20a819..a141ffe82a 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -181,17 +181,6 @@ void board_init_f(ulong dummy) hang(); } - gd->ram_size = sdram_calculate_size(); - printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20)); - - /* Sanity check ensure correct SDRAM size specified */ - debug("DDR: Running SDRAM size sanity check\n"); - if (get_ram_size(0, gd->ram_size) != gd->ram_size) { - puts("DDR: SDRAM size check failed!\n"); - hang(); - } - debug("DDR: SDRAM size check passed!\n"); - mbox_init(); #ifdef CONFIG_CADENCE_QSPI diff --git a/arch/mips/dts/brcm,bcm6838.dtsi b/arch/mips/dts/brcm,bcm6838.dtsi index c060802e8a..6676f83b2a 100644 --- a/arch/mips/dts/brcm,bcm6838.dtsi +++ b/arch/mips/dts/brcm,bcm6838.dtsi @@ -125,5 +125,18 @@ status = "disabled"; }; + + nand: nand-controller@14e02200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm6838", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x14e02200 0x180>, + <0x14e000f0 0x10>, + <0x14e02600 0x180>; + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm968380gerg.dts b/arch/mips/dts/brcm,bcm968380gerg.dts index 98471e3894..5a5ac0ea7d 100644 --- a/arch/mips/dts/brcm,bcm968380gerg.dts +++ b/arch/mips/dts/brcm,bcm968380gerg.dts @@ -50,3 +50,15 @@ &gpio_mid1 { status = "okay"; }; + +&nand { + status = "okay"; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + }; +}; diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index fc52f47f82..e956a05262 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -59,14 +59,6 @@ void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev, void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len); -/* - * sandbox_timer_add_offset() - * - * Allow tests to add to the time reported through lib/time.c functions - * offset: number of milliseconds to advance the system time - */ -void sandbox_timer_add_offset(unsigned long offset); - /** * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time * |