diff options
Diffstat (limited to 'arch')
134 files changed, 1591 insertions, 1516 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index e063ee0d23..78532f56ca 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -78,6 +78,7 @@ config SANDBOX imply LZMA imply SCSI imply CMD_SATA + imply CMD_SF_TEST config SH bool "SuperH architecture" @@ -111,6 +112,8 @@ config X86 imply CMD_GETTIME imply CMD_IO imply CMD_IRQ + imply CMD_SF_TEST + imply CMD_ZBOOT config XTENSA bool "Xtensa architecture" diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index 5798149046..a498ce5b29 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -85,7 +85,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) r2 = (unsigned int)images->ft_addr; } else { r0 = 1; - r2 = (unsigned int)getenv("bootargs"); + r2 = (unsigned int)env_get("bootargs"); } smp_set_core_boot_addr((unsigned long)kernel_entry, -1); diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9cfeedeebd..da9324b43c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -97,6 +97,9 @@ config ARM_ERRATA_833069 config ARM_ERRATA_833471 bool +config ARM_ERRATA_845369 + bool + config ARM_ERRATA_852421 bool @@ -308,6 +311,7 @@ config TARGET_GPLUGD config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS + imply CMD_SAVES help Support for TI's DaVinci platform. @@ -409,21 +413,25 @@ config TARGET_SPEAR300 bool "Support spear300" select CPU_ARM926EJS select BOARD_EARLY_INIT_F + imply CMD_SAVES config TARGET_SPEAR310 bool "Support spear310" select CPU_ARM926EJS select BOARD_EARLY_INIT_F + imply CMD_SAVES config TARGET_SPEAR320 bool "Support spear320" select CPU_ARM926EJS select BOARD_EARLY_INIT_F + imply CMD_SAVES config TARGET_SPEAR600 bool "Support spear600" select CPU_ARM926EJS select BOARD_EARLY_INIT_F + imply CMD_SAVES config TARGET_STV0991 bool "Support stv0991" @@ -488,7 +496,6 @@ config ARCH_BCM283X select DM_GPIO select OF_CONTROL imply FAT_WRITE - imply ENV_IS_IN_FAT config TARGET_VEXPRESS_CA15_TC2 bool "Support vexpress_ca15_tc2" @@ -575,6 +582,7 @@ config ARCH_KEYSTONE select CMD_POWEROFF imply CMD_MTDPARTS imply FIT + imply CMD_SAVES config ARCH_OMAP2PLUS bool "TI OMAP2+" @@ -612,6 +620,11 @@ config ARCH_MX6 select SYS_FSL_SEC_LE select SYS_THUMB_BUILD if SPL +if ARCH_MX6 +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" +endif + config ARCH_MX5 bool "Freescale MX5" select CPU_V7 @@ -700,6 +713,7 @@ config ARCH_VF610 select CPU_V7 select SYS_FSL_ERRATUM_ESDHC111 imply CMD_MTDPARTS + imply NAND config ARCH_ZYNQ bool "Xilinx Zynq Platform" @@ -726,6 +740,7 @@ config ARCH_ZYNQ select CLK_ZYNQ imply CMD_CLK imply FAT_WRITE + imply CMD_SPL config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" @@ -1026,7 +1041,6 @@ config ARCH_UNIPHIER select SPL_PINCTRL if SPL select SUPPORT_SPL imply FAT_WRITE - imply ENV_IS_IN_MMC help Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) @@ -1225,3 +1239,10 @@ source "board/zipitz2/Kconfig" source "arch/arm/Kconfig.debug" endmenu + +config SPL_LDSCRIPT + default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if TARGET_APX4DEVKIT || TARGET_BG0900 || TARGET_M28EVK || TARGET_MX23_OLINUXINO || TARGET_MX23EVK || TARGET_MX28EVK || TARGET_SANSA_FUZE_PLUS || TARGET_SC_SPS_1 || TARGET_TS4600 || TARGET_XFI3 + default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 + + diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c index a60f5838de..ba1e559157 100644 --- a/arch/arm/cpu/arm926ejs/spear/spl.c +++ b/arch/arm/cpu/arm926ejs/spear/spl.c @@ -222,7 +222,7 @@ static void snor_init(void) u32 spl_boot_device(void) { - u32 mode; + u32 mode = 0; /* Currently only SNOR is supported as the only */ if (snor_boot_selected()) { diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c index 79fafa08ed..89e367be82 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c @@ -479,9 +479,9 @@ unsigned long clk_get_rate(struct clk *c) { unsigned long rate; - debug("%s: %s\n", __func__, c->name); if (!c || !c->ops || !c->ops->get_rate) return 0; + debug("%s: %s\n", __func__, c->name); rate = c->ops->get_rate(c); debug("%s: rate = %ld\n", __func__, rate); @@ -493,9 +493,9 @@ int clk_set_rate(struct clk *c, unsigned long rate) { int ret; - debug("%s: %s rate=%ld\n", __func__, c->name, rate); if (!c || !c->ops || !c->ops->set_rate) return -EINVAL; + debug("%s: %s rate=%ld\n", __func__, c->name, rate); if (c->use_cnt) return -EINVAL; diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c index cdc1264d7c..b061c20648 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c @@ -479,9 +479,9 @@ unsigned long clk_get_rate(struct clk *c) { unsigned long rate; - debug("%s: %s\n", __func__, c->name); if (!c || !c->ops || !c->ops->get_rate) return 0; + debug("%s: %s\n", __func__, c->name); rate = c->ops->get_rate(c); debug("%s: rate = %ld\n", __func__, rate); @@ -493,9 +493,9 @@ int clk_set_rate(struct clk *c, unsigned long rate) { int ret; - debug("%s: %s rate=%ld\n", __func__, c->name, rate); if (!c || !c->ops || !c->ops->set_rate) return -EINVAL; + debug("%s: %s rate=%ld\n", __func__, c->name, rate); if (c->use_cnt) return -EINVAL; diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 6a013b2183..fadfce4f05 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -15,6 +15,7 @@ config ARCH_LS1021A select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE imply SCSI + imply CMD_PCI menu "LS102xA architecture" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index f06fd28940..7b84a7a0f1 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -187,6 +187,12 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_845369 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 22 @ set bit #22 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + mov r5, lr @ Store my Caller mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) mov r3, r1, lsr #20 @ get variant field diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index ac2d8d1a3f..88f3f4dd16 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -329,7 +329,7 @@ int arch_misc_init(void) strcpy(soc, "vf"); strcat(soc, soc_type); - setenv("soc", soc); + env_set("soc", soc); return 0; } diff --git a/arch/arm/cpu/armv7m/mpu.c b/arch/arm/cpu/armv7m/mpu.c index 31a243b49a..4622aa4826 100644 --- a/arch/arm/cpu/armv7m/mpu.c +++ b/arch/arm/cpu/armv7m/mpu.c @@ -68,6 +68,7 @@ void mpu_config(struct mpu_region_config *reg_config) break; case DEVICE_NON_SHARED: attr = (2 << TEX_SHIFT) | BUFFERABLE; + break; default: attr = 0; /* strongly ordered */ break; diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index c447085fe4..1249547436 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -8,7 +8,9 @@ extra-y := start.o obj-y += cpu.o +ifndef CONFIG_$(SPL_TPL_)TIMER obj-y += generic_timer.o +endif obj-y += cache_v8.o obj-y += exceptions.o obj-y += cache.o diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 7cba308ee7..ea845d1809 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -22,6 +22,7 @@ * x1: 0 clean & invalidate, 1 invalidate only * x2~x9: clobbered */ +.pushsection .text.__asm_dcache_level, "ax" ENTRY(__asm_dcache_level) lsl x12, x0, #1 msr csselr_el1, x12 /* select cache level */ @@ -58,6 +59,7 @@ loop_way: ret ENDPROC(__asm_dcache_level) +.popsection /* * void __asm_flush_dcache_all(int invalidate_only) @@ -66,6 +68,7 @@ ENDPROC(__asm_dcache_level) * * flush or invalidate all data cache by SET/WAY. */ +.pushsection .text.__asm_dcache_all, "ax" ENTRY(__asm_dcache_all) mov x1, x0 dsb sy @@ -102,16 +105,21 @@ skip: finished: ret ENDPROC(__asm_dcache_all) +.popsection +.pushsection .text.__asm_flush_dcache_all, "ax" ENTRY(__asm_flush_dcache_all) mov x0, #0 b __asm_dcache_all ENDPROC(__asm_flush_dcache_all) +.popsection +.pushsection .text.__asm_invalidate_dcache_all, "ax" ENTRY(__asm_invalidate_dcache_all) mov x0, #0x1 b __asm_dcache_all ENDPROC(__asm_invalidate_dcache_all) +.popsection /* * void __asm_flush_dcache_range(start, end) @@ -121,6 +129,7 @@ ENDPROC(__asm_invalidate_dcache_all) * x0: start address * x1: end address */ +.pushsection .text.__asm_flush_dcache_range, "ax" ENTRY(__asm_flush_dcache_range) mrs x3, ctr_el0 lsr x3, x3, #16 @@ -138,6 +147,7 @@ ENTRY(__asm_flush_dcache_range) dsb sy ret ENDPROC(__asm_flush_dcache_range) +.popsection /* * void __asm_invalidate_dcache_range(start, end) * @@ -146,6 +156,7 @@ ENDPROC(__asm_flush_dcache_range) * x0: start address * x1: end address */ +.pushsection .text.__asm_invalidate_dcache_range, "ax" ENTRY(__asm_invalidate_dcache_range) mrs x3, ctr_el0 ubfm x3, x3, #16, #19 @@ -162,41 +173,51 @@ ENTRY(__asm_invalidate_dcache_range) dsb sy ret ENDPROC(__asm_invalidate_dcache_range) +.popsection /* * void __asm_invalidate_icache_all(void) * * invalidate all tlb entries. */ +.pushsection .text.__asm_invalidate_icache_all, "ax" ENTRY(__asm_invalidate_icache_all) ic ialluis isb sy ret ENDPROC(__asm_invalidate_icache_all) +.popsection +.pushsection .text.__asm_invalidate_l3_dcache, "ax" ENTRY(__asm_invalidate_l3_dcache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_invalidate_l3_dcache) .weak __asm_invalidate_l3_dcache +.popsection +.pushsection .text.__asm_flush_l3_dcache, "ax" ENTRY(__asm_flush_l3_dcache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_flush_l3_dcache) .weak __asm_flush_l3_dcache +.popsection +.pushsection .text.__asm_invalidate_l3_icache, "ax" ENTRY(__asm_invalidate_l3_icache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_invalidate_l3_icache) .weak __asm_invalidate_l3_icache +.popsection /* * void __asm_switch_ttbr(ulong new_ttbr) * * Safely switches to a new page table. */ +.pushsection .text.__asm_switch_ttbr, "ax" ENTRY(__asm_switch_ttbr) /* x2 = SCTLR (alive throghout the function) */ switch_el x4, 3f, 2f, 1f @@ -244,3 +265,4 @@ ENTRY(__asm_switch_ttbr) ret x3 ENDPROC(__asm_switch_ttbr) +.popsection diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5825f9b726..cdeef26fe5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -27,6 +27,7 @@ config ARCH_LS1043A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F imply SCSI + imply CMD_PCI config ARCH_LS1046A bool @@ -307,7 +308,7 @@ config SYS_FSL_DSPI_CLK_DIV default 2 help This is the divider that is used to derive DSPI clock from Platform - PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. + clock, in another word DSPI_clk = Platform_clk / this_divider. config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" @@ -392,3 +393,6 @@ config SYS_MC_RSV_MEM_ALIGN help Reserved memory needs to be aligned for MC to use. Default value is 512MB. + +config SPL_LDSCRIPT + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index aee1ffa7d4..639e9d2ddc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -95,7 +95,7 @@ static void erratum_a008514(void) static unsigned long get_internval_val_mhz(void) { - char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); + char *interval = env_get(PLATFORM_CYCLE_ENV_VAR); /* * interval is the number of platform cycles(MHz) between * wake up events generated by EPU. diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S index 945445bc37..6743111b6a 100644 --- a/arch/arm/cpu/armv8/tlb.S +++ b/arch/arm/cpu/armv8/tlb.S @@ -14,7 +14,8 @@ * void __asm_invalidate_tlb_all(void) * * invalidate all tlb entries. - */ +*/ +.pushsection .text.__asm_invalidate_tlb_all, "ax" ENTRY(__asm_invalidate_tlb_all) switch_el x9, 3f, 2f, 1f 3: tlbi alle3 @@ -31,3 +32,4 @@ ENTRY(__asm_invalidate_tlb_all) 0: ret ENDPROC(__asm_invalidate_tlb_all) +.popsection diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index ca07465376..7aa6935318 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -10,6 +10,7 @@ #include <linux/linkage.h> #include <asm/macro.h> +.pushsection .text.armv8_switch_to_el2, "ax" ENTRY(armv8_switch_to_el2) switch_el x6, 1f, 0f, 0f 0: @@ -30,7 +31,9 @@ ENTRY(armv8_switch_to_el2) br x4 1: armv8_switch_to_el2_m x4, x5, x6 ENDPROC(armv8_switch_to_el2) +.popsection +.pushsection .text.armv8_switch_to_el1, "ax" ENTRY(armv8_switch_to_el1) switch_el x6, 0f, 1f, 0f 0: @@ -40,7 +43,10 @@ ENTRY(armv8_switch_to_el1) br x4 1: armv8_switch_to_el1_m x4, x5, x6 ENDPROC(armv8_switch_to_el1) +.popsection +.pushsection .text.armv8_el2_to_aarch32, "ax" WEAK(armv8_el2_to_aarch32) ret ENDPROC(armv8_el2_to_aarch32) +.popsection diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 21a8103aee..f94c2471b4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ rk3328-evb.dtb \ + rk3368-lion.dtb \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ rk3368-px5-evb.dtb \ diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index 37137c2e52..64f1c2d7da 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -72,6 +72,17 @@ status = "okay"; }; +&sdmmc { + status = "okay"; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + supports-sd; +}; + &uart2 { status = "okay"; }; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index 4f2a1f6a15..22324f97b3 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -21,6 +21,8 @@ serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; + mmc0 = &emmc; + mmc1 = &sdmmc; }; cpus { @@ -383,12 +385,38 @@ status = "disabled"; }; + sdmmc: dwmmc@30000000 { + compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x30000000 0x4000>; + max-frequency = <150000000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "disabled"; + }; + + sdio: dwmmc@30010000 { + compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x30010000 0x4000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; + status = "disabled"; + }; + emmc: dwmmc@30020000 { compatible = "rockchip,rk3288-dw-mshc"; reg = <0x30020000 0x4000>; + max-frequency = <150000000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <37500000>; - max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; @@ -520,6 +548,40 @@ drive-strength = <12>; }; + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + }; + + sdio { + sdio_clk: sdio-clk { + rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + + sdio_cmd: sdio-cmd { + rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + + sdio_bus4: sdio-bus4 { + rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + }; + emmc { emmc_clk: emmc-clk { rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; diff --git a/arch/arm/dts/rk3368-geekbox-u-boot.dtsi b/arch/arm/dts/rk3368-geekbox-u-boot.dtsi new file mode 100644 index 0000000000..764b3e4cb4 --- /dev/null +++ b/arch/arm/dts/rk3368-geekbox-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&service_msch { + u-boot,dm-pre-reloc; +}; + +&dmc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-u-boot.dtsi new file mode 100644 index 0000000000..6052e8a8d3 --- /dev/null +++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/ { + config { + u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */ + u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &emmc, &sdmmc; + }; + +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&service_msch { + u-boot,dm-pre-reloc; +}; + +&dmc { + u-boot,dm-pre-reloc; + + /* + * Validation of throughput using SPEC2000 shows the following + * relative performance for the different memory schedules: + * - CBDR: 30.1 + * - CBRD: 29.8 + * - CRBD: 29.9 + * Note that the best performance for any given application workload + * may vary from the default configured here (e.g. 164.gzip is fastest + * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD). + * + * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for + * details on the 'rockchip,memory-schedule' property and how it + * affects the physical-address to device-address mapping. + */ + rockchip,memory-schedule = <DMC_MSCH_CBDR>; + rockchip,ddr-frequency = <800000000>; + rockchip,ddr-speed-bin = <DDR3_1600K>; + + status = "okay"; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&sgrf { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&spi1 { + u-boot,dm-pre-reloc; + + spiflash: w25q32dw@0 { + u-boot,dm-pre-reloc; + }; +}; + +&timer0 { + u-boot,dm-pre-reloc; + clock-frequency = <24000000>; +}; + + diff --git a/arch/arm/dts/rk3368-lion.dts b/arch/arm/dts/rk3368-lion.dts new file mode 100644 index 0000000000..850db500e4 --- /dev/null +++ b/arch/arm/dts/rk3368-lion.dts @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include "rk3368-lion-u-boot.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "Theobroma Systems RK3368-uQ7 SoM"; + compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368"; + + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&uart0 { + status = "okay"; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + clock-frequency = <150000000>; + disable-wp; + keep-power-in-suspend; + non-removable; + num-slots = <1>; + vmmc-supply = <&vcc33_io>; + vqmmc-supply = <&vcc18_io>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; +}; + +&sdmmc { + status = "okay"; +}; + +&gmac { + status = "okay"; + phy-supply = <&vcc33_io>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <2 10000 50000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x10>; + rx_delay = <0x10>; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + rockchip,system-power-controller; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_sys>; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu"; + }; + + vdd_log: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_log"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc33_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_io"; + }; + + vcc33_video: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_video"; + }; + + vdd10_pll: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_pll"; + }; + + vcc18_io: LDO_REG4 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_io"; + }; + + vdd10_video: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_video"; + }; + + vcc18_video: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_video"; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + spiflash: w25q32dw@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <49500000>; + spi-cpol; + spi-cpha; + }; +}; diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi new file mode 100644 index 0000000000..3a5e30ea55 --- /dev/null +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&service_msch { + u-boot,dm-pre-reloc; +}; + +&dmc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3368-sheep-u-boot.dtsi b/arch/arm/dts/rk3368-sheep-u-boot.dtsi new file mode 100644 index 0000000000..764b3e4cb4 --- /dev/null +++ b/arch/arm/dts/rk3368-sheep-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&service_msch { + u-boot,dm-pre-reloc; +}; + +&dmc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index 9daf765430..b4f4f6139d 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -46,6 +46,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/memory/rk3368-dmc.h> / { compatible = "rockchip,rk3368"; @@ -227,6 +228,21 @@ #clock-cells = <0>; }; + dmc: dmc@ff610000 { + compatible = "rockchip,rk3368-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,msch = <&service_msch>; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + service_msch: syscon@ffac0000 { + compatible = "rockchip,rk3368-msch", "syscon"; + reg = <0x0 0xffac0000 0x0 0x2000>; + status = "okay"; + }; + sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0c0000 0x0 0x4000>; @@ -546,12 +562,6 @@ status = "disabled"; }; - dmc: dmc@ff610000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3368-dmc", "syscon"; - reg = <0x0 0xff610000 0x0 0x1000>; - }; - i2c0: i2c@ff650000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff650000 0x0 0x1000>; @@ -647,11 +657,15 @@ }; pmugrf: syscon@ff738000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-pmugrf", "syscon"; reg = <0x0 0xff738000 0x0 0x1000>; }; + sgrf: syscon@ff740000 { + compatible = "rockchip,rk3368-sgrf", "syscon"; + reg = <0x0 0xff740000 0x0 0x1000>; + }; + cru: clock-controller@ff760000 { compatible = "rockchip,rk3368-cru"; reg = <0x0 0xff760000 0x0 0x1000>; @@ -673,7 +687,7 @@ status = "disabled"; }; - timer@ff810000 { + timer0: timer@ff810000 { compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; reg = <0x0 0xff810000 0x0 0x20>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8ad199f60a..4afc338b8e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -35,6 +35,7 @@ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index a8456a284a..41f7240a35 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -863,7 +863,7 @@ MX6_PAD_DECL(SD3_DAT4__SD3_DATA4, 0x069C, 0x02B4, 0, 0x0000, 0, 0) MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA, 0x069C, 0x02B4, 1, 0x0000, 0, 0) MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA, 0x069C, 0x02B4, 1, 0x0928, 5, 0) MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01, 0x069C, 0x02B4, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD3_CMD__SD3_CMD, 0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) MX6_PAD_DECL(SD3_CMD__UART2_CTS_B, 0x06A0, 0x02B8, 1, 0x0000, 0, 0) MX6_PAD_DECL(SD3_CMD__UART2_RTS_B, 0x06A0, 0x02B8, 1, 0x0924, 2, 0) MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX, 0x06A0, 0x02B8, 2, 0x0000, 0, 0) @@ -924,7 +924,7 @@ MX6_PAD_DECL(NANDF_CS3__ESAI_TX1, 0x06D8, 0x02F0, 2, 0x0878, 1, 0) MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26, 0x06D8, 0x02F0, 3, 0x0000, 0, 0) MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16, 0x06D8, 0x02F0, 5, 0x0000, 0, 0) MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1, 0x06D8, 0x02F0, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD4_CMD__SD4_CMD, 0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) MX6_PAD_DECL(SD4_CMD__NAND_RE_B, 0x06DC, 0x02F4, 1, 0x0000, 0, 0) MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA, 0x06DC, 0x02F4, 2, 0x0000, 0, 0) MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA, 0x06DC, 0x02F4, 2, 0x0930, 2, 0) @@ -1001,7 +1001,7 @@ MX6_PAD_DECL(SD1_DAT3__PWM1_OUT, 0x072C, 0x0344, 3, 0x0000, 0, 0) MX6_PAD_DECL(SD1_DAT3__WDOG2_B, 0x072C, 0x0344, 4, 0x0000, 0, 0) MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21, 0x072C, 0x0344, 5, 0x0000, 0, 0) MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB, 0x072C, 0x0344, 6, 0x0000, 0, 0) -MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD1_CMD__SD1_CMD, 0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI, 0x0730, 0x0348, 1, 0x0830, 0, 0) MX6_PAD_DECL(SD1_CMD__PWM4_OUT, 0x0730, 0x0348, 2, 0x0000, 0, 0) MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1, 0x0730, 0x0348, 3, 0x0000, 0, 0) @@ -1022,7 +1022,7 @@ MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK, 0x073C, 0x0354, 1, 0x0828, 1, 0) MX6_PAD_DECL(SD2_CLK__KEY_COL5, 0x073C, 0x0354, 2, 0x08E8, 3, 0) MX6_PAD_DECL(SD2_CLK__AUD4_RXFS, 0x073C, 0x0354, 3, 0x07C0, 1, 0) MX6_PAD_DECL(SD2_CLK__GPIO1_IO10, 0x073C, 0x0354, 5, 0x0000, 0, 0) -MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 16, 0x0000, 0, 0) +MX6_PAD_DECL(SD2_CMD__SD2_CMD, 0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0) MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI, 0x0740, 0x0358, 1, 0x0830, 1, 0) MX6_PAD_DECL(SD2_CMD__KEY_ROW5, 0x0740, 0x0358, 2, 0x08F4, 2, 0) MX6_PAD_DECL(SD2_CMD__AUD4_RXC, 0x0740, 0x0358, 3, 0x07BC, 1, 0) diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 0c99bbdc93..dbe340d23e 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -236,8 +236,21 @@ #define VDD_MPU_ES2_HIGH 1250 #define VDD_MM_ES2_OD 1120 -#define VDD_MPU_ES2_LOW 880 -#define VDD_MM_ES2_LOW 880 +/* Efuse register offsets for OMAP5 platform */ +#define OMAP5_ES2_EFUSE_BASE 0x4A002000 +#define OMAP5_ES2_PROD_REGBITS 16 + +/* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */ +#define OMAP5_ES2_PROD_CORE_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1D8) + +/* CONTROL_STD_FUSE_OPP_VDD_MM_4 */ +#define OMAP5_ES2_PROD_MM_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A4) +/* CONTROL_STD_FUSE_OPP_VDD_MM_5 */ +#define OMAP5_ES2_PROD_MM_OPOD_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A8) +/* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */ +#define OMAP5_ES2_PROD_MPU_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C4) +/* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */ +#define OMAP5_ES2_PROD_MPU_OPHI_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C8) /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */ #define VDD_MPU_DRA7_NOM 1150 diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 2f005dd3ad..b047f0d650 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -224,8 +224,8 @@ struct s32ktimer { #define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28) /* ABB efuse masks */ -#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) -#define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) +#define OMAP5_PROD_ABB_FUSE_VSET_MASK (0x1F << 20) +#define OMAP5_PROD_ABB_FUSE_ENABLE_MASK (0x1 << 25) #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index cb0a935edc..c7e21bd605 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -85,7 +85,7 @@ enum { EMMC_PLL_SELECT_24MHZ, EMMC_DIV_SHIFT = 8, - EMMC_DIV_MASK = 0x3f < EMMC_DIV_SHIFT, + EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, SDIO0_PLL_SHIFT = 6, SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index 24a9cc0525..2b1197fd46 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -89,19 +89,26 @@ enum { MCU_CLK_DIV_SHIFT = 0, MCU_CLK_DIV_MASK = GENMASK(4, 0), + /* CLKSEL43_CON */ + GMAC_MUX_SEL_EXTCLK = BIT(8), + /* CLKSEL51_CON */ MMC_PLL_SEL_SHIFT = 8, MMC_PLL_SEL_MASK = GENMASK(9, 8), - MMC_PLL_SEL_CPLL = 0, - MMC_PLL_SEL_GPLL, - MMC_PLL_SEL_USBPHY_480M, - MMC_PLL_SEL_24M, + MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT), MMC_CLK_DIV_SHIFT = 0, MMC_CLK_DIV_MASK = GENMASK(6, 0), /* SOFTRST1_CON */ MCU_PO_SRST_MASK = BIT(13), MCU_SYS_SRST_MASK = BIT(12), + DMA1_SRST_REQ = BIT(2), + + /* SOFTRST4_CON */ + DMA2_SRST_REQ = BIT(0), /* GLB_RST_CON */ PMU_GLB_SRST_CTRL_SHIFT = 2, diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file mode 100644 index 0000000000..4e2b2337f2 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only + * in a few details. Most notably, it has an additional field to track + * tREFI in controller cycles (i.e. trefi_mem_ddr3). + */ +struct rk3368_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; + u32 trefi_mem_ddr3; + u32 reserved5[45]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[2]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[2]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[3]; + u32 dfilpcfg0; + u32 reserved13[3]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[46]; + u32 ipvr; + u32 iptr; +}; +check_member(rk3368_ddr_pctl, iptr, 0x03fc); + +struct rk3368_ddrphy { + u32 reg[0x100]; +}; +check_member(rk3368_ddrphy, reg[0xff], 0x03fc); + +struct rk3368_msch { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 reserved1[8]; + u32 activate; + u32 devtodev; +}; +check_member(rk3368_msch, devtodev, 0x003c); + +/* GRF_SOC_CON0 */ +enum { + NOC_RSP_ERR_STALL = BIT(9), + MOBILE_DDR_SEL = BIT(4), + DDR0_16BIT_EN = BIT(3), + MSCH0_MAINDDR3_DDR3 = BIT(2), + MSCH0_MAINPARTIALPOP = BIT(1), + UPCTL_C_ACTIVE = BIT(0), +}; + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h index 93c4e7d4e1..6b6651acab 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -1,4 +1,6 @@ -/* (C) Copyright 2016 Rockchip Electronics Co., Ltd +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * * SPDX-License-Identifier: GPL-2.0+ */ @@ -74,8 +76,11 @@ struct rk3368_grf { u32 soc_con15; u32 soc_con16; u32 soc_con17; + u32 reserved5[0x6e]; + u32 ddrc0_con0; }; check_member(rk3368_grf, soc_con17, 0x444); +check_member(rk3368_grf, ddrc0_con0, 0x600); struct rk3368_pmu_grf { u32 gpio0a_iomux; @@ -92,323 +97,11 @@ struct rk3368_pmu_grf { u32 gpio0d_drv; u32 gpio0l_sr; u32 gpio0h_sr; - u32 reserved[(0x200 - 0x34) / 4 - 1]; + u32 reserved[0x72]; u32 os_reg[4]; }; -check_member(rk3368_pmu_grf, os_reg[3], 0x20c); - -/*GRF_GPIO0C_IOMUX*/ -enum { - GPIO0C7_SHIFT = 14, - GPIO0C7_MASK = 3 << GPIO0C7_SHIFT, - GPIO0C7_GPIO = 0, - GPIO0C7_LCDC_D19, - GPIO0C7_TRACE_D9, - GPIO0C7_UART1_RTSN, - - GPIO0C6_SHIFT = 12, - GPIO0C6_MASK = 3 << GPIO0C6_SHIFT, - GPIO0C6_GPIO = 0, - GPIO0C6_LCDC_D18, - GPIO0C6_TRACE_D8, - GPIO0C6_UART1_CTSN, - - GPIO0C5_SHIFT = 10, - GPIO0C5_MASK = 3 << GPIO0C5_SHIFT, - GPIO0C5_GPIO = 0, - GPIO0C5_LCDC_D17, - GPIO0C5_TRACE_D7, - GPIO0C5_UART1_SOUT, - - GPIO0C4_SHIFT = 8, - GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, - GPIO0C4_GPIO = 0, - GPIO0C4_LCDC_D16, - GPIO0C4_TRACE_D6, - GPIO0C4_UART1_SIN, - - GPIO0C3_SHIFT = 6, - GPIO0C3_MASK = 3 << GPIO0C3_SHIFT, - GPIO0C3_GPIO = 0, - GPIO0C3_LCDC_D15, - GPIO0C3_TRACE_D5, - GPIO0C3_MCU_JTAG_TDO, - - GPIO0C2_SHIFT = 4, - GPIO0C2_MASK = 3 << GPIO0C2_SHIFT, - GPIO0C2_GPIO = 0, - GPIO0C2_LCDC_D14, - GPIO0C2_TRACE_D4, - GPIO0C2_MCU_JTAG_TDI, - - GPIO0C1_SHIFT = 2, - GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, - GPIO0C1_GPIO = 0, - GPIO0C1_LCDC_D13, - GPIO0C1_TRACE_D3, - GPIO0C1_MCU_JTAG_TRTSN, - - GPIO0C0_SHIFT = 0, - GPIO0C0_MASK = 3 << GPIO0C0_SHIFT, - GPIO0C0_GPIO = 0, - GPIO0C0_LCDC_D12, - GPIO0C0_TRACE_D2, - GPIO0C0_MCU_JTAG_TDO, -}; - -/*GRF_GPIO0D_IOMUX*/ -enum { - GPIO0D7_SHIFT = 14, - GPIO0D7_MASK = 3 << GPIO0D7_SHIFT, - GPIO0D7_GPIO = 0, - GPIO0D7_LCDC_DCLK, - GPIO0D7_TRACE_CTL, - GPIO0D7_PMU_DEBUG5, - - GPIO0D6_SHIFT = 12, - GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, - GPIO0D6_GPIO = 0, - GPIO0D6_LCDC_DEN, - GPIO0D6_TRACE_CLK, - GPIO0D6_PMU_DEBUG4, - - GPIO0D5_SHIFT = 10, - GPIO0D5_MASK = 3 << GPIO0D5_SHIFT, - GPIO0D5_GPIO = 0, - GPIO0D5_LCDC_VSYNC, - GPIO0D5_TRACE_D15, - GPIO0D5_PMU_DEBUG3, - - GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, - GPIO0D4_GPIO = 0, - GPIO0D4_LCDC_HSYNC, - GPIO0D4_TRACE_D14, - GPIO0D4_PMU_DEBUG2, - - GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, - GPIO0D3_GPIO = 0, - GPIO0D3_LCDC_D23, - GPIO0D3_TRACE_D13, - GPIO0D3_UART4_SIN, - - GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, - GPIO0D2_GPIO = 0, - GPIO0D2_LCDC_D22, - GPIO0D2_TRACE_D12, - GPIO0D2_UART4_SOUT, - - GPIO0D1_SHIFT = 2, - GPIO0D1_MASK = 3 << GPIO0D1_SHIFT, - GPIO0D1_GPIO = 0, - GPIO0D1_LCDC_D21, - GPIO0D1_TRACE_D11, - GPIO0D1_UART4_RTSN, - - GPIO0D0_SHIFT = 0, - GPIO0D0_MASK = 3 << GPIO0D0_SHIFT, - GPIO0D0_GPIO = 0, - GPIO0D0_LCDC_D20, - GPIO0D0_TRACE_D10, - GPIO0D0_UART4_CTSN, -}; - -/*GRF_GPIO2A_IOMUX*/ -enum { - GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_SDMMC0_D2, - GPIO2A7_JTAG_TCK, - - GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = 3 << GPIO2A6_SHIFT, - GPIO2A6_GPIO = 0, - GPIO2A6_SDMMC0_D1, - GPIO2A6_UART2_SIN, - - GPIO2A5_SHIFT = 10, - GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, - GPIO2A5_GPIO = 0, - GPIO2A5_SDMMC0_D0, - GPIO2A5_UART2_SOUT, - - GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, - GPIO2A4_GPIO = 0, - GPIO2A4_FLASH_DQS, - GPIO2A4_EMMC_CLKO, - - GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, - GPIO2A3_GPIO = 0, - GPIO2A3_FLASH_CSN3, - GPIO2A3_EMMC_RSTNO, - - GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, - GPIO2A2_GPIO = 0, - GPIO2A2_FLASH_CSN2, - - GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, - GPIO2A1_GPIO = 0, - GPIO2A1_FLASH_CSN1, - - GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, - GPIO2A0_GPIO = 0, - GPIO2A0_FLASH_CSN0, -}; - -/*GRF_GPIO2D_IOMUX*/ -enum { - GPIO2D7_SHIFT = 14, - GPIO2D7_MASK = 3 << GPIO2D7_SHIFT, - GPIO2D7_GPIO = 0, - GPIO2D7_SDIO0_D3, - - GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = 3 << GPIO2D6_SHIFT, - GPIO2D6_GPIO = 0, - GPIO2D6_SDIO0_D2, - - GPIO2D5_SHIFT = 10, - GPIO2D5_MASK = 3 << GPIO2D5_SHIFT, - GPIO2D5_GPIO = 0, - GPIO2D5_SDIO0_D1, - - GPIO2D4_SHIFT = 8, - GPIO2D4_MASK = 3 << GPIO2D4_SHIFT, - GPIO2D4_GPIO = 0, - GPIO2D4_SDIO0_D0, - - GPIO2D3_SHIFT = 6, - GPIO2D3_MASK = 3 << GPIO2D3_SHIFT, - GPIO2D3_GPIO = 0, - GPIO2D3_UART0_RTS0, - - GPIO2D2_SHIFT = 4, - GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, - GPIO2D2_GPIO = 0, - GPIO2D2_UART0_CTS0, - - GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, - GPIO2D1_GPIO = 0, - GPIO2D1_UART0_SOUT, - - GPIO2D0_SHIFT = 0, - GPIO2D0_MASK = 3 << GPIO2D0_SHIFT, - GPIO2D0_GPIO = 0, - GPIO2D0_UART0_SIN, -}; - -/*GRF_GPIO3C_IOMUX*/ -enum { - GPIO3C7_SHIFT = 14, - GPIO3C7_MASK = 3 << GPIO3C7_SHIFT, - GPIO3C7_GPIO = 0, - GPIO3C7_EDPHDMI_CECINOUT, - GPIO3C7_ISP_FLASHTRIGIN, - - GPIO3C6_SHIFT = 12, - GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, - GPIO3C6_GPIO = 0, - GPIO3C6_MAC_CLK, - GPIO3C6_ISP_SHUTTERTRIG, - - GPIO3C5_SHIFT = 10, - GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, - GPIO3C5_GPIO = 0, - GPIO3C5_MAC_RXER, - GPIO3C5_ISP_PRELIGHTTRIG, - - GPIO3C4_SHIFT = 8, - GPIO3C4_MASK = 3 << GPIO3C4_SHIFT, - GPIO3C4_GPIO = 0, - GPIO3C4_MAC_RXDV, - GPIO3C4_ISP_FLASHTRIGOUT, - - GPIO3C3_SHIFT = 6, - GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, - GPIO3C3_GPIO = 0, - GPIO3C3_MAC_RXDV, - GPIO3C3_EMMC_RSTNO, - - GPIO3C2_SHIFT = 4, - GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, - GPIO3C2_MAC_MDC = 0, - GPIO3C2_ISP_SHUTTEREN, - - GPIO3C1_SHIFT = 2, - GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, - GPIO3C1_GPIO = 0, - GPIO3C1_MAC_RXD2, - GPIO3C1_UART3_RTSN, - - GPIO3C0_SHIFT = 0, - GPIO3C0_MASK = 3 << GPIO3C0_SHIFT, - GPIO3C0_GPIO = 0, - GPIO3C0_MAC_RXD1, - GPIO3C0_UART3_CTSN, - GPIO3C0_GPS_RFCLK, -}; - -/*GRF_GPIO3D_IOMUX*/ -enum { - GPIO3D7_SHIFT = 14, - GPIO3D7_MASK = 3 << GPIO3D7_SHIFT, - GPIO3D7_GPIO = 0, - GPIO3D7_SC_VCC18V, - GPIO3D7_I2C2_SDA, - GPIO3D7_GPUJTAG_TCK, - - GPIO3D6_SHIFT = 12, - GPIO3D6_MASK = 3 << GPIO3D6_SHIFT, - GPIO3D6_GPIO = 0, - GPIO3D6_IR_TX, - GPIO3D6_UART3_SOUT, - GPIO3D6_PWM3, - - GPIO3D5_SHIFT = 10, - GPIO3D5_MASK = 3 << GPIO3D5_SHIFT, - GPIO3D5_GPIO = 0, - GPIO3D5_IR_RX, - GPIO3D5_UART3_SIN, - - GPIO3D4_SHIFT = 8, - GPIO3D4_MASK = 3 << GPIO3D4_SHIFT, - GPIO3D4_GPIO = 0, - GPIO3D4_MAC_TXCLKOUT, - GPIO3D4_SPI1_CSN1, - - GPIO3D3_SHIFT = 6, - GPIO3D3_MASK = 3 << GPIO3D3_SHIFT, - GPIO3D3_GPIO = 0, - GPIO3D3_HDMII2C_SCL, - GPIO3D3_I2C5_SCL, - - GPIO3D2_SHIFT = 4, - GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, - GPIO3D2_GPIO = 0, - GPIO3D2_HDMII2C_SDA, - GPIO3D2_I2C5_SDA, - - GPIO3D1_SHIFT = 2, - GPIO3D1_MASK = 3 << GPIO3D1_SHIFT, - GPIO3D1_GPIO = 0, - GPIO3D1_MAC_RXCLKIN, - GPIO3D1_I2C4_SCL, - - GPIO3D0_SHIFT = 0, - GPIO3D0_MASK = 3 << GPIO3D0_SHIFT, - GPIO3D0_GPIO = 0, - GPIO3D0_MAC_MDIO, - GPIO3D0_I2C4_SDA, -}; +check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); +check_member(rk3368_pmu_grf, os_reg[0], 0x200); /*GRF_SOC_CON11/12/13*/ enum { @@ -439,4 +132,5 @@ enum { MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0, MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0), }; + #endif diff --git a/arch/arm/include/asm/arch-stm32f1/gpio.h b/arch/arm/include/asm/arch-stm32f1/gpio.h deleted file mode 100644 index 8e8712fecc..0000000000 --- a/arch/arm/include/asm/arch-stm32f1/gpio.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2011 - * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _STM32_GPIO_H_ -#define _STM32_GPIO_H_ - -enum stm32_gpio_port { - STM32_GPIO_PORT_A = 0, - STM32_GPIO_PORT_B, - STM32_GPIO_PORT_C, - STM32_GPIO_PORT_D, - STM32_GPIO_PORT_E, - STM32_GPIO_PORT_F, - STM32_GPIO_PORT_G, -}; - -enum stm32_gpio_pin { - STM32_GPIO_PIN_0 = 0, - STM32_GPIO_PIN_1, - STM32_GPIO_PIN_2, - STM32_GPIO_PIN_3, - STM32_GPIO_PIN_4, - STM32_GPIO_PIN_5, - STM32_GPIO_PIN_6, - STM32_GPIO_PIN_7, - STM32_GPIO_PIN_8, - STM32_GPIO_PIN_9, - STM32_GPIO_PIN_10, - STM32_GPIO_PIN_11, - STM32_GPIO_PIN_12, - STM32_GPIO_PIN_13, - STM32_GPIO_PIN_14, - STM32_GPIO_PIN_15 -}; - -enum stm32_gpio_icnf { - STM32_GPIO_ICNF_AN = 0, - STM32_GPIO_ICNF_IN_FLT, - STM32_GPIO_ICNF_IN_PUD, - STM32_GPIO_ICNF_RSVD -}; - -enum stm32_gpio_ocnf { - STM32_GPIO_OCNF_GP_PP = 0, - STM32_GPIO_OCNF_GP_OD, - STM32_GPIO_OCNF_AF_PP, - STM32_GPIO_OCNF_AF_OD -}; - -enum stm32_gpio_pupd { - STM32_GPIO_PUPD_DOWN = 0, - STM32_GPIO_PUPD_UP, -}; - -enum stm32_gpio_mode { - STM32_GPIO_MODE_IN = 0, - STM32_GPIO_MODE_OUT_10M, - STM32_GPIO_MODE_OUT_2M, - STM32_GPIO_MODE_OUT_50M -}; - -enum stm32_gpio_af { - STM32_GPIO_AF0 = 0, - STM32_GPIO_AF1, - STM32_GPIO_AF2, - STM32_GPIO_AF3, - STM32_GPIO_AF4, - STM32_GPIO_AF5, - STM32_GPIO_AF6, - STM32_GPIO_AF7, - STM32_GPIO_AF8, - STM32_GPIO_AF9, - STM32_GPIO_AF10, - STM32_GPIO_AF11, - STM32_GPIO_AF12, - STM32_GPIO_AF13, - STM32_GPIO_AF14, - STM32_GPIO_AF15 -}; - -struct stm32_gpio_dsc { - enum stm32_gpio_port port; - enum stm32_gpio_pin pin; -}; - -struct stm32_gpio_ctl { - enum stm32_gpio_icnf icnf; - enum stm32_gpio_ocnf ocnf; - enum stm32_gpio_mode mode; - enum stm32_gpio_pupd pupd; - enum stm32_gpio_af af; -}; - -static inline unsigned stm32_gpio_to_port(unsigned gpio) -{ - return gpio / 16; -} - -static inline unsigned stm32_gpio_to_pin(unsigned gpio) -{ - return gpio % 16; -} - -int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc, - const struct stm32_gpio_ctl *gpio_ctl); -int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state); - -#endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f1/stm32.h b/arch/arm/include/asm/arch-stm32f1/stm32.h deleted file mode 100644 index 1af73c5428..0000000000 --- a/arch/arm/include/asm/arch-stm32f1/stm32.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2011 - * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MACH_STM32_H_ -#define _MACH_STM32_H_ - -/* - * Peripheral memory map - */ -#define STM32_PERIPH_BASE 0x40000000 -#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) -#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) -#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00018000) - -#define STM32_BUS_MASK 0xFFFF0000 - -#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800) -#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00) -#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000) -#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400) -#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800) -#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00) -#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000) - -/* - * Register maps - */ -struct stm32_des_regs { - u16 flash_size; - u16 pad1; - u32 pad2; - u32 uid0; - u32 uid1; - u32 uid2; -}; - -struct stm32_rcc_regs { - u32 cr; /* RCC clock control */ - u32 cfgr; /* RCC clock configuration */ - u32 cir; /* RCC clock interrupt */ - u32 apb2rstr; /* RCC APB2 peripheral reset */ - u32 apb1rstr; /* RCC APB1 peripheral reset */ - u32 ahbenr; /* RCC AHB peripheral clock enable */ - u32 apb2enr; /* RCC APB2 peripheral clock enable */ - u32 apb1enr; /* RCC APB1 peripheral clock enable */ - u32 bdcr; /* RCC Backup domain control */ - u32 csr; /* RCC clock control & status */ -}; - -struct stm32_pwr_regs { - u32 cr; - u32 csr; -}; - -struct stm32_flash_regs { - u32 acr; - u32 keyr; - u32 optkeyr; - u32 sr; - u32 cr; - u32 ar; - u32 rsvd1; /* Reserved */ - u32 obr; - u32 wrpr; - u32 rsvd2[8]; /* Reserved */ - u32 keyr2; - u32 rsvd3; - u32 sr2; - u32 cr2; - u32 ar2; -}; - -/* Per bank register set for XL devices */ -struct stm32_flash_bank_regs { - u32 keyr; - u32 rsvd; /* Reserved */ - u32 sr; - u32 cr; - u32 ar; -}; - -/* - * Registers access macros - */ -#define STM32_DES_BASE (0x1ffff7e0) -#define STM32_DES ((struct stm32_des_regs *)STM32_DES_BASE) - -#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x9000) -#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) - -#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000) -#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE) - -#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0xa000) -#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE) - -#define STM32_FLASH_SR_BSY (1 << 0) - -#define STM32_FLASH_CR_PG (1 << 0) -#define STM32_FLASH_CR_PER (1 << 1) -#define STM32_FLASH_CR_STRT (1 << 6) -#define STM32_FLASH_CR_LOCK (1 << 7) - -enum clock { - CLOCK_CORE, - CLOCK_AHB, - CLOCK_APB1, - CLOCK_APB2 -}; - -int configure_clocks(void); -unsigned long clock_get(enum clock clck); - -#endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 0e674704ab..df45511699 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -30,6 +30,7 @@ enum { BOOT_DEVICE_BOARD, BOOT_DEVICE_DFU, BOOT_DEVICE_XIP, + BOOT_DEVICE_BOOTROM, BOOT_DEVICE_NONE }; #endif diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 704849bd0c..5c62d9c144 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -216,7 +216,7 @@ static void do_nonsec_virt_switch(void) /* Subcommand: PREP */ static void boot_prep_linux(bootm_headers_t *images) { - char *commandline = getenv("bootargs"); + char *commandline = env_get("bootargs"); if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { #ifdef CONFIG_OF_LIBFDT @@ -273,7 +273,7 @@ __weak bool armv7_boot_nonsec_default(void) #ifdef CONFIG_ARMV7_NONSEC bool armv7_boot_nonsec(void) { - char *s = getenv("bootm_boot_mode"); + char *s = env_get("bootm_boot_mode"); bool nonsec = armv7_boot_nonsec_default(); if (s && !strcmp(s, "sec")) @@ -361,7 +361,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) ulong addr = (ulong)kernel_entry | 1; kernel_entry = (void *)addr; #endif - s = getenv("machid"); + s = env_get("machid"); if (s) { if (strict_strtoul(s, 16, &machid) < 0) { debug("strict_strtoul failed!\n"); diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 57e728f9f2..62fad452b2 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -69,7 +69,9 @@ ENTRY(_main) /* * Set up initial C runtime environment and call board_init_f(0). */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) + ldr x0, =(CONFIG_TPL_STACK) +#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK) #else ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index 415ac89de9..bcd16ee591 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -200,7 +200,7 @@ static int do_smhload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Optionally save returned end to the environment */ if (argc == 4) { sprintf(end_str, "0x%08lx", end_addr); - setenv(argv[3], end_str); + env_set(argv[3], end_str); } } else { return CMD_RET_USAGE; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 23ddc6296d..20f7eeaf09 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -199,4 +199,8 @@ source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" +config SPL_LDSCRIPT + default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS + default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if CPU_V7 + endif diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 4757f2496d..35e4e9bcea 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -53,4 +53,8 @@ source "board/davinci/ea20/Kconfig" source "board/omicron/calimain/Kconfig" source "board/lego/ev3/Kconfig" +config SPL_LDSCRIPT + default "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" if TARGET_IPAM390 + default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" + endif diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index ec331ba6bb..461ff778c2 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -90,7 +90,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) uint8_t env_enetaddr[6]; int ret; - ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); + ret = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr); if (!ret) { /* * There is no MAC address in the environment, so we @@ -99,7 +99,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) debug("### Setting environment from EEPROM MAC address = " "\"%pM\"\n", env_enetaddr); - ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr); + ret = !eth_env_set_enetaddr("ethaddr", rom_enetaddr); } if (!ret) printf("Failed to set mac address from EEPROM: %d\n", ret); diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index d1aa68db20..2fb84f9453 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -8,7 +8,6 @@ config ARCH_EXYNOS4 bool "Exynos4 SoC family" select CPU_V7 select BOARD_EARLY_INIT_F - imply ENV_IS_IN_MMC help Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There are multiple SoCs in this family including Exynos4210, Exynos4412, @@ -161,4 +160,7 @@ source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" source "board/samsung/espresso7420/Kconfig" +config SPL_LDSCRIPT + default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4 + endif diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index bb2ce33132..a1aa36bc22 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -1,24 +1,32 @@ if ARCH_MX6 +config MX6_SMP + select ARM_ERRATA_751472 + select ARM_ERRATA_761320 + select ARM_ERRATA_794072 + select ARM_ERRATA_845369 + bool + config MX6 + select ARM_ERRATA_743622 if !MX6UL bool default y - select ARM_ERRATA_743622 if !MX6UL - select ARM_ERRATA_751472 if !MX6UL - select ARM_ERRATA_761320 if !MX6UL - select ARM_ERRATA_794072 if !MX6UL imply CMD_FUSE config MX6D + select MX6_SMP bool config MX6DL + select MX6_SMP bool config MX6Q + select MX6_SMP bool config MX6QDL + select MX6_SMP bool config MX6S @@ -30,7 +38,6 @@ config MX6SL config MX6SX select ROM_UNIFIED_SECTIONS bool - imply ENV_IS_IN_MMC config MX6SLL select ROM_UNIFIED_SECTIONS @@ -145,6 +152,7 @@ config TARGET_GW_VENTANA bool "gw_ventana" select SUPPORT_SPL imply CMD_SATA + imply CMD_SPL config TARGET_KOSAGI_NOVENA bool "Kosagi Novena" @@ -331,6 +339,11 @@ config TARGET_PCM058 select BOARD_LATE_INIT select SUPPORT_SPL +config TARGET_PFLA02 + bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad" + select BOARD_LATE_INIT + select SUPPORT_SPL + config TARGET_SECOMX6 bool "secomx6 boards" @@ -428,6 +441,7 @@ source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ullevk/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" +source "board/phytec/pfla02/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/samtec/vining_2000/Kconfig" diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 1f2739e864..0e019c4262 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -19,7 +19,7 @@ enum pll_clocks { PLL_USBOTG, /* OTG USB PLL */ PLL_ENET, /* ENET PLL */ PLL_AUDIO, /* AUDIO PLL */ - PLL_VIDEO, /* AUDIO PLL */ + PLL_VIDEO, /* VIDEO PLL */ }; struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index 22b244079b..f8d7e8ee68 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -132,7 +132,7 @@ int board_late_init(void) /* In bootstrap don't use the env vars */ if (((reg & 0x3000000) >> 24) == 0x1) { set_default_env(NULL); - setenv("preboot", ""); + env_set("preboot", ""); } return opos6ul_board_late_init(); diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index af316735ee..9ede1f5435 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -114,6 +114,12 @@ u32 get_cpu_rev(void) #define OCOTP_CFG3_SPEED_528MHZ 1 #define OCOTP_CFG3_SPEED_696MHZ 2 +/* + * For i.MX6ULL + */ +#define OCOTP_CFG3_SPEED_792MHZ 2 +#define OCOTP_CFG3_SPEED_900MHZ 3 + u32 get_cpu_speed_grade_hz(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -126,11 +132,22 @@ u32 get_cpu_speed_grade_hz(void) val >>= OCOTP_CFG3_SPEED_SHIFT; val &= 0x3; - if (is_mx6ul() || is_mx6ull()) { + if (is_mx6ul()) { if (val == OCOTP_CFG3_SPEED_528MHZ) return 528000000; else if (val == OCOTP_CFG3_SPEED_696MHZ) - return 69600000; + return 696000000; + else + return 0; + } + + if (is_mx6ull()) { + if (val == OCOTP_CFG3_SPEED_528MHZ) + return 528000000; + else if (val == OCOTP_CFG3_SPEED_792MHZ) + return 792000000; + else if (val == OCOTP_CFG3_SPEED_900MHZ) + return 900000000; else return 0; } @@ -234,6 +251,10 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) u32 val, step, old, reg = readl(&anatop->reg_core); u8 shift; + /* No LDO_SOC/PU/ARM */ + if (is_mx6sll()) + return 0; + if (mv < 725) val = 0x00; /* Power gated off */ else if (mv > 1450) @@ -293,7 +314,7 @@ static void clear_mmdc_ch_mask(void) reg = readl(&mxc_ccm->ccdr); /* Clear MMDC channel mask */ - if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) + if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll()) reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); else reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); @@ -344,20 +365,10 @@ static void init_bandgap(void) } } -#ifdef CONFIG_MX6SL -static void set_preclk_from_osc(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - u32 reg; - - reg = readl(&mxc_ccm->cscmr1); - reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; - writel(reg, &mxc_ccm->cscmr1); -} -#endif - int arch_cpu_init(void) { + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + init_aips(); /* Need to clear MMDC_CHx_MASK to make warm reset work. */ @@ -421,12 +432,14 @@ int arch_cpu_init(void) } /* Set perclk to source from OSC 24MHz */ -#if defined(CONFIG_MX6SL) - set_preclk_from_osc(); -#endif + if (is_mx6sl()) + setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK); imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ + if (is_mx6sx()) + setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL); + init_src(); return 0; @@ -495,6 +508,10 @@ uint mmc_get_env_part(struct mmc *mmc) int board_postclk_init(void) { + /* NO LDO SOC on i.MX6SLL */ + if (is_mx6sll()) + return 0; + set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ return 0; @@ -576,7 +593,7 @@ void s_init(void) u32 mask528; u32 reg, periph1, periph2; - if (is_mx6sx() || is_mx6ul() || is_mx6ull()) + if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll()) return; /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 7053697f9b..aea85265ef 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -13,7 +13,6 @@ config MX7D select ROM_UNIFIED_SECTIONS imply CMD_FUSE bool - imply ENV_IS_IN_MMC choice prompt "MX7 board select" diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 4cf977e20a..87bf105f38 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -31,7 +31,7 @@ U_BOOT_DEVICE(imx7_thermal) = { }; #endif -#ifdef CONFIG_IMX_RDC +#if CONFIG_IS_ENABLED(IMX_RDC) /* * In current design, if any peripheral was assigned to both A7 and M4, * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter @@ -245,8 +245,9 @@ int arch_cpu_init(void) mxs_dma_init(); #endif - if (IS_ENABLED(CONFIG_IMX_RDC)) - isolate_resource(); +#if CONFIG_IS_ENABLED(IMX_RDC) + isolate_resource(); +#endif return 0; } @@ -256,9 +257,9 @@ int arch_misc_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG if (is_mx7d()) - setenv("soc", "imx7d"); + env_set("soc", "imx7d"); else - setenv("soc", "imx7s"); + env_set("soc", "imx7s"); #endif return 0; diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c index 55242f0eaa..c670c5dfc9 100644 --- a/arch/arm/mach-imx/video.c +++ b/arch/arm/mach-imx/video.c @@ -10,7 +10,7 @@ int board_video_skip(void) { int i; int ret; - char const *panel = getenv("panel"); + char const *panel = env_get("panel"); if (!panel) { for (i = 0; i < display_count; i++) { diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index 5146e51f9c..d506ee5b39 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -11,13 +11,11 @@ config ARCH_INTEGRATOR_AP config ARCH_INTEGRATOR_CP bool "Support Integrator/CP platform" select ARCH_CINTEGRATOR - imply ENV_IS_IN_FLASH endchoice config ARCH_CINTEGRATOR bool - imply ENV_IS_IN_FLASH choice prompt "Integrator core module select" diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 4cad6a2d81..b2f5414a5c 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -331,7 +331,7 @@ void ddr3_check_ecc_int(u32 base) int ecc_test = 0; u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); - env = getenv("ecc_test"); + env = env_get("ecc_test"); if (env) ecc_test = simple_strtol(env, NULL, 0); diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c index beb8a767c4..fcabfbd5c3 100644 --- a/arch/arm/mach-keystone/keystone.c +++ b/arch/arm/mach-keystone/keystone.c @@ -46,7 +46,7 @@ int misc_init_r(void) char *env; long ks2_debug = 0; - env = getenv("ks2_debug"); + env = env_get("ks2_debug"); if (env) ks2_debug = simple_strtol(env, NULL, 0); diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 4c9d3fde47..db2ff0311c 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -129,7 +129,7 @@ int kw_config_adr_windows(void) static void kw_sysrst_action(void) { int ret; - char *s = getenv("sysrstcmd"); + char *s = env_get("sysrstcmd"); if (!s) { debug("Error.. %s failed, check sysrstcmd\n", @@ -153,7 +153,7 @@ static void kw_sysrst_check(void) /* * no action if sysrstdelay environment variable is not defined */ - s = getenv("sysrstdelay"); + s = env_get("sysrstdelay"); if (s == NULL) return; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 1b12b33060..01d700bf2e 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -32,7 +32,6 @@ config ARMADA_38X config ARMADA_XP bool select ARMADA_32BIT - imply ENV_IS_IN_SPI_FLASH # ARMv8 SoCs... config ARMADA_3700 diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index b0e193b78c..525576a4fc 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -354,16 +354,16 @@ int serdes_phy_config(void) } info = board_serdes_cfg_get(PEX_MODE_GET(satr11)); - DEBUG_INIT_FULL_S("info->line0_7= 0x"); - DEBUG_INIT_FULL_D(info->line0_7, 8); - DEBUG_INIT_FULL_S(" info->line8_15= 0x"); - DEBUG_INIT_FULL_D(info->line8_15, 8); - DEBUG_INIT_FULL_S("\n"); if (info == NULL) { DEBUG_INIT_S("Hight speed PHY Error #1\n"); return MV_ERROR; } + DEBUG_INIT_FULL_S("info->line0_7= 0x"); + DEBUG_INIT_FULL_D(info->line0_7, 8); + DEBUG_INIT_FULL_S(" info->line8_15= 0x"); + DEBUG_INIT_FULL_D(info->line8_15, 8); + DEBUG_INIT_FULL_S("\n"); if (config_module & ETM_MODULE_DETECT) { /* step 0.9 ETM */ DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n"); diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 89c91d1b77..72832ad099 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -170,4 +170,7 @@ source "board/ti/am335x/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + endif diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index d8abba992a..7260d27877 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -81,6 +81,7 @@ config TARGET_AM335X_SHC select DM select DM_SERIAL select DM_GPIO + imply CMD_SPL config TARGET_AM335X_SL50 bool "Support am335x_sl50" diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 700e6c2f79..26245aa169 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -10,6 +10,7 @@ #include <common.h> #include <ahci.h> +#include <environment.h> #include <spl.h> #include <asm/omap_common.h> #include <asm/arch/omap.h> @@ -240,8 +241,8 @@ void arch_preboot_os(void) int fb_set_reboot_flag(void) { printf("Setting reboot to fastboot flag ...\n"); - setenv("dofastboot", "1"); - saveenv(); + env_set("dofastboot", "1"); + env_save(); return 0; } #endif diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index d540cf08d2..8197e7b032 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -76,7 +76,7 @@ static void do_emif4_init(void) regval |= (1<<10); writel(regval, &emif4_base->sdram_iodft_tlgc); /*Wait till that bit clears*/ - while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1); + while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) != 0x0); /*Re-verify the DDR PHY status*/ while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0); diff --git a/arch/arm/mach-omap2/omap5/abb.c b/arch/arm/mach-omap2/omap5/abb.c index 3bf88979e5..1882c49e7d 100644 --- a/arch/arm/mach-omap2/omap5/abb.c +++ b/arch/arm/mach-omap2/omap5/abb.c @@ -28,8 +28,8 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) { u32 vset; - u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK; - u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK; + u32 fuse_enable_mask = OMAP5_PROD_ABB_FUSE_ENABLE_MASK; + u32 fuse_vset_mask = OMAP5_PROD_ABB_FUSE_VSET_MASK; if (!is_omap54xx()) { /* DRA7 */ diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index a8a6b8a869..4ad6b530d2 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -329,6 +329,15 @@ struct vcores_data omap5430_volts_es2 = { .mm.addr = SMPS_REG_ADDR_45_IVA, .mm.pmic = &palmas, .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, + + .mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN, + .mpu.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, + + .core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN, + .core.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, + + .mm.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MM_OPNO_VMIN, + .mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, }; /* diff --git a/arch/arm/mach-omap2/sysinfo-common.c b/arch/arm/mach-omap2/sysinfo-common.c index 1dc7051ab3..4dab12a8d7 100644 --- a/arch/arm/mach-omap2/sysinfo-common.c +++ b/arch/arm/mach-omap2/sysinfo-common.c @@ -16,6 +16,15 @@ */ u32 get_device_type(void) { +#if defined(CONFIG_OMAP34XX) + /* + * On OMAP3 systems we call this early enough that we must just + * use the direct offset for safety. + */ + return (readl(OMAP34XX_CTRL_BASE + 0x2f0) & DEVICE_TYPE_MASK) >> + DEVICE_TYPE_SHIFT; +#else return (readl((*ctrl)->control_status) & DEVICE_TYPE_MASK) >> DEVICE_TYPE_SHIFT; +#endif } diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 1946641eb9..0b0bf1837c 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -40,7 +40,7 @@ static void omap_set_fastboot_cpu(void) printf("Warning: fastboot.cpu: unknown CPU rev: %u\n", cpu_rev); } - setenv("fastboot.cpu", cpu); + env_set("fastboot.cpu", cpu); } static void omap_set_fastboot_secure(void) @@ -63,18 +63,18 @@ static void omap_set_fastboot_secure(void) printf("Warning: fastboot.secure: unknown CPU sec: %u\n", dev); } - setenv("fastboot.secure", secure); + env_set("fastboot.secure", secure); } static void omap_set_fastboot_board_rev(void) { const char *board_rev; - board_rev = getenv("board_rev"); + board_rev = env_get("board_rev"); if (board_rev == NULL) printf("Warning: fastboot.board_rev: unknown board revision\n"); - setenv("fastboot.board_rev", board_rev); + env_set("fastboot.board_rev", board_rev); } #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV @@ -118,7 +118,7 @@ static void omap_set_fastboot_userdata_size(void) sprintf(buf, "%u", sz_kb); } - setenv("fastboot.userdata_size", buf); + env_set("fastboot.userdata_size", buf); } #else static inline void omap_set_fastboot_userdata_size(void) @@ -169,11 +169,11 @@ void omap_die_id_serial(void) omap_die_id((unsigned int *)&die_id); - if (!getenv("serial#")) { + if (!env_get("serial#")) { snprintf(serial_string, sizeof(serial_string), "%08x%08x", die_id[0], die_id[3]); - setenv("serial#", serial_string); + env_set("serial#", serial_string); } } @@ -182,7 +182,7 @@ void omap_die_id_get_board_serial(struct tag_serialnr *serialnr) char *serial_string; unsigned long long serial; - serial_string = getenv("serial#"); + serial_string = env_get("serial#"); if (serial_string) { serial = simple_strtoull(serial_string, NULL, 16); @@ -202,7 +202,7 @@ void omap_die_id_usbethaddr(void) omap_die_id((unsigned int *)&die_id); - if (!getenv("usbethaddr")) { + if (!env_get("usbethaddr")) { /* * Create a fake MAC address from the processor ID code. * First byte is 0x02 to signify locally administered. @@ -214,7 +214,7 @@ void omap_die_id_usbethaddr(void) mac[4] = die_id[0] & 0xff; mac[5] = (die_id[0] >> 8) & 0xff; - eth_setenv_enetaddr("usbethaddr", mac); + eth_env_set_enetaddr("usbethaddr", mac); } } diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 7644b8dc85..2984a3edda 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -15,4 +15,7 @@ config SYS_SOC source "board/LaCie/edminiv2/Kconfig" +config SPL_LDSCRIPT + default "$(CPUDIR)/orion5x/u-boot-spl.lds" if ORION5X + endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c9246132e0..d9b25d5de4 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -67,14 +67,42 @@ config ROCKCHIP_RK3328 config ROCKCHIP_RK3368 bool "Support Rockchip RK3368" select ARM64 + select SUPPORT_SPL + select SUPPORT_TPL + select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL + select TPL_NEEDS_SEPARATE_STACK if TPL + imply SPL_SEPARATE_BSS + imply SPL_SERIAL_SUPPORT + imply TPL_SERIAL_SUPPORT + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT select SYS_NS16550 help - The Rockchip RK3328 is a ARM-based SoC with a octa-core Cortex-A53. - including NEON and GPU, 512KB L2 cache for big cluster and 256 KB - L2 cache for little cluser, PowerVR G6110 based graphics, one video - output processor supporting LVDS、HDMI、eDP, several DDR3 options - and video codec support. Peripherals include Gigabit Ethernet, - USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. + The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised + into a big and little cluster with 4 cores each) Cortex-A53 including + AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache + (for the little cluster), PowerVR G6110 based graphics, one video + output processor supporting LVDS/HDMI/eDP, several DDR3 options and + video codec support. + + On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, + I2S, UARTs, SPI, I2C and PWMs. + +if ROCKCHIP_RK3368 + +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds" + +config TPL_TEXT_BASE + default 0xff8c1000 + +config TPL_MAX_SIZE + default 28672 + +config TPL_STACK + default 0xff8cffff + +endif config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" @@ -101,10 +129,21 @@ config ROCKCHIP_RV1108 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. -config ROCKCHIP_SPL_BACK_TO_BROM +config SPL_ROCKCHIP_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 select ROCKCHIP_BROM_HELPER + depends on SPL + help + Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, + SPL will return to the boot rom, which will then load the U-Boot + binary to keep going on. + +config TPL_ROCKCHIP_BACK_TO_BROM + bool "TPL returns to bootrom" + default y if ROCKCHIP_RK3368 + select ROCKCHIP_BROM_HELPER + depends on TPL help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, SPL will return to the boot rom, which will then load the U-Boot @@ -122,7 +161,7 @@ config ROCKCHIP_BROM_HELPER bool config SPL_MMC_SUPPORT - default y if !ROCKCHIP_SPL_BACK_TO_BROM + default y if !SPL_ROCKCHIP_BACK_TO_BROM source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index cb8d3efe4b..79e9704a2c 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -4,39 +4,50 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o - -ifdef CONFIG_TPL_BUILD -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o -obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o -else ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o -obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o -else +# We don't want the bootrom-helper present in a full U-Boot build, as +# this may have entered from ATF with the stack-pointer pointing to +# inaccessible/protected memory (and the bootrom-helper assumes that +# the stack-pointer is valid before switching to the U-Boot stack). +obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o +obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o + +obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o + +obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o +obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o + +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o -ifdef CONFIG_RAM -obj-y += sdram_common.o -endif endif + +obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o + ifndef CONFIG_ARM64 obj-y += rk_timer.o endif -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ ifndef CONFIG_TPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ endif - obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/ obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ + +# Clear out SPL objects, in case this is a TPL build +obj-spl-$(CONFIG_TPL_BUILD) = + +# Now add SPL/TPL objects back into the main build +obj-$(CONFIG_SPL_BUILD) += $(obj-spl-y) +obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y) diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index 4ca9962310..8380e4e006 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -9,8 +9,8 @@ void back_to_bootrom(void) { -#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && !defined(CONFIG_TPL_BUILD) - puts("Returning to boot ROM..."); +#if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) + puts("Returning to boot ROM...\n"); #endif _back_to_bootrom_s(); } diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c index 26ea23b014..a3457f3914 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/rk3036-board.c @@ -34,11 +34,11 @@ static void setup_boot_mode(void) switch (boot_mode) { case BOOT_FASTBOOT: printf("enter fastboot!\n"); - setenv("preboot", "setenv preboot; fastboot usb0"); + env_set("preboot", "setenv preboot; fastboot usb0"); break; case BOOT_UMS: printf("enter UMS!\n"); - setenv("preboot", "setenv preboot; ums mmc 0"); + env_set("preboot", "setenv preboot; ums mmc 0"); break; } } diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index c3e174db9e..d3866bf029 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -167,8 +167,7 @@ void board_init_f(ulong dummy) } setup_arm_clock(); - -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif } @@ -229,7 +228,7 @@ void spl_board_init(void) } preloader_console_init(); -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) back_to_bootrom(); #endif return; diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 3e76100ad1..622e046dc0 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -39,7 +39,7 @@ int board_late_init(void) int board_init(void) { -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) struct udevice *pinctrl; int ret; diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig index d129fcda99..2bb35662d1 100644 --- a/arch/arm/mach-rockchip/rk3188/Kconfig +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -30,9 +30,6 @@ config TPL_LIBCOMMON_SUPPORT config TPL_LIBGENERIC_SUPPORT default y -config TPL_SERIAL_SUPPORT - default y - source "board/radxa/rock/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 15216c74b0..4ddb8ba065 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -41,6 +41,8 @@ static struct rk322x_grf * const grf = (void *)GRF_BASE; CON_IOMUX_UART2SEL_MASK, CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); } + +#define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) { struct udevice *dev; @@ -71,6 +73,8 @@ void board_init_f(ulong dummy) return; } + /* Disable the ddr secure region setting to make it non-secure */ + rk_clrreg(SGRF_DDR_CON0, 0x4000); #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c index b6543a5108..1e79c19309 100644 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -30,11 +30,11 @@ static void setup_boot_mode(void) switch (boot_mode) { case BOOT_FASTBOOT: printf("enter fastboot!\n"); - setenv("preboot", "setenv preboot; fastboot usb0"); + env_set("preboot", "setenv preboot; fastboot usb0"); break; case BOOT_UMS: printf("enter UMS!\n"); - setenv("preboot", "setenv preboot; ums mmc 0"); + env_set("preboot", "setenv preboot; ums mmc 0"); break; } } diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 5668fd28a0..6b7bf85d8d 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -249,7 +249,7 @@ void board_init_f(ulong dummy) debug("DRAM init failed: %d\n", ret); return; } -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif } @@ -316,7 +316,7 @@ void spl_board_init(void) } preloader_console_init(); -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) back_to_bootrom(); #endif return; diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 613967c307..74c6cc14a1 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -37,11 +37,11 @@ static void setup_boot_mode(void) switch (boot_mode) { case BOOT_FASTBOOT: printf("enter fastboot!\n"); - setenv("preboot", "setenv preboot; fastboot usb0"); + env_set("preboot", "setenv preboot; fastboot usb0"); break; case BOOT_UMS: printf("enter UMS!\n"); - setenv("preboot", "setenv preboot; if mmc dev 0;" + env_set("preboot", "setenv preboot; if mmc dev 0;" "then ums mmc 0; else ums mmc 1;fi"); break; } @@ -78,7 +78,7 @@ int board_late_init(void) return rk_board_late_init(); } -#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) static int veyron_init(void) { struct udevice *dev; @@ -115,7 +115,7 @@ static int veyron_init(void) int board_init(void) { -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) struct udevice *pinctrl; int ret; diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c new file mode 100644 index 0000000000..cabf344486 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <asm/arch/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ +} + +void board_init_f(ulong dummy) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + /* Set up our preloader console */ + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + error("%s: pinctrl init failed: %d\n", __func__, ret); + hang(); + } + + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0); + if (ret) { + error("%s: failed to set up console UART\n", __func__); + hang(); + } + + preloader_console_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c new file mode 100644 index 0000000000..b3e6ffa781 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/bootrom.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/hardware.h> +#include <asm/arch/timer.h> +#include <syscon.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The SPL (and also the full U-Boot stage on the RK3368) will run in + * secure mode (i.e. EL3) and an ATF will eventually be booted before + * starting up the operating system... so we can initialize the SGRF + * here and rely on the ATF installing the final (secure) policy + * later. + */ +static inline uintptr_t sgrf_soc_con_addr(unsigned no) +{ + const uintptr_t SGRF_BASE = + (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); + + return SGRF_BASE + sizeof(u32) * no; +} + +static inline uintptr_t sgrf_busdmac_addr(unsigned no) +{ + const uintptr_t SGRF_BASE = + (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); + const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100; + const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET; + + return SGRF_BUSDMAC_BASE + sizeof(u32) * no; +} + +static void sgrf_init(void) +{ + struct rk3368_cru * const cru = + (struct rk3368_cru * const)rockchip_get_cru(); + const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); + const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2); + const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); + + /* Set all configurable IP to 'non secure'-mode */ + rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); + rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); + rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); + + /* + * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c + * Original comment: "ddr space set no secure mode" + */ + rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); + rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); + rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); + + /* Set 'secure dma' to 'non secure'-mode */ + rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); + rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); + + dsb(); /* barrier */ + + rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); + rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); + + dsb(); /* barrier */ + udelay(10); + + rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); + rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); +} + +void board_debug_uart_init(void) +{ + /* + * N.B.: This is called before the device-model has been + * initialised. For this reason, we can not access + * the GRF address range using the syscon API. + */ + struct rk3368_grf * const grf = + (struct rk3368_grf * const)0xff770000; + + enum { + GPIO2D1_MASK = GENMASK(3, 2), + GPIO2D1_GPIO = 0, + GPIO2D1_UART0_SOUT = (1 << 2), + + GPIO2D0_MASK = GENMASK(1, 0), + GPIO2D0_GPIO = 0, + GPIO2D0_UART0_SIN = (1 << 0), + }; + +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) + /* Enable early UART0 on the RK3368 */ + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D0_MASK, GPIO2D0_UART0_SIN); + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D1_MASK, GPIO2D1_UART0_SOUT); +#endif +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#define EARLY_UART +#ifdef EARLY_UART + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("U-Boot TPL board init\n"); +#endif + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + /* Reset security, so we can use DMA in the MMC drivers */ + sgrf_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +void board_return_to_bootrom(void) +{ + back_to_bootrom(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 6d32068920..7c9b722b00 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -3,6 +3,26 @@ if ROCKCHIP_RK3368 choice prompt "RK3368 board" +config TARGET_LION_RK3368 + bool "Theobroma Systems RK3368-uQ7 (Lion) module" + help + The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm, + MXM-230 connector) system-on-module designed by Theobroma + Systems for industrial applications. + + It provides the following features: + - 8x Cortex-A53 (in 2 clusters of 4 cores each) + - (on-module) up to 4GB of DDR3 memory + - (on-module) SPI-NOR flash + - (on-module) eMMC + - Gigabit Ethernet (with an on-module KSZ9031 PHY) + - USB + - HDMI + - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group) + - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...) + - on-module STM32 providing CAN, RTC and fan-control + - (optional on-module) EAL4+-certified security module + config TARGET_SHEEP bool "Sheep board" help @@ -25,8 +45,12 @@ endchoice config SYS_SOC default "rockchip" +source "board/theobroma-systems/lion_rk3368/Kconfig" source "board/rockchip/sheep_rk3368/Kconfig" source "board/geekbuying/geekbox/Kconfig" source "board/rockchip/evb_px5/Kconfig" +config SPL_LDSCRIPT + default "arch/arm/cpu/armv8/u-boot-spl.lds" + endif diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile index 0390716410..46798c2e93 100644 --- a/arch/arm/mach-rockchip/rk3368/Makefile +++ b/arch/arm/mach-rockchip/rk3368/Makefile @@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.o diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted file mode 100644 index d0d090087b..0000000000 --- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR; -struct dram_info { - struct ram_info info; - struct rk3368_pmu_grf *pmugrf; -}; - -static int rk3368_dmc_probe(struct udevice *dev) -{ - struct dram_info *priv = dev_get_priv(dev); - - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - debug("%s: grf=%p\n", __func__, priv->pmugrf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = rockchip_sdram_size( - (phys_addr_t)&priv->pmugrf->os_reg[2]); - - return 0; -} - -static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info) -{ - struct dram_info *priv = dev_get_priv(dev); - - *info = priv->info; - - return 0; -} - -static struct ram_ops rk3368_dmc_ops = { - .get_info = rk3368_dmc_get_info, -}; - - -static const struct udevice_id rk3368_dmc_ids[] = { - { .compatible = "rockchip,rk3368-dmc" }, - { } -}; - -U_BOOT_DRIVER(dmc_rk3368) = { - .name = "rockchip_rk3368_dmc", - .id = UCLASS_RAM, - .of_match = rk3368_dmc_ids, - .ops = &rk3368_dmc_ops, - .probe = rk3368_dmc_probe, - .priv_auto_alloc_size = sizeof(struct dram_info), -}; diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c index 03e97eb629..99d51f0edc 100644 --- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -1,6 +1,8 @@ /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd * Author: Andy Yan <andy.yan@rock-chips.com> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,6 +16,10 @@ static const struct udevice_id rk3368_syscon_ids[] = { .data = ROCKCHIP_SYSCON_GRF }, { .compatible = "rockchip,rk3368-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { .compatible = "rockchip,rk3368-msch", + .data = ROCKCHIP_SYSCON_MSCH }, + { .compatible = "rockchip,rk3368-sgrf", + .data = ROCKCHIP_SYSCON_SGRF }, { } }; @@ -22,3 +28,41 @@ U_BOOT_DRIVER(syscon_rk3368) = { .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids, }; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rk3368_syscon_bind_of_platdata(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rk3368_grf) = { + .name = "rockchip_rk3368_grf", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids, + .bind = rk3368_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = { + .name = "rockchip_rk3368_pmugrf", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids + 1, + .bind = rk3368_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3368_msch) = { + .name = "rockchip_rk3368_msch", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids + 2, + .bind = rk3368_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3368_sgrf) = { + .name = "rockchip_rk3368_sgrf", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids + 3, + .bind = rk3368_syscon_bind_of_platdata, +}; +#endif diff --git a/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds b/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds new file mode 100644 index 0000000000..cc59844735 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE + +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE + +#include "../../cpu/armv8/u-boot-spl.lds" diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index e050affac0..a13b717bbd 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -8,9 +8,6 @@ #include <debug_uart.h> #include <dm.h> #include <fdtdec.h> -#include <led.h> -#include <malloc.h> -#include <mmc.h> #include <ram.h> #include <spl.h> #include <asm/gpio.h> @@ -21,111 +18,10 @@ #include <asm/arch/sdram.h> #include <asm/arch/timer.h> #include <dm/pinctrl.h> -#include <dm/root.h> -#include <dm/test.h> -#include <dm/util.h> #include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OF_CONTROL) -static int spl_node_to_boot_device(int node) -{ - struct udevice *parent; - - /* - * This should eventually move into the SPL code, once SPL becomes - * aware of the block-device layer. Until then (and to avoid unneeded - * delays in getting this feature out, it lives at the board-level). - */ - if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) { - struct udevice *dev; - struct blk_desc *desc = NULL; - - for (device_find_first_child(parent, &dev); - dev; - device_find_next_child(&dev)) { - if (device_get_uclass_id(dev) == UCLASS_BLK) { - desc = dev_get_uclass_platdata(dev); - break; - } - } - - if (!desc) - return -ENOENT; - - switch (desc->devnum) { - case 0: - return BOOT_DEVICE_MMC1; - case 1: - return BOOT_DEVICE_MMC2; - default: - return -ENOSYS; - } - } - - /* - * SPL doesn't differentiate SPI flashes, so we keep the detection - * brief and inaccurate... hopefully, the common SPL layer can be - * extended with awareness of the BLK layer (and matching OF_CONTROL) - * soon. - */ - if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) - return BOOT_DEVICE_SPI; - - return -1; -} - -void board_boot_order(u32 *spl_boot_list) -{ - const void *blob = gd->fdt_blob; - int chosen_node = fdt_path_offset(blob, "/chosen"); - int idx = 0; - int elem; - int boot_device; - int node; - const char *conf; - - if (chosen_node < 0) { - debug("%s: /chosen not found, using spl_boot_device()\n", - __func__); - spl_boot_list[0] = spl_boot_device(); - return; - } - - for (elem = 0; - (conf = fdt_stringlist_get(blob, chosen_node, - "u-boot,spl-boot-order", elem, NULL)); - elem++) { - /* First check if the list element is an alias */ - const char *alias = fdt_get_alias(blob, conf); - if (alias) - conf = alias; - - /* Try to resolve the config item (or alias) as a path */ - node = fdt_path_offset(blob, conf); - if (node < 0) { - debug("%s: could not find %s in FDT", __func__, conf); - continue; - } - - /* Try to map this back onto SPL boot devices */ - boot_device = spl_node_to_boot_device(node); - if (boot_device < 0) { - debug("%s: could not map node @%x to a boot-device\n", - __func__, node); - continue; - } - - spl_boot_list[idx++] = boot_device; - } - - /* If we had no matches, fall back to spl_boot_device */ - if (idx == 0) - spl_boot_list[0] = spl_boot_device(); -} -#endif - u32 spl_boot_device(void) { return BOOT_DEVICE_MMC1; @@ -263,7 +159,7 @@ void spl_board_init(void) } preloader_console_init(); -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) back_to_bootrom(); #endif diff --git a/arch/arm/mach-rockchip/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S index 5e6c8dba13..50fce207a5 100644 --- a/arch/arm/mach-rockchip/save_boot_param.S +++ b/arch/arm/mach-rockchip/save_boot_param.S @@ -1,11 +1,47 @@ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * * SPDX-License-Identifier: GPL-2.0+ */ #include <linux/linkage.h> +#if defined(CONFIG_ARM64) +.globl SAVE_SP_ADDR +SAVE_SP_ADDR: + .quad 0 + +ENTRY(save_boot_params) + sub sp, sp, #0x60 + stp x29, x30, [sp, #0x50] + stp x27, x28, [sp, #0x40] + stp x25, x26, [sp, #0x30] + stp x23, x24, [sp, #0x20] + stp x21, x22, [sp, #0x10] + stp x19, x20, [sp, #0] + ldr x8, =SAVE_SP_ADDR + mov x9, sp + str x9, [x8] + b save_boot_params_ret /* back to my caller */ +ENDPROC(save_boot_params) + +.globl _back_to_bootrom_s +ENTRY(_back_to_bootrom_s) + ldr x0, =SAVE_SP_ADDR + ldr x0, [x0] + mov sp, x0 + ldp x29, x30, [sp, #0x50] + ldp x27, x28, [sp, #0x40] + ldp x25, x26, [sp, #0x30] + ldp x23, x24, [sp, #0x20] + ldp x21, x22, [sp, #0x10] + ldp x19, x20, [sp] + add sp, sp, #0x60 + mov x0, xzr + ret +ENDPROC(_back_to_bootrom_s) +#else .globl SAVE_SP_ADDR SAVE_SP_ADDR: .word 0 @@ -30,3 +66,4 @@ ENTRY(_back_to_bootrom_s) mov r0, #0 pop {r1-r12, pc} ENDPROC(_back_to_bootrom_s) +#endif diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c new file mode 100644 index 0000000000..4f78c72720 --- /dev/null +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <mmc.h> +#include <spl.h> + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int spl_node_to_boot_device(int node) +{ + struct udevice *parent; + + /* + * This should eventually move into the SPL code, once SPL becomes + * aware of the block-device layer. Until then (and to avoid unneeded + * delays in getting this feature out, it lives at the board-level). + */ + if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) { + struct udevice *dev; + struct blk_desc *desc = NULL; + + for (device_find_first_child(parent, &dev); + dev; + device_find_next_child(&dev)) { + if (device_get_uclass_id(dev) == UCLASS_BLK) { + desc = dev_get_uclass_platdata(dev); + break; + } + } + + if (!desc) + return -ENOENT; + + switch (desc->devnum) { + case 0: + return BOOT_DEVICE_MMC1; + case 1: + return BOOT_DEVICE_MMC2; + default: + return -ENOSYS; + } + } + + /* + * SPL doesn't differentiate SPI flashes, so we keep the detection + * brief and inaccurate... hopefully, the common SPL layer can be + * extended with awareness of the BLK layer (and matching OF_CONTROL) + * soon. + */ + if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) + return BOOT_DEVICE_SPI; + + return -1; +} + +void board_boot_order(u32 *spl_boot_list) +{ + const void *blob = gd->fdt_blob; + int chosen_node = fdt_path_offset(blob, "/chosen"); + int idx = 0; + int elem; + int boot_device; + int node; + const char *conf; + + if (chosen_node < 0) { + debug("%s: /chosen not found, using spl_boot_device()\n", + __func__); + spl_boot_list[0] = spl_boot_device(); + return; + } + + for (elem = 0; + (conf = fdt_stringlist_get(blob, chosen_node, + "u-boot,spl-boot-order", elem, NULL)); + elem++) { + /* First check if the list element is an alias */ + const char *alias = fdt_get_alias(blob, conf); + if (alias) + conf = alias; + + /* Try to resolve the config item (or alias) as a path */ + node = fdt_path_offset(blob, conf); + if (node < 0) { + debug("%s: could not find %s in FDT", __func__, conf); + continue; + } + + /* Try to map this back onto SPL boot devices */ + boot_device = spl_node_to_boot_device(node); + if (boot_device < 0) { + debug("%s: could not map node @%x to a boot-device\n", + __func__, node); + continue; + } + + spl_boot_list[idx++] = boot_device; + } + + /* If we had no matches, fall back to spl_boot_device */ + if (idx == 0) + spl_boot_list[0] = spl_boot_device(); +} +#endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 49b26b3570..2f1da740fb 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -219,9 +219,9 @@ int arch_misc_init(void) { const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; const int fpga_id = socfpga_fpga_id(0); - setenv("bootmode", bsel_str[bsel].mode); + env_set("bootmode", bsel_str[bsel].mode); if (fpga_id >= 0) - setenv("fpgatype", socfpga_fpga_model[fpga_id].var); + env_set("fpgatype", socfpga_fpga_model[fpga_id].var); return socfpga_eth_reset(); } #endif diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 8f4371429f..f70f5ec965 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -3,9 +3,6 @@ if STM32 config STM32F4 bool "stm32f4 family" -config STM32F1 - bool "stm32f1 family" - config STM32F7 bool "stm32f7 family" select SUPPORT_SPL @@ -29,7 +26,6 @@ config STM32F7 select SPL_XIP_SUPPORT source "arch/arm/mach-stm32/stm32f4/Kconfig" -source "arch/arm/mach-stm32/stm32f1/Kconfig" source "arch/arm/mach-stm32/stm32f7/Kconfig" endif diff --git a/arch/arm/mach-stm32/Makefile b/arch/arm/mach-stm32/Makefile index ffc537f35b..6b7694471f 100644 --- a/arch/arm/mach-stm32/Makefile +++ b/arch/arm/mach-stm32/Makefile @@ -5,6 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_STM32F1) += stm32f1/ obj-$(CONFIG_STM32F4) += stm32f4/ obj-$(CONFIG_STM32F7) += stm32f7/ diff --git a/arch/arm/mach-stm32/stm32f1/Kconfig b/arch/arm/mach-stm32/stm32f1/Kconfig deleted file mode 100644 index f627fd2541..0000000000 --- a/arch/arm/mach-stm32/stm32f1/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -if STM32F1 - -endif diff --git a/arch/arm/mach-stm32/stm32f1/Makefile b/arch/arm/mach-stm32/stm32f1/Makefile deleted file mode 100644 index e2081dbf9e..0000000000 --- a/arch/arm/mach-stm32/stm32f1/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2015 -# Kamil Lulko, <kamil.lulko@gmail.com> -# -# Copyright 2015 ATS Advanced Telematics Systems GmbH -# Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += soc.o clock.o timer.o flash.o diff --git a/arch/arm/mach-stm32/stm32f1/clock.c b/arch/arm/mach-stm32/stm32f1/clock.c deleted file mode 100644 index 28208485d4..0000000000 --- a/arch/arm/mach-stm32/stm32f1/clock.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * (C) Copyright 2014 - * STMicroelectronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/stm32.h> - -#define RCC_CR_HSION (1 << 0) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_PLLRDY (1 << 25) - -#define RCC_CFGR_PLLMUL_MASK 0x3C0000 -#define RCC_CFGR_PLLMUL_SHIFT 18 -#define RCC_CFGR_PLLSRC_HSE (1 << 16) - -#define RCC_CFGR_AHB_PSC_MASK 0xF0 -#define RCC_CFGR_APB1_PSC_MASK 0x700 -#define RCC_CFGR_APB2_PSC_MASK 0x3800 -#define RCC_CFGR_SW0 (1 << 0) -#define RCC_CFGR_SW1 (1 << 1) -#define RCC_CFGR_SW_MASK 0x3 -#define RCC_CFGR_SW_HSI 0 -#define RCC_CFGR_SW_HSE RCC_CFGR_SW0 -#define RCC_CFGR_SW_PLL RCC_CFGR_SW1 -#define RCC_CFGR_SWS0 (1 << 2) -#define RCC_CFGR_SWS1 (1 << 3) -#define RCC_CFGR_SWS_MASK 0xC -#define RCC_CFGR_SWS_HSI 0 -#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 -#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 -#define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_PPRE1_SHIFT 8 -#define RCC_CFGR_PPRE2_SHIFT 11 - -#define RCC_APB1ENR_PWREN (1 << 28) - -#define PWR_CR_VOS0 (1 << 14) -#define PWR_CR_VOS1 (1 << 15) -#define PWR_CR_VOS_MASK 0xC000 -#define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1) -#define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1) -#define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0) - -#define FLASH_ACR_WS(n) n -#define FLASH_ACR_PRFTEN (1 << 8) -#define FLASH_ACR_ICEN (1 << 9) -#define FLASH_ACR_DCEN (1 << 10) - -struct psc { - u8 ahb_psc; - u8 apb1_psc; - u8 apb2_psc; -}; - -#define AHB_PSC_1 0 -#define AHB_PSC_2 0x8 -#define AHB_PSC_4 0x9 -#define AHB_PSC_8 0xA -#define AHB_PSC_16 0xB -#define AHB_PSC_64 0xC -#define AHB_PSC_128 0xD -#define AHB_PSC_256 0xE -#define AHB_PSC_512 0xF - -#define APB_PSC_1 0 -#define APB_PSC_2 0x4 -#define APB_PSC_4 0x5 -#define APB_PSC_8 0x6 -#define APB_PSC_16 0x7 - -#if !defined(CONFIG_STM32_HSE_HZ) -#error "CONFIG_STM32_HSE_HZ not defined!" -#else -#if (CONFIG_STM32_HSE_HZ == 8000000) -#define RCC_CFGR_PLLMUL_CFG 0x7 -struct psc psc_hse = { - .ahb_psc = AHB_PSC_1, - .apb1_psc = APB_PSC_2, - .apb2_psc = APB_PSC_1 -}; -#else -#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" -#endif -#endif - -int configure_clocks(void) -{ - /* Reset RCC configuration */ - setbits_le32(&STM32_RCC->cr, RCC_CR_HSION); - writel(0, &STM32_RCC->cfgr); /* Reset CFGR */ - clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON - | RCC_CR_PLLON)); - clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP); - writel(0, &STM32_RCC->cir); /* Disable all interrupts */ - - /* Configure for HSE+PLL operation */ - setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON); - while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) - ; - - /* Enable high performance mode, System frequency up to 168 MHz */ - setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); - writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr); - - setbits_le32(&STM32_RCC->cfgr, - RCC_CFGR_PLLMUL_CFG << RCC_CFGR_PLLMUL_SHIFT); - setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_PLLSRC_HSE); - setbits_le32(&STM32_RCC->cfgr, (( - psc_hse.ahb_psc << RCC_CFGR_HPRE_SHIFT) - | (psc_hse.apb1_psc << RCC_CFGR_PPRE1_SHIFT) - | (psc_hse.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); - - setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON); - - while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY)) - ; - - /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */ - writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN - | FLASH_ACR_DCEN, &STM32_FLASH->acr); - - clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); - setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); - - while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) != - RCC_CFGR_SWS_PLL) - ; - - return 0; -} - -unsigned long clock_get(enum clock clck) -{ - u32 sysclk = 0; - u32 shift = 0; - /* PLL table lookups for clock computation */ - u8 pll_mul_table[16] = { - 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16 - }; - /* Prescaler table lookups for clock computation */ - u8 ahb_psc_table[16] = { - 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 - }; - u8 apb_psc_table[8] = { - 0, 0, 0, 0, 1, 2, 3, 4 - }; - - if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) == - RCC_CFGR_SWS_PLL) { - u16 pll; - pll = ((readl(&STM32_RCC->cfgr) & RCC_CFGR_PLLMUL_MASK) - >> RCC_CFGR_PLLMUL_SHIFT); - sysclk = CONFIG_STM32_HSE_HZ * pll_mul_table[pll]; - } - - switch (clck) { - case CLOCK_CORE: - return sysclk; - break; - case CLOCK_AHB: - shift = ahb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) - >> RCC_CFGR_HPRE_SHIFT)]; - return sysclk >>= shift; - break; - case CLOCK_APB1: - shift = apb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK) - >> RCC_CFGR_PPRE1_SHIFT)]; - return sysclk >>= shift; - break; - case CLOCK_APB2: - shift = apb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK) - >> RCC_CFGR_PPRE2_SHIFT)]; - return sysclk >>= shift; - break; - default: - return 0; - break; - } -} diff --git a/arch/arm/mach-stm32/stm32f1/flash.c b/arch/arm/mach-stm32/stm32f1/flash.c deleted file mode 100644 index 7d41f63733..0000000000 --- a/arch/arm/mach-stm32/stm32f1/flash.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/stm32.h> - -#define STM32_FLASH_KEY1 0x45670123 -#define STM32_FLASH_KEY2 0xcdef89ab - -#define STM32_NUM_BANKS 2 -#define STM32_MAX_BANK 0x200 - -flash_info_t flash_info[STM32_NUM_BANKS]; -static struct stm32_flash_bank_regs *flash_bank[STM32_NUM_BANKS]; - -static void stm32f1_flash_lock(u8 bank, u8 lock) -{ - if (lock) { - setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_LOCK); - } else { - writel(STM32_FLASH_KEY1, &flash_bank[bank]->keyr); - writel(STM32_FLASH_KEY2, &flash_bank[bank]->keyr); - } -} - -/* Only XL devices are supported (2 KiB sector size) */ -unsigned long flash_init(void) -{ - u8 i, banks; - u16 j, size; - - /* Set up accessors for XL devices with wonky register layout */ - flash_bank[0] = (struct stm32_flash_bank_regs *)&STM32_FLASH->keyr; - flash_bank[1] = (struct stm32_flash_bank_regs *)&STM32_FLASH->keyr2; - - /* - * Get total flash size (in KiB) and configure number of banks - * present and sector count per bank. - */ - size = readw(&STM32_DES->flash_size); - if (size <= STM32_MAX_BANK) { - banks = 1; - flash_info[0].sector_count = size >> 1; - } else if (size > STM32_MAX_BANK) { - banks = 2; - flash_info[0].sector_count = STM32_MAX_BANK >> 1; - flash_info[1].sector_count = (size - STM32_MAX_BANK) >> 1; - } - - /* Configure start/size for all sectors */ - for (i = 0; i < banks; i++) { - flash_info[i].flash_id = FLASH_STM32F1; - flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 19); - flash_info[i].size = 2048; - for (j = 1; (j < flash_info[i].sector_count); j++) { - flash_info[i].start[j] = flash_info[i].start[j - 1] - + 2048; - flash_info[i].size += 2048; - } - } - - return size << 10; -} - -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Missing or unknown FLASH type\n"); - return; - } else if (info->flash_id == FLASH_STM32F1) { - printf("STM32F1 Embedded Flash\n"); - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf("\n"); - return; -} - -int flash_erase(flash_info_t *info, int first, int last) -{ - u8 bank = 0xff; - int i; - - for (i = 0; i < STM32_NUM_BANKS; i++) { - if (info == &flash_info[i]) { - bank = i; - break; - } - } - if (bank == 0xff) - return -1; - - stm32f1_flash_lock(bank, 0); - - for (i = first; i <= last; i++) { - while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY) - ; - - setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PER); - - writel(info->start[i], &flash_bank[bank]->ar); - - setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_STRT); - - while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY) - ; - } - - clrbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PER); - - stm32f1_flash_lock(bank, 1); - - return 0; -} - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong i; - u8 bank = 0xff; - - if (addr & 1) { - printf("Flash address must be half word aligned\n"); - return -1; - } - - if (cnt & 1) { - printf("Flash length must be half word aligned\n"); - return -1; - } - - for (i = 0; i < 2; i++) { - if (info == &flash_info[i]) { - bank = i; - break; - } - } - - if (bank == 0xff) - return -1; - - while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY) - ; - - stm32f1_flash_lock(bank, 0); - - setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PG); - - /* STM32F1 requires half word writes */ - for (i = 0; i < cnt >> 1; i++) { - *(u16 *)(addr + i * 2) = ((u16 *)src)[i]; - while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY) - ; - } - - clrbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PG); - - stm32f1_flash_lock(bank, 1); - - return 0; -} diff --git a/arch/arm/mach-stm32/stm32f1/soc.c b/arch/arm/mach-stm32/stm32f1/soc.c deleted file mode 100644 index 4438621b9a..0000000000 --- a/arch/arm/mach-stm32/stm32f1/soc.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/armv7m.h> -#include <asm/arch/stm32.h> - -u32 get_cpu_rev(void) -{ - return 0; -} - -int arch_cpu_init(void) -{ - configure_clocks(); - - /* - * Configure the memory protection unit (MPU) to allow full access to - * the whole 4GB address space. - */ - writel(0, &V7M_MPU->rnr); - writel(0, &V7M_MPU->rbar); - writel((V7M_MPU_RASR_AP_RW_RW | V7M_MPU_RASR_SIZE_4GB - | V7M_MPU_RASR_EN), &V7M_MPU->rasr); - writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); - - return 0; -} diff --git a/arch/arm/mach-stm32/stm32f1/timer.c b/arch/arm/mach-stm32/stm32f1/timer.c deleted file mode 100644 index 6a261986e9..0000000000 --- a/arch/arm/mach-stm32/stm32f1/timer.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/armv7m.h> -#include <asm/arch/stm32.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define STM32_TIM2_BASE (STM32_APB1PERIPH_BASE + 0x0000) - -#define RCC_APB1ENR_TIM2EN (1 << 0) - -struct stm32_tim2_5 { - u32 cr1; - u32 cr2; - u32 smcr; - u32 dier; - u32 sr; - u32 egr; - u32 ccmr1; - u32 ccmr2; - u32 ccer; - u32 cnt; - u32 psc; - u32 arr; - u32 reserved1; - u32 ccr1; - u32 ccr2; - u32 ccr3; - u32 ccr4; - u32 reserved2; - u32 dcr; - u32 dmar; - u32 or; -}; - -#define TIM_CR1_CEN (1 << 0) - -#define TIM_EGR_UG (1 << 0) - -int timer_init(void) -{ - struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; - - setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); - - if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1)) - writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1, - &tim->psc); - else - writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1, - &tim->psc); - - writel(0xFFFFFFFF, &tim->arr); - writel(TIM_CR1_CEN, &tim->cr1); - setbits_le32(&tim->egr, TIM_EGR_UG); - - gd->arch.tbl = 0; - gd->arch.tbu = 0; - gd->arch.lastinc = 0; - - return 0; -} - -ulong get_timer(ulong base) -{ - return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base; -} - -unsigned long long get_ticks(void) -{ - struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; - u32 now; - - now = readl(&tim->cnt); - - if (now >= gd->arch.lastinc) - gd->arch.tbl += (now - gd->arch.lastinc); - else - gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now; - - gd->arch.lastinc = now; - - return gd->arch.tbl; -} - -void reset_timer(void) -{ - struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; - - gd->arch.lastinc = readl(&tim->cnt); - gd->arch.tbl = 0; -} - -/* delay x useconds */ -void __udelay(ulong usec) -{ - unsigned long long start; - - start = get_ticks(); /* get current timestamp */ - while ((get_ticks() - start) < usec) - ; /* loop till time has passed */ -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ_CLOCK; -} diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 94412bac0c..2cd7bae078 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,5 +1,8 @@ if ARCH_SUNXI +config SPL_LDSCRIPT + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 + config IDENT_STRING default " Allwinner Technology" @@ -59,7 +62,6 @@ config MACH_SUNXI_H3_H5 select SUNXI_DRAM_DW_32BIT select SUNXI_GEN_SUN6I select SUPPORT_SPL - imply ENV_IS_IN_MMC choice prompt "Sunxi SoC Variant" @@ -71,7 +73,6 @@ config MACH_SUN4I select ARM_CORTEX_CPU_IS_UP select SUNXI_GEN_SUN4I select SUPPORT_SPL - imply ENV_IS_IN_MMC config MACH_SUN5I bool "sun5i (Allwinner A13)" @@ -89,7 +90,6 @@ config MACH_SUN6I select SUNXI_GEN_SUN6I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - imply ENV_IS_IN_MMC config MACH_SUN7I bool "sun7i (Allwinner A20)" @@ -100,7 +100,6 @@ config MACH_SUN7I select SUNXI_GEN_SUN4I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - imply ENV_IS_IN_MMC config MACH_SUN8I_A23 bool "sun8i (Allwinner A23)" @@ -111,7 +110,6 @@ config MACH_SUN8I_A23 select SUNXI_GEN_SUN6I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - imply ENV_IS_IN_MMC config MACH_SUN8I_A33 bool "sun8i (Allwinner A33)" @@ -137,7 +135,6 @@ config MACH_SUN8I_H3 select ARCH_SUPPORT_PSCI select MACH_SUNXI_H3_H5 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - imply ENV_IS_IN_MMC config MACH_SUN8I_R40 bool "sun8i (Allwinner R40)" diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 58085dc0a3..51e50907d2 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -60,7 +60,6 @@ config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" select ARM64 select TEGRA_COMMON - imply ENV_IS_IN_MMC choice prompt "Tegra SoC select" @@ -78,7 +77,6 @@ config TEGRA30 select ARM_ERRATA_743622 select ARM_ERRATA_751472 select TEGRA_ARMV7_COMMON - imply ENV_IS_IN_MMC config TEGRA114 bool "Tegra114 family" @@ -87,7 +85,6 @@ config TEGRA114 config TEGRA124 bool "Tegra124 family" select TEGRA_ARMV7_COMMON - imply ENV_IS_IN_MMC imply REGMAP imply SYSCON diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index bd137969f0..0426b7a95a 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -214,9 +214,9 @@ int board_late_init(void) #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) if (tegra_cpu_is_non_secure()) { printf("CPU is in NS mode\n"); - setenv("cpu_ns_mode", "1"); + env_set("cpu_ns_mode", "1"); } else { - setenv("cpu_ns_mode", ""); + env_set("cpu_ns_mode", ""); } #endif start_cpu_fan(); diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_board.c b/arch/arm/mach-tegra/tegra186/nvtboot_board.c index feb935f0d9..b94eb424aa 100644 --- a/arch/arm/mach-tegra/tegra186/nvtboot_board.c +++ b/arch/arm/mach-tegra/tegra186/nvtboot_board.c @@ -15,7 +15,7 @@ static int set_fdt_addr(void) { int ret; - ret = setenv_hex("fdt_addr", nvtboot_boot_x0); + ret = env_set_hex("fdt_addr", nvtboot_boot_x0); if (ret) { printf("Failed to set fdt_addr to point at DTB: %d\n", ret); return ret; @@ -35,7 +35,7 @@ static int set_ethaddr_from_nvtboot(void) const u32 *prop; /* Already a valid address in the environment? If so, keep it */ - if (getenv("ethaddr")) + if (env_get("ethaddr")) return 0; node = fdt_path_offset(nvtboot_blob, "/chosen"); @@ -49,7 +49,7 @@ static int set_ethaddr_from_nvtboot(void) return -ENOENT; } - ret = setenv("ethaddr", (void *)prop); + ret = env_set("ethaddr", (void *)prop); if (ret) { printf("Failed to set ethaddr from nvtboot DTB: %d\n", ret); return ret; diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 1aed55a539..3147db76cb 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -9,6 +9,7 @@ config ARCH_UNIPHIER_32BIT select CPU_V7_HAS_NONSEC select ARMV7_NONSEC select ARCH_SUPPORT_PSCI + imply NAND choice prompt "UniPhier SoC select" diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 4bfa10b374..b9a2cbe148 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -37,7 +37,7 @@ static int uniphier_set_fdt_file(void) char dtb_name[256]; int buf_len = sizeof(dtb_name); - if (getenv("fdt_file")) + if (env_get("fdt_file")) return 0; /* do nothing if it is already set */ compat = fdt_stringlist_get(gd->fdt_blob, 0, "compatible", 0, NULL); @@ -55,7 +55,7 @@ static int uniphier_set_fdt_file(void) strncat(dtb_name, ".dtb", buf_len); - return setenv("fdt_file", dtb_name); + return env_set("fdt_file", dtb_name); } int board_late_init(void) @@ -65,20 +65,20 @@ int board_late_init(void) switch (uniphier_boot_device_raw()) { case BOOT_DEVICE_MMC1: printf("eMMC Boot"); - setenv("bootmode", "emmcboot"); + env_set("bootmode", "emmcboot"); break; case BOOT_DEVICE_NAND: printf("NAND Boot"); - setenv("bootmode", "nandboot"); + env_set("bootmode", "nandboot"); nand_denali_wp_disable(); break; case BOOT_DEVICE_NOR: printf("NOR Boot"); - setenv("bootmode", "norboot"); + env_set("bootmode", "norboot"); break; case BOOT_DEVICE_USB: printf("USB Boot"); - setenv("bootmode", "usbboot"); + env_set("bootmode", "usbboot"); break; default: printf("Unknown"); diff --git a/arch/arm/mach-uniphier/mmc-first-dev.c b/arch/arm/mach-uniphier/mmc-first-dev.c index 8c45229a89..acc859a6c3 100644 --- a/arch/arm/mach-uniphier/mmc-first-dev.c +++ b/arch/arm/mach-uniphier/mmc-first-dev.c @@ -35,7 +35,7 @@ static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (dev < 0) return CMD_RET_FAILURE; - setenv_ulong("mmc_first_dev", dev); + env_set_ulong("mmc_first_dev", dev); return CMD_RET_SUCCESS; } diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index c428ce5cc7..b9cd45ba09 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,5 +1,8 @@ if ARCH_ZYNQ +config SPL_LDSCRIPT + default "arch/arm/mach-zynq/u-boot-spl.lds" + config SPL_FAT_SUPPORT default y diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 88e7d6a7b6..26509b73c6 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -10,7 +10,6 @@ config MCF520x config MCF52x2 bool - imply ENV_IS_IN_FLASH config MCF523x bool @@ -23,7 +22,6 @@ config MCF5301x config MCF532x bool - imply ENV_IS_IN_FLASH config MCF537x bool @@ -39,7 +37,6 @@ config MCF5227x config MCF547x_8x bool - imply ENV_IS_IN_FLASH # processor type config M5208 @@ -73,7 +70,6 @@ config M5275 config M5282 bool select MCF52x2 - imply ENV_IS_IN_FLASH config M5307 bool @@ -111,12 +107,10 @@ config M52277 config M547x bool select MCF547x_8x - imply ENV_IS_IN_FLASH config M548x bool select MCF547x_8x - imply ENV_IS_IN_FLASH choice prompt "Target select" @@ -197,12 +191,10 @@ config TARGET_M54455EVB config TARGET_M5475EVB bool "Support M5475EVB" select M547x - imply ENV_IS_IN_FLASH config TARGET_M5485EVB bool "Support M5485EVB" select M548x - imply ENV_IS_IN_FLASH config TARGET_AMCORE bool "Support AMCORE" diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index fa9c493081..c976904fa9 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -113,7 +113,8 @@ static void set_clocks_in_mhz (bd_t *kbd) { char *s; - if ((s = getenv("clocks_in_mhz")) != NULL) { + s = env_get("clocks_in_mhz"); + if (s) { /* convert all clock information to MHz */ kbd->bi_intfreq /= 1000000L; kbd->bi_busfreq /= 1000000L; diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 20fa25b5cc..f791c0081e 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -21,4 +21,7 @@ endchoice source "board/xilinx/microblaze-generic/Kconfig" +config SPL_LDSCRIPT + default "arch/microblaze/cpu/u-boot-spl.lds" + endmenu diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 2732203b93..0a286e82c2 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -27,7 +27,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], { /* First parameter is mapped to $r5 for kernel boot args */ void (*thekernel) (char *, ulong, ulong); - char *commandline = getenv("bootargs"); + char *commandline = env_get("bootargs"); ulong rd_data_start, rd_data_end; /* diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b53206bf8e..d07b92d1b4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -21,7 +21,6 @@ config TARGET_QEMU_MIPS select SUPPORTS_CPU_MIPS64_R1 select SUPPORTS_CPU_MIPS64_R2 select ROM_EXCEPTION_VECTORS - imply ENV_IS_IN_FLASH config TARGET_MALTA bool "Support malta" @@ -43,7 +42,6 @@ config TARGET_MALTA select SWAP_IO_SPACE select MIPS_L1_CACHE_SHIFT_6 select ROM_EXCEPTION_VECTORS - imply ENV_IS_IN_FLASH config TARGET_VCT bool "Support vct" @@ -85,7 +83,6 @@ config ARCH_BMIPS select CPU select RAM select SYSRESET - imply ENV_IS_NOWHERE config MACH_PIC32 bool "Support Microchip PIC32" @@ -110,7 +107,6 @@ config TARGET_BOSTON select SUPPORTS_CPU_MIPS64_R2 select SUPPORTS_CPU_MIPS64_R6 select ROM_EXCEPTION_VECTORS - imply ENV_IS_IN_FLASH config TARGET_XILFPGA bool "Support Imagination Xilfpga" @@ -200,7 +196,6 @@ config CPU_MIPS64_R2 bool "MIPS64 Release 2" depends on SUPPORTS_CPU_MIPS64_R2 select 64BIT - imply ENV_IS_IN_FLASH help Choose this option to build a kernel for release 2 through 5 of the MIPS64 architecture. diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 2b6790524c..5a9a2811ff 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -80,7 +80,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images) linux_cmdline_init(); - bootargs = getenv("bootargs"); + bootargs = env_get("bootargs"); if (!bootargs) return; @@ -202,11 +202,11 @@ static void linux_env_legacy(bootm_headers_t *images) sprintf(env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); linux_env_set("flash_size", env_buf); - cp = getenv("ethaddr"); + cp = env_get("ethaddr"); if (cp) linux_env_set("ethaddr", cp); - cp = getenv("eth1addr"); + cp = env_get("eth1addr"); if (cp) linux_env_set("eth1addr", cp); diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c index 21aadf284f..e834329e0b 100644 --- a/arch/nds32/lib/bootm.c +++ b/arch/nds32/lib/bootm.c @@ -50,7 +50,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) void (*theKernel)(int zero, int arch, uint params); #ifdef CONFIG_CMDLINE_TAG - char *commandline = getenv("bootargs"); + char *commandline = env_get("bootargs"); #endif /* @@ -64,7 +64,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) theKernel = (void (*)(int, int, uint))images->ep; - s = getenv("machid"); + s = env_get("machid"); if (s) { machid = simple_strtoul(s, NULL, 16); printf("Using machid 0x%x from environment\n", machid); diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index 4e5c269193..00ade2c573 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -12,7 +12,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) { void (*kernel)(int, int, int, char *) = (void *)images->ep; - char *commandline = getenv("bootargs"); + char *commandline = env_get("bootargs"); ulong initrd_start = images->rd_start; ulong initrd_end = images->rd_end; char *of_flat_tree = NULL; diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 8094416e4a..e4b3043fa2 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -28,10 +28,11 @@ config MPC86xx bool "MPC86xx" select SYS_FSL_DDR select SYS_FSL_DDR_BE - imply ENV_IS_IN_FLASH + imply CMD_REGINFO config 8xx bool "MPC8xx" + imply CMD_REGINFO endchoice diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index b5b26f9b3a..a3779734c1 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -13,7 +13,6 @@ config TARGET_MPC8308_P1M config TARGET_SBC8349 bool "Support sbc8349" - imply ENV_IS_IN_FLASH config TARGET_VE8313 bool "Support ve8313" @@ -40,7 +39,6 @@ config TARGET_MPC8323ERDB config TARGET_MPC832XEMDS bool "Support MPC832XEMDS" select BOARD_EARLY_INIT_F - imply ENV_IS_IN_FLASH config TARGET_MPC8349EMDS bool "Support MPC8349EMDS" @@ -52,7 +50,6 @@ config TARGET_MPC8349EMDS config TARGET_MPC8349ITX bool "Support MPC8349ITX" imply CMD_IRQ - imply ENV_IS_IN_FLASH config TARGET_MPC837XEMDS bool "Support MPC837XEMDS" @@ -77,13 +74,11 @@ config TARGET_SUVD3 bool "Support suvd3" imply CMD_CRAMFS imply FS_CRAMFS - imply ENV_IS_IN_FLASH config TARGET_TUXX1 bool "Support tuxx1" imply CMD_CRAMFS imply FS_CRAMFS - imply ENV_IS_IN_FLASH config TARGET_TQM834X bool "Support TQM834x" @@ -95,7 +90,7 @@ config TARGET_HRCON config TARGET_STRIDER bool "Support strider" select SYS_FSL_ERRATUM_ESDHC111 - imply ENV_IS_IN_FLASH + imply CMD_PCA953X endchoice diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 93a454cf1f..92187d371b 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -19,7 +19,6 @@ choice config TARGET_SBC8548 bool "Support sbc8548" select ARCH_MPC8548 - imply ENV_IS_IN_FLASH config TARGET_SOCRATES bool "Support socrates" @@ -105,7 +104,6 @@ config TARGET_MPC8544DS config TARGET_MPC8548CDS bool "Support MPC8548CDS" select ARCH_MPC8548 - imply ENV_IS_IN_FLASH config TARGET_MPC8555CDS bool "Support MPC8555CDS" @@ -427,6 +425,7 @@ config ARCH_B4420 select FSL_IFC imply CMD_EEPROM imply CMD_NAND + imply CMD_REGINFO config ARCH_B4860 bool @@ -454,6 +453,7 @@ config ARCH_B4860 select FSL_IFC imply CMD_EEPROM imply CMD_NAND + imply CMD_REGINFO config ARCH_BSC9131 bool @@ -469,6 +469,7 @@ config ARCH_BSC9131 select FSL_IFC imply CMD_EEPROM imply CMD_NAND + imply CMD_REGINFO config ARCH_BSC9132 bool @@ -489,6 +490,8 @@ config ARCH_BSC9132 imply CMD_EEPROM imply CMD_MTDPARTS imply CMD_NAND + imply CMD_PCI + imply CMD_REGINFO config ARCH_C29X bool @@ -503,6 +506,8 @@ config ARCH_C29X select SYS_PPC_E500_USE_DEBUG_TLB select FSL_IFC imply CMD_NAND + imply CMD_PCI + imply CMD_REGINFO config ARCH_MPC8536 bool @@ -518,6 +523,7 @@ config ARCH_MPC8536 select FSL_ELBC imply CMD_NAND imply CMD_SATA + imply CMD_REGINFO config ARCH_MPC8540 bool @@ -557,7 +563,7 @@ config ARCH_MPC8548 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB - imply ENV_IS_IN_FLASH + imply CMD_REGINFO config ARCH_MPC8555 bool @@ -607,7 +613,6 @@ config ARCH_MPC8572 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC imply CMD_NAND - imply ENV_IS_IN_FLASH config ARCH_P1010 bool @@ -633,6 +638,8 @@ config ARCH_P1010 imply CMD_MTDPARTS imply CMD_NAND imply CMD_SATA + imply CMD_PCI + imply CMD_REGINFO config ARCH_P1011 bool @@ -663,6 +670,8 @@ config ARCH_P1020 select FSL_ELBC imply CMD_NAND imply CMD_SATA + imply CMD_PCI + imply CMD_REGINFO config ARCH_P1021 bool @@ -677,8 +686,10 @@ config ARCH_P1021 select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC + imply CMD_REGINFO imply CMD_NAND imply CMD_SATA + imply CMD_REGINFO config ARCH_P1022 bool @@ -724,6 +735,8 @@ config ARCH_P1024 imply CMD_EEPROM imply CMD_NAND imply CMD_SATA + imply CMD_PCI + imply CMD_REGINFO config ARCH_P1025 bool @@ -739,6 +752,7 @@ config ARCH_P1025 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC imply CMD_SATA + imply CMD_REGINFO config ARCH_P2020 bool @@ -756,6 +770,7 @@ config ARCH_P2020 select FSL_ELBC imply CMD_EEPROM imply CMD_NAND + imply CMD_REGINFO config ARCH_P2041 bool @@ -805,6 +820,7 @@ config ARCH_P3041 select FSL_ELBC imply CMD_NAND imply CMD_SATA + imply CMD_REGINFO config ARCH_P4080 bool @@ -841,6 +857,7 @@ config ARCH_P4080 select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC imply CMD_SATA + imply CMD_REGINFO config ARCH_P5020 bool @@ -863,6 +880,7 @@ config ARCH_P5020 select SYS_PPC64 select FSL_ELBC imply CMD_SATA + imply CMD_REGINFO config ARCH_P5040 bool @@ -885,6 +903,7 @@ config ARCH_P5040 select SYS_PPC64 select FSL_ELBC imply CMD_SATA + imply CMD_REGINFO config ARCH_QEMU_E500 bool @@ -907,6 +926,7 @@ config ARCH_T1023 select FSL_IFC imply CMD_EEPROM imply CMD_NAND + imply CMD_REGINFO config ARCH_T1024 bool @@ -927,6 +947,7 @@ config ARCH_T1024 imply CMD_EEPROM imply CMD_NAND imply CMD_MTDPARTS + imply CMD_REGINFO config ARCH_T1040 bool @@ -948,6 +969,7 @@ config ARCH_T1040 imply CMD_MTDPARTS imply CMD_NAND imply CMD_SATA + imply CMD_REGINFO config ARCH_T1042 bool @@ -969,6 +991,7 @@ config ARCH_T1042 imply CMD_MTDPARTS imply CMD_NAND imply CMD_SATA + imply CMD_REGINFO config ARCH_T2080 bool @@ -993,6 +1016,7 @@ config ARCH_T2080 select FSL_IFC imply CMD_SATA imply CMD_NAND + imply CMD_REGINFO config ARCH_T2081 bool @@ -1014,6 +1038,7 @@ config ARCH_T2081 select SYS_PPC64 select FSL_IFC imply CMD_NAND + imply CMD_REGINFO config ARCH_T4160 bool @@ -1037,6 +1062,7 @@ config ARCH_T4160 select FSL_IFC imply CMD_SATA imply CMD_NAND + imply CMD_REGINFO config ARCH_T4240 bool @@ -1063,6 +1089,7 @@ config ARCH_T4240 select FSL_IFC imply CMD_SATA imply CMD_NAND + imply CMD_REGINFO config BOOKE bool @@ -1076,6 +1103,7 @@ config E500 config E500MC bool + imply CMD_PCI help Enble PowerPC E500MC core diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index a3076d8d71..ea46e49853 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -256,7 +256,7 @@ static void enable_tdm_law(void) * is not setup properly yet. Search for tdm entry in * hwconfig. */ - ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + ret = env_get_f("hwconfig", buffer, sizeof(buffer)); if (ret > 0) { tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); /* If tdm is defined in hwconfig, set law for tdm workaround */ @@ -280,7 +280,7 @@ void enable_cpc(void) cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; /* Extract hwconfig from environment */ - ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + ret = env_get_f("hwconfig", buffer, sizeof(buffer)); if (ret > 0) { /* * If "en_cpc" is not defined in hwconfig then by default all @@ -754,7 +754,7 @@ int cpu_init_r(void) char *buf = NULL; int n, res; - n = getenv_f("hwconfig", buffer, sizeof(buffer)); + n = env_get_f("hwconfig", buffer, sizeof(buffer)); if (n > 0) buf = buffer; @@ -794,7 +794,7 @@ int cpu_init_r(void) #endif #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) - spin = getenv("spin_table_compat"); + spin = env_get("spin_table_compat"); if (spin && (*spin == 'n')) spin_table_compat = 0; else @@ -845,7 +845,7 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_SRIO srio_init(); #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER - char *s = getenv("bootmaster"); + char *s = env_get("bootmaster"); if (s) { if (!strcmp(s, "SRIO1")) { srio_boot_master(1); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index caa0bf9bdc..297dc4af48 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -92,7 +92,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) * Extract hwconfig from environment. * Search for tdm entry in hwconfig. */ - ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + ret = env_get_f("hwconfig", buffer, sizeof(buffer)); if (ret > 0) tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); @@ -580,7 +580,7 @@ static void fdt_fixup_l2_switch(void *blob) return; /* Get MAC address for the l2switch from "l2switchaddr"*/ - if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) { + if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) { printf("Warning: MAC address for l2switch not found\n"); memset(l2swaddr, 0, sizeof(l2swaddr)); } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 1bc0c64cfc..79d6544a09 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -514,7 +514,7 @@ void fsl_serdes_init(void) * Extract hwconfig from environment since we have not properly setup * the environment but need it for ddr config params */ - if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; #endif if (serdes_prtcl_map & (1 << NONE)) diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 0addf8493c..2ea9f5c7be 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -31,7 +31,7 @@ u32 get_my_id() int hold_cores_in_reset(int verbose) { /* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */ - if (getenv_yesno("mp_holdoff") == 1) { + if (env_get_yesno("mp_holdoff") == 1) { if (verbose) { puts("Secondary cores are being held in reset.\n"); puts("See 'mp_holdoff' environment variable\n"); diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig index fe56efdf55..2cc180da38 100644 --- a/arch/powerpc/cpu/mpc86xx/Kconfig +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -40,7 +40,6 @@ config ARCH_MPC8641 select FSL_LAW select SYS_FSL_HAS_DDR1 select SYS_FSL_HAS_DDR2 - imply ENV_IS_IN_FLASH config FSL_LAW bool diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 0e204027af..b9ae24dc98 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -86,7 +86,7 @@ static void boot_jump_linux(bootm_headers_t *images) debug (" Booting using OF flat tree...\n"); WATCHDOG_RESET (); (*kernel) ((bd_t *)of_flat_tree, 0, 0, EPAPR_MAGIC, - getenv_bootm_mapsize(), 0, 0); + env_get_bootm_mapsize(), 0, 0); /* does not return */ } else #endif @@ -121,8 +121,8 @@ void arch_lmb_reserve(struct lmb *lmb) phys_size_t bootm_size; ulong size, sp, bootmap_base; - bootmap_base = getenv_bootm_low(); - bootm_size = getenv_bootm_size(); + bootmap_base = env_get_bootm_low(); + bootm_size = env_get_bootm_size(); #ifdef DEBUG if (((u64)bootmap_base + bootm_size) > @@ -275,7 +275,8 @@ static void set_clocks_in_mhz (bd_t *kbd) { char *s; - if ((s = getenv ("clocks_in_mhz")) != NULL) { + s = env_get("clocks_in_mhz"); + if (s) { /* convert all clock information to MHz */ kbd->bi_intfreq /= 1000000L; kbd->bi_busfreq /= 1000000L; @@ -339,6 +340,6 @@ void boot_jump_vxworks(bootm_headers_t *images) ((void (*)(void *, ulong, ulong, ulong, ulong, ulong, ulong))images->ep)(images->ft_addr, - 0, 0, EPAPR_MAGIC, getenv_bootm_mapsize(), 0, 0); + 0, 0, EPAPR_MAGIC, env_get_bootm_mapsize(), 0, 0); } #endif diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 1d40fe6845..d20761e66c 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -3,16 +3,13 @@ menu "SuperH architecture" config CPU_SH2 bool - imply ENV_IS_IN_FLASH config CPU_SH2A bool select CPU_SH2 - imply ENV_IS_IN_FLASH config CPU_SH3 bool - imply ENV_IS_IN_FLASH config CPU_SH4 bool @@ -128,6 +125,8 @@ config SYS_CPU default "sh3" if CPU_SH3 default "sh4" if CPU_SH4 +source "arch/sh/lib/Kconfig" + source "board/alphaproject/ap_sh4a_4a/Kconfig" source "board/espt/Kconfig" source "board/mpr2/Kconfig" diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index bbf9ff485f..7fc91bc4aa 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -33,9 +33,9 @@ SECTIONS KEEP(CONFIG_BOARDDIR/lowlevel_init.o (.text .spiboot1.text)) KEEP(*(.spiboot2.text)) . = ALIGN(8192); - common/env_embedded.o (.ppcenv) + env/embedded.o (.ppcenv) . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) + env/embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); diff --git a/arch/sh/lib/Kconfig b/arch/sh/lib/Kconfig new file mode 100644 index 0000000000..cec8d09cc3 --- /dev/null +++ b/arch/sh/lib/Kconfig @@ -0,0 +1,6 @@ +config CMD_SH_ZIMAGEBOOT + bool "zimageboot - Boot a zImage on SH" + default y + help + This is special SH-specific command to boot a zImage (compressed + Linux image) on SH-architecture boards. diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index 8a0010be23..09fbd5e5df 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -61,7 +61,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima char *cmdline = (char *)param + COMMAND_LINE; /* PAGE_SIZE */ unsigned long size = images->ep - (unsigned long)param; - char *bootargs = getenv("bootargs"); + char *bootargs = env_get("bootargs"); /* * allow the PREP bootm subcommand, it is required for bootm to work diff --git a/arch/sh/lib/zimageboot.c b/arch/sh/lib/zimageboot.c index 3fea5f5b53..cd4abba10a 100644 --- a/arch/sh/lib/zimageboot.c +++ b/arch/sh/lib/zimageboot.c @@ -42,7 +42,7 @@ int do_sh_zimageboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Linux kernel command line */ cmdline = (char *)param + COMMAND_LINE; - bootargs = getenv("bootargs"); + bootargs = env_get("bootargs"); /* Clear zero page */ /* cppcheck-suppress nullPointer */ diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig index 9374c121f9..75dbbc27f1 100644 --- a/arch/x86/cpu/baytrail/Kconfig +++ b/arch/x86/cpu/baytrail/Kconfig @@ -10,7 +10,6 @@ config INTEL_BAYTRAIL select ARCH_MISC_INIT if !EFI imply HAVE_INTEL_ME if !EFI imply ENABLE_MRC_CACHE - imply ENV_IS_IN_SPI_FLASH imply AHCI_PCI imply ICH_SPI imply INTEL_ICH6_GPIO diff --git a/arch/x86/cpu/broadwell/Kconfig b/arch/x86/cpu/broadwell/Kconfig index b421f18202..bc2dba2bd7 100644 --- a/arch/x86/cpu/broadwell/Kconfig +++ b/arch/x86/cpu/broadwell/Kconfig @@ -9,7 +9,6 @@ config INTEL_BROADWELL select ARCH_EARLY_INIT_R imply HAVE_INTEL_ME imply ENABLE_MRC_CACHE - imply ENV_IS_IN_SPI_FLASH imply AHCI_PCI imply ICH_SPI imply INTEL_BROADWELL_GPIO diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index d4e0587fc5..60eb45f9d0 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -3,7 +3,6 @@ if TARGET_COREBOOT config SYS_COREBOOT bool default y - imply ENV_IS_NOWHERE imply AHCI_PCI imply E1000 imply ICH_SPI diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 00f99d6b11..c214ea0efe 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -10,7 +10,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select CACHE_MRC_BIN if HAVE_MRC imply HAVE_INTEL_ME imply ENABLE_MRC_CACHE - imply ENV_IS_IN_SPI_FLASH imply AHCI_PCI imply ICH_SPI imply INTEL_ICH6_GPIO diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index fdf5ae338e..da378128fe 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -7,7 +7,6 @@ config QEMU bool select ARCH_EARLY_INIT_R - imply ENV_IS_NOWHERE imply AHCI_PCI imply E1000 imply SYS_NS16550 diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig index 7ec46e95ef..0ed724813d 100644 --- a/arch/x86/cpu/quark/Kconfig +++ b/arch/x86/cpu/quark/Kconfig @@ -10,7 +10,6 @@ config INTEL_QUARK select ARCH_EARLY_INIT_R select ARCH_MISC_INIT imply ENABLE_MRC_CACHE - imply ENV_IS_IN_SPI_FLASH imply ETH_DESIGNWARE imply ICH_SPI imply INTEL_ICH6_GPIO diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig index d1b04c952a..835de85268 100644 --- a/arch/x86/cpu/queensbay/Kconfig +++ b/arch/x86/cpu/queensbay/Kconfig @@ -9,7 +9,6 @@ config INTEL_QUEENSBAY select HAVE_FSP select HAVE_CMC select ARCH_EARLY_INIT_R - imply ENV_IS_IN_SPI_FLASH imply AHCI_PCI imply ICH_SPI imply INTEL_ICH6_GPIO diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index aafbeb01f9..00172dc7c1 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -48,15 +48,15 @@ static void build_command_line(char *command_line, int auto_boot) command_line[0] = '\0'; - env_command_line = getenv("bootargs"); + env_command_line = env_get("bootargs"); /* set console= argument if we use a serial console */ if (!strstr(env_command_line, "console=")) { - if (!strcmp(getenv("stdout"), "serial")) { + if (!strcmp(env_get("stdout"), "serial")) { /* We seem to use serial console */ sprintf(command_line, "console=ttyS0,%s ", - getenv("baudrate")); + env_get("baudrate")); } } @@ -285,7 +285,7 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) /* argv[1] holds the address of the bzImage */ s = argv[1]; } else { - s = getenv("fileaddr"); + s = env_get("fileaddr"); } if (s) diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c index 1604bb9536..16961acba5 100644 --- a/arch/xtensa/lib/bootm.c +++ b/arch/xtensa/lib/bootm.c @@ -136,7 +136,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { struct bp_tag *params, *params_start; ulong initrd_start, initrd_end; - char *commandline = getenv("bootargs"); + char *commandline = env_get("bootargs"); if (!(flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO))) return 0; |