diff options
Diffstat (limited to 'arch')
108 files changed, 3914 insertions, 2484 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index e3f9db7b29..aee15d5353 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -116,6 +116,24 @@ config SYS_DCACHE_OFF bool "Do not use Data Cache" default n +menuconfig ARC_DBG + bool "ARC debugging" + default n + +if ARC_DBG + +config ARC_DBG_IOC_ENABLE + bool "Enable IO coherency unit" + depends on CPU_ARCHS38 + default n + help + Enable IO coherency unit to debug problems with caches and + DMA peripherals. + NOTE: as of today linux will not work properly if this option + is enabled in u-boot! + +endif + choice prompt "Target select" default TARGET_AXS103 diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 3ed0c282ba..d040454d1a 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -51,9 +51,10 @@ PLATFORM_CPPFLAGS += -mcpu=archs endif PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 -mno-sdata +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections # Needed for relocation -LDFLAGS_FINAL += -pie +LDFLAGS_FINAL += -pie --gc-sections # Load address for standalone apps CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000 diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi index b74d3c8545..17ef656483 100644 --- a/arch/arc/dts/axs10x_mb.dtsi +++ b/arch/arc/dts/axs10x_mb.dtsi @@ -31,11 +31,8 @@ }; ethernet@18000 { - #interrupt-cells = <1>; compatible = "altr,socfpga-stmmac"; reg = < 0x18000 0x2000 >; - interrupts = < 25 >; - interrupt-names = "macirq"; phy-mode = "gmii"; snps,pbl = < 32 >; clocks = <&apbclk>; @@ -46,13 +43,11 @@ ehci@0x40000 { compatible = "generic-ehci"; reg = < 0x40000 0x100 >; - interrupts = < 8 >; }; ohci@0x60000 { compatible = "generic-ohci"; reg = < 0x60000 0x100 >; - interrupts = < 8 >; }; uart0: serial0@22000 { diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts index 67dfb93ca8..80b864af74 100644 --- a/arch/arc/dts/hsdk.dts +++ b/arch/arc/dts/hsdk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "skeleton.dtsi" +#include "dt-bindings/clock/snps,hsdk-cgu.h" / { #address-cells = <1>; @@ -13,6 +14,7 @@ aliases { console = &uart0; + spi0 = &spi0; }; cpu_card { @@ -24,6 +26,35 @@ }; }; + clk-fmeas { + clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>, + <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>, + <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>, + <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>, + <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>, + <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>, + <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>, + <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>, + <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>, + <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>, + <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>, + <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>, + <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>; + clock-names = "cpu-pll", "sys-pll", + "tun-pll", "ddr-clk", + "cpu-clk", "hdmi-pll", + "tun-clk", "hdmi-clk", + "apb-clk", "axi-clk", + "eth-clk", "usb-clk", + "sdio-clk", "hdmi-sys-clk", + "gfx-core-clk", "gfx-dma-clk", + "gfx-cfg-clk", "dmac-core-clk", + "dmac-cfg-clk", "sdio-ref-clk", + "spi-clk", "i2c-clk", + "uart-clk", "ebi-clk", + "rom-clk", "pwm-clk"; + }; + cgu_clk: cgu-clk@f0000000 { compatible = "snps,hsdk-cgu-clock"; reg = <0xf0000000 0x10>, <0xf00014B8 0x4>; @@ -53,4 +84,29 @@ compatible = "generic-ohci"; reg = <0xf0060000 0x100>; }; + + spi0: spi@f0020000 { + compatible = "snps,dw-apb-ssi"; + reg = <0xf0020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <4000000>; + clocks = <&cgu_clk CLK_SYS_SPI_REF>; + clock-names = "spi_clk"; + cs-gpio = <&cs_gpio 0>; + spi_flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <4000000>; + }; + }; + + cs_gpio: gpio@f00014b0 { + compatible = "snps,hsdk-creg-gpio"; + reg = <0xf00014b0 0x4>; + gpio-controller; + #gpio-cells = <1>; + gpio-bank-name = "hsdk-spi-cs"; + gpio-count = <1>; + }; }; diff --git a/arch/arc/include/asm/arc-bcr.h b/arch/arc/include/asm/arc-bcr.h new file mode 100644 index 0000000000..823906d946 --- /dev/null +++ b/arch/arc/include/asm/arc-bcr.h @@ -0,0 +1,77 @@ +/* + * ARC Build Configuration Registers, with encoded hardware config + * + * Copyright (C) 2018 Synopsys + * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARC_BCR_H +#define __ARC_BCR_H +#ifndef __ASSEMBLY__ + +#include <config.h> + +union bcr_di_cache { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; +#else + unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; +#endif + } fields; + unsigned int word; +}; + +union bcr_slc_cfg { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:24, way:2, lsz:2, sz:4; +#else + unsigned int sz:4, lsz:2, way:2, pad:24; +#endif + } fields; + unsigned int word; +}; + +union bcr_generic { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:24, ver:8; +#else + unsigned int ver:8, pad:24; +#endif + } fields; + unsigned int word; +}; + +union bcr_clust_cfg { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; +#else + unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; +#endif + } fields; + unsigned int word; +}; + +union bcr_mmu_4 { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, + n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; +#else + /* DTLB ITLB JES JE JA */ + unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, + pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; +#endif + } fields; + unsigned int word; +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ARC_BCR_H */ diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 67f416305d..3a513149f5 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -8,6 +8,7 @@ #define _ASM_ARC_ARCREGS_H #include <asm/cache.h> +#include <config.h> /* * ARC architecture has additional address space - auxiliary registers. @@ -88,6 +89,16 @@ /* ARCNUM [15:8] - field to identify each core in a multi-core system */ #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8) + +static const inline int is_isa_arcv2(void) +{ + return IS_ENABLED(CONFIG_ISA_ARCV2); +} + +static const inline int is_isa_arcompact(void) +{ + return IS_ENABLED(CONFIG_ISA_ARCOMPACT); +} #endif /* __ASSEMBLY__ */ #endif /* _ASM_ARC_ARCREGS_H */ diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index d26d9fb18d..2269183615 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -30,6 +30,13 @@ #ifndef __ASSEMBLY__ void cache_init(void); +void flush_n_invalidate_dcache_all(void); +void sync_n_cleanup_cache_all(void); + +static const inline int is_ioc_enabled(void) +{ + return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE); +} #endif /* __ASSEMBLY__ */ diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h index f0242f1ad6..43e1343095 100644 --- a/arch/arc/include/asm/global_data.h +++ b/arch/arc/include/asm/global_data.h @@ -7,9 +7,15 @@ #ifndef __ASM_ARC_GLOBAL_DATA_H #define __ASM_ARC_GLOBAL_DATA_H +#include <config.h> + #ifndef __ASSEMBLY__ /* Architecture-specific global data */ struct arch_global_data { + int l1_line_sz; +#if defined(CONFIG_ISA_ARCV2) + int slc_line_sz; +#endif }; #endif /* __ASSEMBLY__ */ diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index a12303bc73..060cdf637b 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -10,7 +10,7 @@ #include <linux/types.h> #include <asm/byteorder.h> -#ifdef CONFIG_ISA_ARCV2 +#ifdef __ARCHS__ /* * ARCv2 based HS38 cores are in-order issue, but still weakly ordered @@ -42,12 +42,12 @@ #define mb() asm volatile("sync\n" : : : "memory") #endif -#ifdef CONFIG_ISA_ARCV2 +#ifdef __ARCHS__ #define __iormb() rmb() #define __iowmb() wmb() #else -#define __iormb() do { } while (0) -#define __iowmb() do { } while (0) +#define __iormb() asm volatile("" : : : "memory") +#define __iowmb() asm volatile("" : : : "memory") #endif static inline void sync(void) diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h index 909129c333..8b13789179 100644 --- a/arch/arc/include/asm/string.h +++ b/arch/arc/include/asm/string.h @@ -1,27 +1 @@ -/* - * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARC_STRING_H -#define __ASM_ARC_STRING_H - -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMCMP -#define __HAVE_ARCH_STRCHR -#define __HAVE_ARCH_STRCPY -#define __HAVE_ARCH_STRCMP -#define __HAVE_ARCH_STRLEN - -extern void *memset(void *ptr, int, __kernel_size_t); -extern void *memcpy(void *, const void *, __kernel_size_t); -extern void memzero(void *ptr, __kernel_size_t n); -extern int memcmp(const void *, const void *, __kernel_size_t); -extern char *strchr(const char *s, int c); -extern char *strcpy(char *dest, const char *src); -extern int strcmp(const char *cs, const char *ct); -extern __kernel_size_t strlen(const char *); - -#endif /* __ASM_ARC_STRING_H */ diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile index 12097bf3be..6b7fb0fdff 100644 --- a/arch/arc/lib/Makefile +++ b/arch/arc/lib/Makefile @@ -10,13 +10,6 @@ obj-y += cache.o obj-y += cpu.o obj-y += interrupts.o obj-y += relocate.o -obj-y += strchr-700.o -obj-y += strcmp.o -obj-y += strcpy-700.o -obj-y += strlen.o -obj-y += memcmp.o -obj-y += memcpy-700.o -obj-y += memset.o obj-y += reset.o obj-y += ints_low.o obj-y += init_helpers.o diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index 4d4acff239..4f04aad34a 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <asm/cache.h> #include <common.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,41 +41,52 @@ void arch_lmb_reserve(struct lmb *lmb) static int cleanup_before_linux(void) { disable_interrupts(); - flush_dcache_all(); - invalidate_icache_all(); + sync_n_cleanup_cache_all(); return 0; } +__weak int board_prep_linux(bootm_headers_t *images) { return 0; } + /* Subcommand: PREP */ -static void boot_prep_linux(bootm_headers_t *images) +static int boot_prep_linux(bootm_headers_t *images) { - if (image_setup_linux(images)) - hang(); + int ret; + + ret = image_setup_linux(images); + if (ret) + return ret; + + return board_prep_linux(images); } -__weak void smp_set_core_boot_addr(unsigned long addr, int corenr) {} -__weak void smp_kick_all_cpus(void) {} +/* Generic implementation for single core CPU */ +__weak void board_jump_and_run(ulong entry, int zero, int arch, uint params) +{ + void (*kernel_entry)(int zero, int arch, uint params); + + kernel_entry = (void (*)(int, int, uint))entry; + + kernel_entry(zero, arch, params); +} /* Subcommand: GO */ static void boot_jump_linux(bootm_headers_t *images, int flag) { - void (*kernel_entry)(int zero, int arch, uint params); + ulong kernel_entry; unsigned int r0, r2; int fake = (flag & BOOTM_STATE_OS_FAKE_GO); - kernel_entry = (void (*)(int, int, uint))images->ep; + kernel_entry = images->ep; debug("## Transferring control to Linux (at address %08lx)...\n", - (ulong) kernel_entry); + kernel_entry); bootstage_mark(BOOTSTAGE_ID_RUN_OS); printf("\nStarting kernel ...%s\n\n", fake ? "(fake run for tracing)" : ""); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); - cleanup_before_linux(); - if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { r0 = 2; r2 = (unsigned int)images->ft_addr; @@ -83,11 +95,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) r2 = (unsigned int)env_get("bootargs"); } - if (!fake) { - smp_set_core_boot_addr((unsigned long)kernel_entry, -1); - smp_kick_all_cpus(); - kernel_entry(r0, 0, r2); - } + cleanup_before_linux(); + + if (!fake) + board_jump_and_run(kernel_entry, r0, 0, r2); } int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) @@ -96,17 +107,13 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE)) return -1; - if (flag & BOOTM_STATE_OS_PREP) { - boot_prep_linux(images); - return 0; - } + if (flag & BOOTM_STATE_OS_PREP) + return boot_prep_linux(images); if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { boot_jump_linux(images, flag); return 0; } - boot_prep_linux(images); - boot_jump_linux(images, flag); - return 0; + return -1; } diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 04f1d9d59b..8203fae145 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -10,8 +10,145 @@ #include <linux/kernel.h> #include <linux/log2.h> #include <asm/arcregs.h> +#include <asm/arc-bcr.h> #include <asm/cache.h> +/* + * [ NOTE 1 ]: + * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable + * operation may result in unexpected behavior and data loss even if we flush + * data cache right before invalidation. That may happens if we store any context + * on stack (like we store BLINK register on stack before function call). + * BLINK register is the register where return address is automatically saved + * when we do function call with instructions like 'bl'. + * + * There is the real example: + * We may hang in the next code as we store any BLINK register on stack in + * invalidate_dcache_all() function. + * + * void flush_dcache_all() { + * __dc_entire_op(OP_FLUSH); + * // Other code // + * } + * + * void invalidate_dcache_all() { + * __dc_entire_op(OP_INV); + * // Other code // + * } + * + * void foo(void) { + * flush_dcache_all(); + * invalidate_dcache_all(); + * } + * + * Now let's see what really happens during that code execution: + * + * foo() + * |->> call flush_dcache_all + * [return address is saved to BLINK register] + * [push BLINK] (save to stack) ![point 1] + * |->> call __dc_entire_op(OP_FLUSH) + * [return address is saved to BLINK register] + * [flush L1 D$] + * return [jump to BLINK] + * <<------ + * [other flush_dcache_all code] + * [pop BLINK] (get from stack) + * return [jump to BLINK] + * <<------ + * |->> call invalidate_dcache_all + * [return address is saved to BLINK register] + * [push BLINK] (save to stack) ![point 2] + * |->> call __dc_entire_op(OP_FLUSH) + * [return address is saved to BLINK register] + * [invalidate L1 D$] ![point 3] + * // Oops!!! + * // We lose return address from invalidate_dcache_all function: + * // we save it to stack and invalidate L1 D$ after that! + * return [jump to BLINK] + * <<------ + * [other invalidate_dcache_all code] + * [pop BLINK] (get from stack) + * // we don't have this data in L1 dcache as we invalidated it in [point 3] + * // so we get it from next memory level (for example DDR memory) + * // but in the memory we have value which we save in [point 1], which + * // is return address from flush_dcache_all function (instead of + * // address from current invalidate_dcache_all function which we + * // saved in [point 2] !) + * return [jump to BLINK] + * <<------ + * // As BLINK points to invalidate_dcache_all, we call it again and + * // loop forever. + * + * Fortunately we may fix that by using flush & invalidation of D$ with a single + * one instruction (instead of flush and invalidation instructions pair) and + * enabling force function inline with '__attribute__((always_inline))' gcc + * attribute to avoid any function call (and BLINK store) between cache flush + * and disable. + * + * + * [ NOTE 2 ]: + * As of today we only support the following cache configurations on ARC. + * Other configurations may exist in HW (for example, since version 3.0 HS + * supports SL$ (L2 system level cache) disable) but we don't support it in SW. + * Configuration 1: + * ______________________ + * | | + * | ARC CPU | + * |______________________| + * ___|___ ___|___ + * | | | | + * | L1 I$ | | L1 D$ | + * |_______| |_______| + * on/off on/off + * ___|______________|____ + * | | + * | main memory | + * |______________________| + * + * Configuration 2: + * ______________________ + * | | + * | ARC CPU | + * |______________________| + * ___|___ ___|___ + * | | | | + * | L1 I$ | | L1 D$ | + * |_______| |_______| + * on/off on/off + * ___|______________|____ + * | | + * | L2 (SL$) | + * |______________________| + * always must be on + * ___|______________|____ + * | | + * | main memory | + * |______________________| + * + * Configuration 3: + * ______________________ + * | | + * | ARC CPU | + * |______________________| + * ___|___ ___|___ + * | | | | + * | L1 I$ | | L1 D$ | + * |_______| |_______| + * on/off must be on + * ___|______________|____ _______ + * | | | | + * | L2 (SL$) |-----| IOC | + * |______________________| |_______| + * always must be on on/off + * ___|______________|____ + * | | + * | main memory | + * |______________________| + */ + +DECLARE_GLOBAL_DATA_PTR; + /* Bit values in IC_CTRL */ #define IC_CTRL_CACHE_DISABLE BIT(0) @@ -19,11 +156,10 @@ #define DC_CTRL_CACHE_DISABLE BIT(0) #define DC_CTRL_INV_MODE_FLUSH BIT(6) #define DC_CTRL_FLUSH_STATUS BIT(8) -#define CACHE_VER_NUM_MASK 0xF -#define OP_INV 0x1 -#define OP_FLUSH 0x2 -#define OP_INV_IC 0x3 +#define OP_INV BIT(0) +#define OP_FLUSH BIT(1) +#define OP_FLUSH_N_INV (OP_FLUSH | OP_INV) /* Bit val in SLC_CONTROL */ #define SLC_CTRL_DIS 0x001 @@ -31,55 +167,117 @@ #define SLC_CTRL_BUSY 0x100 #define SLC_CTRL_RGN_OP_INV 0x200 +#define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1)) + /* - * By default that variable will fall into .bss section. - * But .bss section is not relocated and so it will be initilized before - * relocation but will be used after being zeroed. + * We don't want to use '__always_inline' macro here as it can be redefined + * to simple 'inline' in some cases which breaks stuff. See [ NOTE 1 ] for more + * details about the reasons we need to use always_inline functions. */ -int l1_line_sz __section(".data"); -bool dcache_exists __section(".data") = false; -bool icache_exists __section(".data") = false; - -#define CACHE_LINE_MASK (~(l1_line_sz - 1)) - -#ifdef CONFIG_ISA_ARCV2 -int slc_line_sz __section(".data"); -bool slc_exists __section(".data") = false; -bool ioc_exists __section(".data") = false; -bool pae_exists __section(".data") = false; +#define inlined_cachefunc inline __attribute__((always_inline)) -/* To force enable IOC set ioc_enable to 'true' */ -bool ioc_enable __section(".data") = false; +static inlined_cachefunc void __ic_entire_invalidate(void); +static inlined_cachefunc void __dc_entire_op(const int cacheop); -void read_decode_mmu_bcr(void) +static inline bool pae_exists(void) { /* TODO: should we compare mmu version from BCR and from CONFIG? */ #if (CONFIG_ARC_MMU_VER >= 4) - u32 tmp; + union bcr_mmu_4 mmu4; - tmp = read_aux_reg(ARC_AUX_MMU_BCR); + mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR); - struct bcr_mmu_4 { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, - n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; -#else - /* DTLB ITLB JES JE JA */ - unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, - pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; -#endif /* CONFIG_CPU_BIG_ENDIAN */ - } *mmu4; + if (mmu4.fields.pae) + return true; +#endif /* (CONFIG_ARC_MMU_VER >= 4) */ - mmu4 = (struct bcr_mmu_4 *)&tmp; + return false; +} - pae_exists = !!mmu4->pae; -#endif /* (CONFIG_ARC_MMU_VER >= 4) */ +static inlined_cachefunc bool icache_exists(void) +{ + union bcr_di_cache ibcr; + + ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); + return !!ibcr.fields.ver; } -static void __slc_entire_op(const int op) +static inlined_cachefunc bool icache_enabled(void) +{ + if (!icache_exists()) + return false; + + return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE); +} + +static inlined_cachefunc bool dcache_exists(void) +{ + union bcr_di_cache dbcr; + + dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); + return !!dbcr.fields.ver; +} + +static inlined_cachefunc bool dcache_enabled(void) +{ + if (!dcache_exists()) + return false; + + return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE); +} + +static inlined_cachefunc bool slc_exists(void) +{ + if (is_isa_arcv2()) { + union bcr_generic sbcr; + + sbcr.word = read_aux_reg(ARC_BCR_SLC); + return !!sbcr.fields.ver; + } + + return false; +} + +static inlined_cachefunc bool slc_data_bypass(void) +{ + /* + * If L1 data cache is disabled SL$ is bypassed and all load/store + * requests are sent directly to main memory. + */ + return !dcache_enabled(); +} + +static inline bool ioc_exists(void) +{ + if (is_isa_arcv2()) { + union bcr_clust_cfg cbcr; + + cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); + return cbcr.fields.c; + } + + return false; +} + +static inline bool ioc_enabled(void) +{ + /* + * We check only CONFIG option instead of IOC HW state check as IOC + * must be disabled by default. + */ + if (is_ioc_enabled()) + return ioc_exists(); + + return false; +} + +static inlined_cachefunc void __slc_entire_op(const int op) { unsigned int ctrl; + if (!slc_exists()) + return; + ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); if (!(op & OP_FLUSH)) /* i.e. OP_INV */ @@ -104,6 +302,14 @@ static void __slc_entire_op(const int op) static void slc_upper_region_init(void) { /* + * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist + * only if PAE exists in current HW. So we had to check pae_exist + * before using them. + */ + if (!pae_exists()) + return; + + /* * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 * as we don't use PAE40. */ @@ -113,9 +319,14 @@ static void slc_upper_region_init(void) static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) { +#ifdef CONFIG_ISA_ARCV2 + unsigned int ctrl; unsigned long end; + if (!slc_exists()) + return; + /* * The Region Flush operation is specified by CTRL.RGN_OP[11..9] * - b'000 (default) is Flush, @@ -142,7 +353,7 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) * END needs to be setup before START (latter triggers the operation) * END can't be same as START, so add (l2_line_sz - 1) to sz */ - end = paddr + sz + slc_line_sz - 1; + end = paddr + sz + gd->arch.slc_line_sz - 1; /* * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) @@ -156,85 +367,82 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) read_aux_reg(ARC_AUX_SLC_CTRL); while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); -} + #endif /* CONFIG_ISA_ARCV2 */ +} + +static void arc_ioc_setup(void) +{ + /* IOC Aperture start is equal to DDR start */ + unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; + /* IOC Aperture size is equal to DDR size */ + long ap_size = CONFIG_SYS_SDRAM_SIZE; + + /* Unsupported configuration. See [ NOTE 2 ] for more details. */ + if (!slc_exists()) + panic("Try to enable IOC but SLC is not present"); + + /* Unsupported configuration. See [ NOTE 2 ] for more details. */ + if (!dcache_enabled()) + panic("Try to enable IOC but L1 D$ is disabled"); + + if (!is_power_of_2(ap_size) || ap_size < 4096) + panic("IOC Aperture size must be power of 2 and bigger 4Kib"); + + /* IOC Aperture start must be aligned to the size of the aperture */ + if (ap_base % ap_size != 0) + panic("IOC Aperture start must be aligned to the size of the aperture"); + + flush_n_invalidate_dcache_all(); + + /* + * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, + * so setting 0x11 implies 512M, 0x12 implies 1G... + */ + write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, + order_base_2(ap_size / 1024) - 2); + + write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); + write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); + write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); +} -#ifdef CONFIG_ISA_ARCV2 static void read_decode_cache_bcr_arcv2(void) { - union { - struct { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:24, way:2, lsz:2, sz:4; -#else - unsigned int sz:4, lsz:2, way:2, pad:24; -#endif - } fields; - unsigned int word; - } slc_cfg; - - union { - struct { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:24, ver:8; -#else - unsigned int ver:8, pad:24; -#endif - } fields; - unsigned int word; - } sbcr; +#ifdef CONFIG_ISA_ARCV2 - sbcr.word = read_aux_reg(ARC_BCR_SLC); - if (sbcr.fields.ver) { + union bcr_slc_cfg slc_cfg; + + if (slc_exists()) { slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); - slc_exists = true; - slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; - } + gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; - union { - struct bcr_clust_cfg { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; -#else - unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; -#endif - } fields; - unsigned int word; - } cbcr; + /* + * We don't support configuration where L1 I$ or L1 D$ is + * absent but SL$ exists. See [ NOTE 2 ] for more details. + */ + if (!icache_exists() || !dcache_exists()) + panic("Unsupported cache configuration: SLC exists but one of L1 caches is absent"); + } - cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); - if (cbcr.fields.c && ioc_enable) - ioc_exists = true; +#endif /* CONFIG_ISA_ARCV2 */ } -#endif void read_decode_cache_bcr(void) { int dc_line_sz = 0, ic_line_sz = 0; - - union { - struct { -#ifdef CONFIG_CPU_BIG_ENDIAN - unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; -#else - unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; -#endif - } fields; - unsigned int word; - } ibcr, dbcr; + union bcr_di_cache ibcr, dbcr; ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); if (ibcr.fields.ver) { - icache_exists = true; - l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; + gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; if (!ic_line_sz) panic("Instruction exists but line length is 0\n"); } dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); if (dbcr.fields.ver) { - dcache_exists = true; - l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; + gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; if (!dc_line_sz) panic("Data cache exists but line length is 0\n"); } @@ -247,109 +455,79 @@ void cache_init(void) { read_decode_cache_bcr(); -#ifdef CONFIG_ISA_ARCV2 - read_decode_cache_bcr_arcv2(); - - if (ioc_exists) { - /* IOC Aperture start is equal to DDR start */ - unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; - /* IOC Aperture size is equal to DDR size */ - long ap_size = CONFIG_SYS_SDRAM_SIZE; - - flush_dcache_all(); - invalidate_dcache_all(); + if (is_isa_arcv2()) + read_decode_cache_bcr_arcv2(); - if (!is_power_of_2(ap_size) || ap_size < 4096) - panic("IOC Aperture size must be power of 2 and bigger 4Kib"); - - /* - * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB, - * so setting 0x11 implies 512M, 0x12 implies 1G... - */ - write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, - order_base_2(ap_size / 1024) - 2); - - /* IOC Aperture start must be aligned to the size of the aperture */ - if (ap_base % ap_size != 0) - panic("IOC Aperture start must be aligned to the size of the aperture"); - - write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); - write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); - write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); - } + if (is_isa_arcv2() && ioc_enabled()) + arc_ioc_setup(); - read_decode_mmu_bcr(); - - /* - * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist - * only if PAE exists in current HW. So we had to check pae_exist - * before using them. - */ - if (slc_exists && pae_exists) + if (is_isa_arcv2() && slc_exists()) slc_upper_region_init(); -#endif /* CONFIG_ISA_ARCV2 */ } int icache_status(void) { - if (!icache_exists) - return 0; - - if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) - return 0; - else - return 1; + return icache_enabled(); } void icache_enable(void) { - if (icache_exists) + if (icache_exists()) write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & ~IC_CTRL_CACHE_DISABLE); } void icache_disable(void) { - if (icache_exists) - write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | - IC_CTRL_CACHE_DISABLE); + if (!icache_exists()) + return; + + __ic_entire_invalidate(); + + write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | + IC_CTRL_CACHE_DISABLE); } -void invalidate_icache_all(void) +/* IC supports only invalidation */ +static inlined_cachefunc void __ic_entire_invalidate(void) { + if (!icache_enabled()) + return; + /* Any write to IC_IVIC register triggers invalidation of entire I$ */ - if (icache_status()) { - write_aux_reg(ARC_AUX_IC_IVIC, 1); - /* - * As per ARC HS databook (see chapter 5.3.3.2) - * it is required to add 3 NOPs after each write to IC_IVIC. - */ - __builtin_arc_nop(); - __builtin_arc_nop(); - __builtin_arc_nop(); - read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ - } + write_aux_reg(ARC_AUX_IC_IVIC, 1); + /* + * As per ARC HS databook (see chapter 5.3.3.2) + * it is required to add 3 NOPs after each write to IC_IVIC. + */ + __builtin_arc_nop(); + __builtin_arc_nop(); + __builtin_arc_nop(); + read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ +} -#ifdef CONFIG_ISA_ARCV2 - if (slc_exists) +void invalidate_icache_all(void) +{ + __ic_entire_invalidate(); + + /* + * If SL$ is bypassed for data it is used only for instructions, + * so we need to invalidate it too. + * TODO: HS 3.0 supports SLC disable so we need to check slc + * enable/disable status here. + */ + if (is_isa_arcv2() && slc_data_bypass()) __slc_entire_op(OP_INV); -#endif } int dcache_status(void) { - if (!dcache_exists) - return 0; - - if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) - return 0; - else - return 1; + return dcache_enabled(); } void dcache_enable(void) { - if (!dcache_exists) + if (!dcache_exists()) return; write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & @@ -358,83 +536,77 @@ void dcache_enable(void) void dcache_disable(void) { - if (!dcache_exists) + if (!dcache_exists()) return; + __dc_entire_op(OP_FLUSH_N_INV); + + /* + * As SLC will be bypassed for data after L1 D$ disable we need to + * flush it first before L1 D$ disable. Also we invalidate SLC to + * avoid any inconsistent data problems after enabling L1 D$ again with + * dcache_enable function. + */ + if (is_isa_arcv2()) + __slc_entire_op(OP_FLUSH_N_INV); + write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | DC_CTRL_CACHE_DISABLE); } -#ifndef CONFIG_SYS_DCACHE_OFF -/* - * Common Helper for Line Operations on {I,D}-Cache - */ -static inline void __cache_line_loop(unsigned long paddr, unsigned long sz, - const int cacheop) +/* Common Helper for Line Operations on D-cache */ +static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, + const int cacheop) { unsigned int aux_cmd; -#if (CONFIG_ARC_MMU_VER == 3) - unsigned int aux_tag; -#endif int num_lines; - if (cacheop == OP_INV_IC) { - aux_cmd = ARC_AUX_IC_IVIL; -#if (CONFIG_ARC_MMU_VER == 3) - aux_tag = ARC_AUX_IC_PTAG; -#endif - } else { - /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ - aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; -#if (CONFIG_ARC_MMU_VER == 3) - aux_tag = ARC_AUX_DC_PTAG; -#endif - } + /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ + aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL; sz += paddr & ~CACHE_LINE_MASK; paddr &= CACHE_LINE_MASK; - num_lines = DIV_ROUND_UP(sz, l1_line_sz); + num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz); while (num_lines-- > 0) { #if (CONFIG_ARC_MMU_VER == 3) - write_aux_reg(aux_tag, paddr); + write_aux_reg(ARC_AUX_DC_PTAG, paddr); #endif write_aux_reg(aux_cmd, paddr); - paddr += l1_line_sz; + paddr += gd->arch.l1_line_sz; } } -static unsigned int __before_dc_op(const int op) +static inlined_cachefunc void __before_dc_op(const int op) { - unsigned int reg; + unsigned int ctrl; - if (op == OP_INV) { - /* - * IM is set by default and implies Flush-n-inv - * Clear it here for vanilla inv - */ - reg = read_aux_reg(ARC_AUX_DC_CTRL); - write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH); - } + ctrl = read_aux_reg(ARC_AUX_DC_CTRL); - return reg; + /* IM bit implies flush-n-inv, instead of vanilla inv */ + if (op == OP_INV) + ctrl &= ~DC_CTRL_INV_MODE_FLUSH; + else + ctrl |= DC_CTRL_INV_MODE_FLUSH; + + write_aux_reg(ARC_AUX_DC_CTRL, ctrl); } -static void __after_dc_op(const int op, unsigned int reg) +static inlined_cachefunc void __after_dc_op(const int op) { if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); - - /* Switch back to default Invalidate mode */ - if (op == OP_INV) - write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH); } -static inline void __dc_entire_op(const int cacheop) +static inlined_cachefunc void __dc_entire_op(const int cacheop) { int aux; - unsigned int ctrl_reg = __before_dc_op(cacheop); + + if (!dcache_enabled()) + return; + + __before_dc_op(cacheop); if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ aux = ARC_AUX_DC_IVDC; @@ -443,36 +615,36 @@ static inline void __dc_entire_op(const int cacheop) write_aux_reg(aux, 0x1); - __after_dc_op(cacheop, ctrl_reg); + __after_dc_op(cacheop); } static inline void __dc_line_op(unsigned long paddr, unsigned long sz, const int cacheop) { - unsigned int ctrl_reg = __before_dc_op(cacheop); + if (!dcache_enabled()) + return; - __cache_line_loop(paddr, sz, cacheop); - __after_dc_op(cacheop, ctrl_reg); + __before_dc_op(cacheop); + __dcache_line_loop(paddr, sz, cacheop); + __after_dc_op(cacheop); } -#else -#define __dc_entire_op(cacheop) -#define __dc_line_op(paddr, sz, cacheop) -#endif /* !CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_range(unsigned long start, unsigned long end) { if (start >= end) return; -#ifdef CONFIG_ISA_ARCV2 - if (!ioc_exists) -#endif + /* + * ARCv1 -> call __dc_line_op + * ARCv2 && L1 D$ disabled -> nothing + * ARCv2 && L1 D$ enabled && IOC enabled -> nothing + * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op + */ + if (!is_isa_arcv2() || !ioc_enabled()) __dc_line_op(start, end - start, OP_INV); -#ifdef CONFIG_ISA_ARCV2 - if (slc_exists && !ioc_exists) + if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass()) __slc_rgn_op(start, end - start, OP_INV); -#endif } void flush_dcache_range(unsigned long start, unsigned long end) @@ -480,15 +652,17 @@ void flush_dcache_range(unsigned long start, unsigned long end) if (start >= end) return; -#ifdef CONFIG_ISA_ARCV2 - if (!ioc_exists) -#endif + /* + * ARCv1 -> call __dc_line_op + * ARCv2 && L1 D$ disabled -> nothing + * ARCv2 && L1 D$ enabled && IOC enabled -> nothing + * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op + */ + if (!is_isa_arcv2() || !ioc_enabled()) __dc_line_op(start, end - start, OP_FLUSH); -#ifdef CONFIG_ISA_ARCV2 - if (slc_exists && !ioc_exists) + if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass()) __slc_rgn_op(start, end - start, OP_FLUSH); -#endif } void flush_cache(unsigned long start, unsigned long size) @@ -496,22 +670,47 @@ void flush_cache(unsigned long start, unsigned long size) flush_dcache_range(start, start + size); } -void invalidate_dcache_all(void) +/* + * As invalidate_dcache_all() is not used in generic U-Boot code and as we + * don't need it in arch/arc code alone (invalidate without flush) we implement + * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because + * it's much safer. See [ NOTE 1 ] for more details. + */ +void flush_n_invalidate_dcache_all(void) { - __dc_entire_op(OP_INV); + __dc_entire_op(OP_FLUSH_N_INV); -#ifdef CONFIG_ISA_ARCV2 - if (slc_exists) - __slc_entire_op(OP_INV); -#endif + if (is_isa_arcv2() && !slc_data_bypass()) + __slc_entire_op(OP_FLUSH_N_INV); } void flush_dcache_all(void) { __dc_entire_op(OP_FLUSH); -#ifdef CONFIG_ISA_ARCV2 - if (slc_exists) + if (is_isa_arcv2() && !slc_data_bypass()) __slc_entire_op(OP_FLUSH); -#endif +} + +/* + * This is function to cleanup all caches (and therefore sync I/D caches) which + * can be used for cleanup before linux launch or to sync caches during + * relocation. + */ +void sync_n_cleanup_cache_all(void) +{ + __dc_entire_op(OP_FLUSH_N_INV); + + /* + * If SL$ is bypassed for data it is used only for instructions, + * and we shouldn't flush it. So invalidate it instead of flush_n_inv. + */ + if (is_isa_arcv2()) { + if (slc_data_bypass()) + __slc_entire_op(OP_INV); + else + __slc_entire_op(OP_FLUSH_N_INV); + } + + __ic_entire_invalidate(); } diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c index dbc8d68ffb..435fe96ef4 100644 --- a/arch/arc/lib/init_helpers.c +++ b/arch/arc/lib/init_helpers.c @@ -4,14 +4,14 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <asm/cache.h> #include <common.h> DECLARE_GLOBAL_DATA_PTR; int init_cache_f_r(void) { -#ifndef CONFIG_SYS_DCACHE_OFF - flush_dcache_all(); -#endif + sync_n_cleanup_cache_all(); + return 0; } diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S deleted file mode 100644 index 87bccab51d..0000000000 --- a/arch/arc/lib/memcmp.S +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifdef __LITTLE_ENDIAN__ -#define WORD2 r2 -#define SHIFT r3 -#else /* __BIG_ENDIAN__ */ -#define WORD2 r3 -#define SHIFT r2 -#endif /* _ENDIAN__ */ - -.global memcmp -.align 4 -memcmp: - or %r12, %r0, %r1 - asl_s %r12, %r12, 30 - sub %r3, %r2, 1 - brls %r2, %r12, .Lbytewise - ld %r4, [%r0, 0] - ld %r5, [%r1, 0] - lsr.f %lp_count, %r3, 3 - lpne .Loop_end - ld_s WORD2, [%r0, 4] - ld_s %r12, [%r1, 4] - brne %r4, %r5, .Leven - ld.a %r4, [%r0, 8] - ld.a %r5, [%r1, 8] - brne WORD2, %r12, .Lodd - nop -.Loop_end: - asl_s SHIFT, SHIFT, 3 - bhs_s .Last_cmp - brne %r4, %r5, .Leven - ld %r4, [%r0, 4] - ld %r5, [%r1, 4] -#ifdef __LITTLE_ENDIAN__ - nop_s - /* one more load latency cycle */ -.Last_cmp: - xor %r0, %r4, %r5 - bset %r0, %r0, SHIFT - sub_s %r1, %r0, 1 - bic_s %r1, %r1, %r0 - norm %r1, %r1 - b.d .Leven_cmp - and %r1, %r1, 24 -.Leven: - xor %r0, %r4, %r5 - sub_s %r1, %r0, 1 - bic_s %r1, %r1, %r0 - norm %r1, %r1 - /* slow track insn */ - and %r1, %r1, 24 -.Leven_cmp: - asl %r2, %r4, %r1 - asl %r12, %r5, %r1 - lsr_s %r2, %r2, 1 - lsr_s %r12, %r12, 1 - j_s.d [%blink] - sub %r0, %r2, %r12 - .balign 4 -.Lodd: - xor %r0, WORD2, %r12 - sub_s %r1, %r0, 1 - bic_s %r1, %r1, %r0 - norm %r1, %r1 - /* slow track insn */ - and %r1, %r1, 24 - asl_s %r2, %r2, %r1 - asl_s %r12, %r12, %r1 - lsr_s %r2, %r2, 1 - lsr_s %r12, %r12, 1 - j_s.d [%blink] - sub %r0, %r2, %r12 -#else /* __BIG_ENDIAN__ */ -.Last_cmp: - neg_s SHIFT, SHIFT - lsr %r4, %r4, SHIFT - lsr %r5, %r5, SHIFT - /* slow track insn */ -.Leven: - sub.f %r0, %r4, %r5 - mov.ne %r0, 1 - j_s.d [%blink] - bset.cs %r0, %r0, 31 -.Lodd: - cmp_s WORD2, %r12 - - mov_s %r0, 1 - j_s.d [%blink] - bset.cs %r0, %r0, 31 -#endif /* _ENDIAN__ */ - .balign 4 -.Lbytewise: - breq %r2, 0, .Lnil - ldb %r4, [%r0, 0] - ldb %r5, [%r1, 0] - lsr.f %lp_count, %r3 - lpne .Lbyte_end - ldb_s %r3, [%r0, 1] - ldb %r12, [%r1, 1] - brne %r4, %r5, .Lbyte_even - ldb.a %r4, [%r0, 2] - ldb.a %r5, [%r1, 2] - brne %r3, %r12, .Lbyte_odd - nop -.Lbyte_end: - bcc .Lbyte_even - brne %r4, %r5, .Lbyte_even - ldb_s %r3, [%r0, 1] - ldb_s %r12, [%r1, 1] -.Lbyte_odd: - j_s.d [%blink] - sub %r0, %r3, %r12 -.Lbyte_even: - j_s.d [%blink] - sub %r0, %r4, %r5 -.Lnil: - j_s.d [%blink] - mov %r0, 0 diff --git a/arch/arc/lib/memcpy-700.S b/arch/arc/lib/memcpy-700.S deleted file mode 100644 index 51dd73ab8f..0000000000 --- a/arch/arc/lib/memcpy-700.S +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.global memcpy -.align 4 -memcpy: - or %r3, %r0, %r1 - asl_s %r3, %r3, 30 - mov_s %r5, %r0 - brls.d %r2, %r3, .Lcopy_bytewise - sub.f %r3, %r2, 1 - ld_s %r12, [%r1, 0] - asr.f %lp_count, %r3, 3 - bbit0.d %r3, 2, .Lnox4 - bmsk_s %r2, %r2, 1 - st.ab %r12, [%r5, 4] - ld.a %r12, [%r1, 4] -.Lnox4: - lppnz .Lendloop - ld_s %r3, [%r1, 4] - st.ab %r12, [%r5, 4] - ld.a %r12, [%r1, 8] - st.ab %r3, [%r5, 4] -.Lendloop: - breq %r2, 0, .Last_store - ld %r3, [%r5, 0] -#ifdef __LITTLE_ENDIAN__ - add3 %r2, -1, %r2 - /* uses long immediate */ - xor_s %r12, %r12, %r3 - bmsk %r12, %r12, %r2 - xor_s %r12, %r12, %r3 -#else /* __BIG_ENDIAN__ */ - sub3 %r2, 31, %r2 - /* uses long immediate */ - xor_s %r3, %r3, %r12 - bmsk %r3, %r3, %r2 - xor_s %r12, %r12, %r3 -#endif /* _ENDIAN__ */ -.Last_store: - j_s.d [%blink] - st %r12, [%r5, 0] - - .balign 4 -.Lcopy_bytewise: - jcs [%blink] - ldb_s %r12, [%r1, 0] - lsr.f %lp_count, %r3 - bhs_s .Lnox1 - stb.ab %r12, [%r5, 1] - ldb.a %r12, [%r1, 1] -.Lnox1: - lppnz .Lendbloop - ldb_s %r3, [%r1, 1] - stb.ab %r12, [%r5, 1] - ldb.a %r12, [%r1, 2] - stb.ab %r3, [%r5, 1] -.Lendbloop: - j_s.d [%blink] - stb %r12, [%r5, 0] diff --git a/arch/arc/lib/memset.S b/arch/arc/lib/memset.S deleted file mode 100644 index 017e8af0e8..0000000000 --- a/arch/arc/lib/memset.S +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SMALL 7 /* Must be at least 6 to deal with alignment/loop issues. */ - -.global memset -.align 4 -memset: - mov_s %r4, %r0 - or %r12, %r0, %r2 - bmsk.f %r12, %r12, 1 - extb_s %r1, %r1 - asl %r3, %r1, 8 - beq.d .Laligned - or_s %r1, %r1, %r3 - brls %r2, SMALL, .Ltiny - add %r3, %r2, %r0 - stb %r1, [%r3, -1] - bclr_s %r3, %r3, 0 - stw %r1, [%r3, -2] - bmsk.f %r12, %r0, 1 - add_s %r2, %r2, %r12 - sub.ne %r2, %r2, 4 - stb.ab %r1, [%r4, 1] - and %r4, %r4, -2 - stw.ab %r1, [%r4, 2] - and %r4, %r4, -4 - - .balign 4 -.Laligned: - asl %r3, %r1, 16 - lsr.f %lp_count, %r2, 2 - or_s %r1, %r1, %r3 - lpne .Loop_end - st.ab %r1, [%r4, 4] -.Loop_end: - j_s [%blink] - - .balign 4 -.Ltiny: - mov.f %lp_count, %r2 - lpne .Ltiny_end - stb.ab %r1, [%r4, 1] -.Ltiny_end: - j_s [%blink] - -/* - * memzero: @r0 = mem, @r1 = size_t - * memset: @r0 = mem, @r1 = char, @r2 = size_t - */ - -.global memzero -.align 4 -memzero: - /* adjust bzero args to memset args */ - mov %r2, %r1 - mov %r1, 0 - /* tail call so need to tinker with blink */ - b memset diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c index 7802f40545..96b4bd3d8f 100644 --- a/arch/arc/lib/relocate.c +++ b/arch/arc/lib/relocate.c @@ -17,6 +17,9 @@ int copy_uboot_to_ram(void) { size_t len = (size_t)&__image_copy_end - (size_t)&__image_copy_start; + if (gd->flags & GD_FLG_SKIP_RELOC) + return 0; + memcpy((void *)gd->relocaddr, (void *)&__image_copy_start, len); return 0; @@ -40,6 +43,9 @@ int do_elf_reloc_fixups(void) Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start); Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end); + if (gd->flags & GD_FLG_SKIP_RELOC) + return 0; + debug("Section .rela.dyn is located at %08x-%08x\n", (unsigned int)re_src, (unsigned int)re_end); diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 0d72fe71d4..c78dd001d8 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -10,26 +10,6 @@ #include <asm/arcregs.h> ENTRY(_start) -; ARCompact devices are not supposed to be SMP so master/slave check -; makes no sense. -#ifdef CONFIG_ISA_ARCV2 - ; Non-masters will be halted immediately, they might be kicked later - ; by platform code right before passing control to the Linux kernel - ; in bootm.c:boot_jump_linux(). - lr r5, [identity] - lsr r5, r5, 8 - bmsk r5, r5, 7 - cmp r5, 0 - mov.nz r0, r5 - bz .Lmaster_proceed - flag 1 - nop - nop - nop - -.Lmaster_proceed: -#endif - /* Setup interrupt vector base that matches "__text_start" */ sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] @@ -98,7 +78,13 @@ ENTRY(_start) /* Zero the one and only argument of "board_init_f" */ mov_s %r0, 0 - j board_init_f + bl board_init_f + + /* We only get here if relocation is disabled by GD_FLG_SKIP_RELOC */ + /* Make sure we don't lose GD overwritten by zero new GD */ + mov %r0, %r25 + mov %r1, 0 + bl board_init_r ENDPROC(_start) /* diff --git a/arch/arc/lib/strchr-700.S b/arch/arc/lib/strchr-700.S deleted file mode 100644 index 55fcc9fb00..0000000000 --- a/arch/arc/lib/strchr-700.S +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * ARC700 has a relatively long pipeline and branch prediction, so we want - * to avoid branches that are hard to predict. On the other hand, the - * presence of the norm instruction makes it easier to operate on whole - * words branch-free. - */ - -.global strchr -.align 4 -strchr: - extb_s %r1, %r1 - asl %r5, %r1, 8 - bmsk %r2, %r0, 1 - or %r5, %r5, %r1 - mov_s %r3, 0x01010101 - breq.d %r2, %r0, .Laligned - asl %r4, %r5, 16 - sub_s %r0, %r0, %r2 - asl %r7, %r2, 3 - ld_s %r2, [%r0] -#ifdef __LITTLE_ENDIAN__ - asl %r7, %r3, %r7 -#else /* __BIG_ENDIAN__ */ - lsr %r7, %r3, %r7 -#endif /* _ENDIAN__ */ - or %r5, %r5, %r4 - ror %r4, %r3 - sub %r12, %r2, %r7 - bic_s %r12, %r12, %r2 - and %r12, %r12, %r4 - brne.d %r12, 0, .Lfound0_ua - xor %r6, %r2, %r5 - ld.a %r2, [%r0, 4] - sub %r12, %r6, %r7 - bic %r12, %r12, %r6 -#ifdef __LITTLE_ENDIAN__ - and %r7, %r12, %r4 - /* For speed, we want this branch to be unaligned. */ - breq %r7, 0, .Loop - /* Likewise this one */ - b .Lfound_char -#else /* __BIG_ENDIAN__ */ - and %r12, %r12, %r4 - /* For speed, we want this branch to be unaligned. */ - breq %r12, 0, .Loop - lsr_s %r12, %r12, 7 - bic %r2, %r7, %r6 - b.d .Lfound_char_b - and_s %r2, %r2, %r12 -#endif /* _ENDIAN__ */ - /* We require this code address to be unaligned for speed... */ -.Laligned: - ld_s %r2, [%r0] - or %r5, %r5, %r4 - ror %r4, %r3 - /* ... so that this code address is aligned, for itself and ... */ -.Loop: - sub %r12, %r2, %r3 - bic_s %r12, %r12, %r2 - and %r12, %r12, %r4 - brne.d %r12, 0, .Lfound0 - xor %r6, %r2, %r5 - ld.a %r2, [%r0, 4] - sub %r12, %r6, %r3 - bic %r12, %r12, %r6 - and %r7, %r12, %r4 - breq %r7, 0, .Loop - /* - *... so that this branch is unaligned. - * Found searched-for character. - * r0 has already advanced to next word. - */ -#ifdef __LITTLE_ENDIAN__ - /* - * We only need the information about the first matching byte - * (i.e. the least significant matching byte) to be exact, - * hence there is no problem with carry effects. - */ -.Lfound_char: - sub %r3, %r7, 1 - bic %r3, %r3, %r7 - norm %r2, %r3 - sub_s %r0, %r0, 1 - asr_s %r2, %r2, 3 - j.d [%blink] - sub_s %r0, %r0, %r2 - - .balign 4 -.Lfound0_ua: - mov %r3, %r7 -.Lfound0: - sub %r3, %r6, %r3 - bic %r3, %r3, %r6 - and %r2, %r3, %r4 - or_s %r12, %r12, %r2 - sub_s %r3, %r12, 1 - bic_s %r3, %r3, %r12 - norm %r3, %r3 - add_s %r0, %r0, 3 - asr_s %r12, %r3, 3 - asl.f 0, %r2, %r3 - sub_s %r0, %r0, %r12 - j_s.d [%blink] - mov.pl %r0, 0 -#else /* __BIG_ENDIAN__ */ -.Lfound_char: - lsr %r7, %r7, 7 - - bic %r2, %r7, %r6 -.Lfound_char_b: - norm %r2, %r2 - sub_s %r0, %r0, 4 - asr_s %r2, %r2, 3 - j.d [%blink] - add_s %r0, %r0, %r2 - -.Lfound0_ua: - mov_s %r3, %r7 -.Lfound0: - asl_s %r2, %r2, 7 - or %r7, %r6, %r4 - bic_s %r12, %r12, %r2 - sub %r2, %r7, %r3 - or %r2, %r2, %r6 - bic %r12, %r2, %r12 - bic.f %r3, %r4, %r12 - norm %r3, %r3 - - add.pl %r3, %r3, 1 - asr_s %r12, %r3, 3 - asl.f 0, %r2, %r3 - add_s %r0, %r0, %r12 - j_s.d [%blink] - mov.mi %r0, 0 -#endif /* _ENDIAN__ */ diff --git a/arch/arc/lib/strcmp.S b/arch/arc/lib/strcmp.S deleted file mode 100644 index 8cb7d2f18c..0000000000 --- a/arch/arc/lib/strcmp.S +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This is optimized primarily for the ARC700. - * It would be possible to speed up the loops by one cycle / word - * respective one cycle / byte by forcing double source 1 alignment, unrolling - * by a factor of two, and speculatively loading the second word / byte of - * source 1; however, that would increase the overhead for loop setup / finish, - * and strcmp might often terminate early. - */ - -.global strcmp -.align 4 -strcmp: - or %r2, %r0, %r1 - bmsk_s %r2, %r2, 1 - brne %r2, 0, .Lcharloop - mov_s %r12, 0x01010101 - ror %r5, %r12 -.Lwordloop: - ld.ab %r2, [%r0, 4] - ld.ab %r3, [%r1, 4] - nop_s - sub %r4, %r2, %r12 - bic %r4, %r4, %r2 - and %r4, %r4, %r5 - brne %r4, 0, .Lfound0 - breq %r2 ,%r3, .Lwordloop -#ifdef __LITTLE_ENDIAN__ - xor %r0, %r2, %r3 /* mask for difference */ - sub_s %r1, %r0, 1 - bic_s %r0, %r0, %r1 /* mask for least significant difference bit */ - sub %r1, %r5, %r0 - xor %r0, %r5, %r1 /* mask for least significant difference byte */ - and_s %r2, %r2, %r0 - and_s %r3, %r3, %r0 -#endif /* _ENDIAN__ */ - cmp_s %r2, %r3 - mov_s %r0, 1 - j_s.d [%blink] - bset.lo %r0, %r0, 31 - - .balign 4 -#ifdef __LITTLE_ENDIAN__ -.Lfound0: - xor %r0, %r2, %r3 /* mask for difference */ - or %r0, %r0, %r4 /* or in zero indicator */ - sub_s %r1, %r0, 1 - bic_s %r0, %r0, %r1 /* mask for least significant difference bit */ - sub %r1, %r5, %r0 - xor %r0, %r5, %r1 /* mask for least significant difference byte */ - and_s %r2, %r2, %r0 - and_s %r3, %r3, %r0 - sub.f %r0, %r2, %r3 - mov.hi %r0, 1 - j_s.d [%blink] - bset.lo %r0, %r0, 31 -#else /* __BIG_ENDIAN__ */ - /* - * The zero-detection above can mis-detect 0x01 bytes as zeroes - * because of carry-propagateion from a lower significant zero byte. - * We can compensate for this by checking that bit0 is zero. - * This compensation is not necessary in the step where we - * get a low estimate for r2, because in any affected bytes - * we already have 0x00 or 0x01, which will remain unchanged - * when bit 7 is cleared. - */ - .balign 4 -.Lfound0: - lsr %r0, %r4, 8 - lsr_s %r1, %r2 - bic_s %r2, %r2, %r0 /* get low estimate for r2 and get ... */ - bic_s %r0, %r0, %r1 /* <this is the adjusted mask for zeros> */ - or_s %r3, %r3, %r0 /* ... high estimate r3 so that r2 > r3 will */ - cmp_s %r3, %r2 /* ... be independent of trailing garbage */ - or_s %r2, %r2, %r0 /* likewise for r3 > r2 */ - bic_s %r3, %r3, %r0 - rlc %r0, 0 /* r0 := r2 > r3 ? 1 : 0 */ - cmp_s %r2, %r3 - j_s.d [%blink] - bset.lo %r0, %r0, 31 -#endif /* _ENDIAN__ */ - - .balign 4 -.Lcharloop: - ldb.ab %r2,[%r0,1] - ldb.ab %r3,[%r1,1] - nop_s - breq %r2, 0, .Lcmpend - breq %r2, %r3, .Lcharloop -.Lcmpend: - j_s.d [%blink] - sub %r0, %r2, %r3 diff --git a/arch/arc/lib/strcpy-700.S b/arch/arc/lib/strcpy-700.S deleted file mode 100644 index 41bb53e501..0000000000 --- a/arch/arc/lib/strcpy-700.S +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * If dst and src are 4 byte aligned, copy 8 bytes at a time. - * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get - * it 8 byte aligned. Thus, we can do a little read-ahead, without - * dereferencing a cache line that we should not touch. - * Note that short and long instructions have been scheduled to avoid - * branch stalls. - * The beq_s to r3z could be made unaligned & long to avoid a stall - * there, but it is not likely to be taken often, and it would also be likely - * to cost an unaligned mispredict at the next call. - */ - -.global strcpy -.align 4 -strcpy: - or %r2, %r0, %r1 - bmsk_s %r2, %r2, 1 - brne.d %r2, 0, charloop - mov_s %r10, %r0 - ld_s %r3, [%r1, 0] - mov %r8, 0x01010101 - bbit0.d %r1, 2, loop_start - ror %r12, %r8 - sub %r2, %r3, %r8 - bic_s %r2, %r2, %r3 - tst_s %r2,%r12 - bne r3z - mov_s %r4,%r3 - .balign 4 -loop: - ld.a %r3, [%r1, 4] - st.ab %r4, [%r10, 4] -loop_start: - ld.a %r4, [%r1, 4] - sub %r2, %r3, %r8 - bic_s %r2, %r2, %r3 - tst_s %r2, %r12 - bne_s r3z - st.ab %r3, [%r10, 4] - sub %r2, %r4, %r8 - bic %r2, %r2, %r4 - tst %r2, %r12 - beq loop - mov_s %r3, %r4 -#ifdef __LITTLE_ENDIAN__ -r3z: bmsk.f %r1, %r3, 7 - lsr_s %r3, %r3, 8 -#else /* __BIG_ENDIAN__ */ -r3z: lsr.f %r1, %r3, 24 - asl_s %r3, %r3, 8 -#endif /* _ENDIAN__ */ - bne.d r3z - stb.ab %r1, [%r10, 1] - j_s [%blink] - - .balign 4 -charloop: - ldb.ab %r3, [%r1, 1] - brne.d %r3, 0, charloop - stb.ab %r3, [%r10, 1] - j [%blink] diff --git a/arch/arc/lib/strlen.S b/arch/arc/lib/strlen.S deleted file mode 100644 index 666e22c0d5..0000000000 --- a/arch/arc/lib/strlen.S +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.global strlen -.align 4 -strlen: - or %r3, %r0, 7 - ld %r2, [%r3, -7] - ld.a %r6, [%r3, -3] - mov %r4, 0x01010101 - /* uses long immediate */ -#ifdef __LITTLE_ENDIAN__ - asl_s %r1, %r0, 3 - btst_s %r0, 2 - asl %r7, %r4, %r1 - ror %r5, %r4 - sub %r1, %r2, %r7 - bic_s %r1, %r1, %r2 - mov.eq %r7, %r4 - sub %r12, %r6, %r7 - bic %r12, %r12, %r6 - or.eq %r12, %r12, %r1 - and %r12, %r12, %r5 - brne %r12, 0, .Learly_end -#else /* __BIG_ENDIAN__ */ - ror %r5, %r4 - btst_s %r0, 2 - mov_s %r1, 31 - sub3 %r7, %r1, %r0 - sub %r1, %r2, %r4 - bic_s %r1, %r1, %r2 - bmsk %r1, %r1, %r7 - sub %r12, %r6, %r4 - bic %r12, %r12, %r6 - bmsk.ne %r12, %r12, %r7 - or.eq %r12, %r12, %r1 - and %r12, %r12, %r5 - brne %r12, 0, .Learly_end -#endif /* _ENDIAN__ */ - -.Loop: - ld_s %r2, [%r3, 4] - ld.a %r6, [%r3, 8] - /* stall for load result */ - sub %r1, %r2, %r4 - bic_s %r1, %r1, %r2 - sub %r12, %r6, %r4 - bic %r12, %r12, %r6 - or %r12, %r12, %r1 - and %r12, %r12, %r5 - breq %r12, 0, .Loop -.Lend: - and.f %r1, %r1, %r5 - sub.ne %r3, %r3, 4 - mov.eq %r1, %r12 -#ifdef __LITTLE_ENDIAN__ - sub_s %r2, %r1, 1 - bic_s %r2, %r2, %r1 - norm %r1, %r2 - sub_s %r0, %r0, 3 - lsr_s %r1, %r1, 3 - sub %r0, %r3, %r0 - j_s.d [%blink] - sub %r0, %r0, %r1 -#else /* __BIG_ENDIAN__ */ - lsr_s %r1, %r1, 7 - mov.eq %r2, %r6 - bic_s %r1, %r1, %r2 - norm %r1, %r1 - sub %r0, %r3, %r0 - lsr_s %r1, %r1, 3 - j_s.d [%blink] - add %r0, %r0, %r1 -#endif /* _ENDIAN */ -.Learly_end: - b.d .Lend - sub_s.ne %r1, %r1, %r1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 95553bee9d..068ea1e877 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -762,6 +762,7 @@ config ARCH_ZYNQ select SUPPORT_SPL select OF_CONTROL select SPL_BOARD_INIT if SPL + select BOARD_EARLY_INIT_F if WDT select SPL_OF_CONTROL if SPL select DM select DM_ETH if NET @@ -1132,7 +1133,7 @@ config ARCH_UNIPHIER (formerly, System LSI Business Division of Panasonic Corporation) config STM32 - bool "Support STM32" + bool "Support STMicroelectronics STM32 MCU with cortex M" select CPU_V7M select DM select DM_SERIAL @@ -1150,6 +1151,27 @@ config ARCH_STI Support for STMicroelectronics STiH407/10 SoC family. This SoC is used on Linaro 96Board STiH410-B2260 +config ARCH_STM32MP + bool "Support STMicroelectronics STM32MP Socs with cortex A" + select BOARD_LATE_INIT + select CLK + select DM + select DM_GPIO + select DM_RESET + select DM_SERIAL + select OF_CONTROL + select OF_LIBFDT + select PINCTRL + select REGMAP + select SUPPORT_SPL + select SYSCON + select SYS_THUMB_BUILD + help + Support for STM32MP SoC family developed by STMicroelectronics, + MPUs based on ARM cortex A core + U-BOOT is running in DDR and SPL support is the unsecure First Stage + BootLoader (FSBL) + config ARCH_ROCKCHIP bool "Support Rockchip SoCs" select OF_CONTROL @@ -1262,6 +1284,8 @@ source "arch/arm/mach-sti/Kconfig" source "arch/arm/mach-stm32/Kconfig" +source "arch/arm/mach-stm32mp/Kconfig" + source "arch/arm/mach-sunxi/Kconfig" source "arch/arm/mach-tegra/Kconfig" @@ -1336,6 +1360,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" +source "board/xilinx/zynqmp/Kconfig" source "board/zipitz2/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5881fdc8e2..4fa8b38397 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -72,6 +72,7 @@ machine-$(CONFIG_ARCH_SOCFPGA) += socfpga machine-$(CONFIG_ARCH_RMOBILE) += rmobile machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_STM32) += stm32 +machine-$(CONFIG_ARCH_STM32MP) += stm32mp machine-$(CONFIG_TEGRA) += tegra machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_ZYNQ) += zynq diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index 30915d28aa..545c518506 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -17,7 +17,7 @@ int timer_init(void) gd->arch.tbl = 0; gd->arch.tbu = 0; - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ; + gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; return 0; } @@ -34,27 +34,9 @@ unsigned long long get_ticks(void) } -ulong get_timer(ulong base) -{ - return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base; -} - ulong timer_get_boot_us(void) { - return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000)); -} - -void __udelay(unsigned long usec) -{ - unsigned long long endtime; - - endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz, - 1000UL); - - endtime += get_ticks(); - - while (get_ticks() < endtime) - ; + return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / 1000000); } ulong get_tbclk(void) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index b9f837d58d..18fb937a3a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -612,6 +612,29 @@ int setup_chip_volt(void) return 0; } +#ifdef CONFIG_FSL_PFE +void init_pfe_scfg_dcfg_regs(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 ecccr2; + + out_be32(&scfg->pfeasbcr, + in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0); + out_be32(&scfg->pfebsbcr, + in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0); + + /* CCI-400 QoS settings for PFE */ + out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS + | SCFG_WR_QOS1_PFE2_QOS)); + out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS + | SCFG_RD_QOS1_PFE2_QOS)); + + ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); + out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, + ecccr2 | (unsigned int)DISABLE_PFE_ECC); +} +#endif + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index bc77dd03c3..14e7d40064 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -185,7 +185,7 @@ void zynqmp_pmufw_version(void) pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT, pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK); - if (pm_api_version != ZYNQMP_PM_VERSION) + if (pm_api_version < ZYNQMP_PM_VERSION) panic("PMUFW version error. Expected: v%d.%d\n", ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR); } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 83e13ec915..e983622fea 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -146,7 +146,6 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zturn-myir.dtb \ zynq-zybo.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ - zynqmp-ep108.dtb \ zynqmp-mini-emmc.dtb \ zynqmp-mini-nand.dtb \ zynqmp-zcu102-revA.dtb \ @@ -500,6 +499,9 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb +dtb-$(CONFIG_TARGET_STM32MP1) += \ + stm32mp157c-ed1.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts index 5f06252e4e..770c08aa7d 100644 --- a/arch/arm/dts/armada-3720-db.dts +++ b/arch/arm/dts/armada-3720-db.dts @@ -82,7 +82,7 @@ ð0 { pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; + pinctrl-0 = <&rgmii_pins>, <&smi_pins>; status = "okay"; phy-mode = "rgmii"; }; @@ -100,6 +100,8 @@ &sdhci0 { bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; status = "okay"; }; @@ -109,6 +111,8 @@ mmc-ddr-1_8v; mmc-hs400-1_8v; marvell,pad-type = "fixed-1-8v"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; status = "okay"; #address-cells = <1>; @@ -150,3 +154,11 @@ &usb3 { status = "okay"; }; + +/* CON17 */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts index aa6587af66..7bfccb0435 100644 --- a/arch/arm/dts/armada-3720-espressobin.dts +++ b/arch/arm/dts/armada-3720-espressobin.dts @@ -89,6 +89,8 @@ ð0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&smi_pins>; phy-mode = "rgmii"; phy_addr = <0x1>; fixed-link { @@ -98,6 +100,8 @@ }; &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; @@ -108,6 +112,8 @@ &spi0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_quad_pins>; spi-flash@0 { #address-cells = <1>; @@ -121,6 +127,8 @@ /* Exported on the micro USB connector CON32 through an FTDI */ &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; status = "okay"; }; @@ -133,3 +141,10 @@ &usb3 { status = "okay"; }; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + reset-gpio = <&gpiosb 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index 690234234b..54007428ed 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -46,6 +46,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/comphy/comphy_data.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Marvell Armada 37xx SoC"; @@ -154,6 +155,11 @@ groups = "uart2"; function = "uart"; }; + + mmc_pins: mmc-pins { + groups = "emmc_nb"; + function = "emmc"; + }; }; pinctrl_sb: pinctrl-sb@18800 { @@ -162,7 +168,7 @@ reg = <0x18800 0x100>, <0x18C00 0x20>; gpiosb: gpiosb { #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 29>; + gpio-ranges = <&pinctrl_sb 0 0 30>; gpio-controller; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, @@ -177,6 +183,20 @@ function = "mii"; }; + smi_pins: smi-pins { + groups = "smi"; + function = "smi"; + }; + + sdio_pins: sdio-pins { + groups = "sdio_sb"; + function = "sdio"; + }; + + pcie_pins: pcie-pins { + groups = "pcie1"; + function = "gpio"; + }; }; usb3: usb@58000 { @@ -266,20 +286,6 @@ status = "disabled"; }; - pinctl0: pinctl@13830 { /* north bridge */ - compatible = "marvell,armada-3700-pinctl"; - bank-name = "armada-3700-nb"; - reg = <0x13830 0x4>; - pin-count = <36>; - }; - - pinctl1: pinctl@18830 { /* south bridge */ - compatible = "marvell,armada-3700-pinctl"; - bank-name = "armada-3700-sb"; - reg = <0x18830 0x4>; - pin-count = <30>; - }; - comphy: comphy@18300 { compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; reg = <0x18300 0x28>, @@ -288,5 +294,21 @@ max-lanes = <2>; }; }; + + pcie0: pcie@d0070000 { + compatible = "marvell,armada-37xx-pcie"; + reg = <0 0xd0070000 0 0x20000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + status = "disabled"; + + bus-range = <0 0xff>; + ranges = <0x82000000 0 0xe8000000 + 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ + 0x81000000 0 0xe9000000 + 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ + }; }; }; diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi new file mode 100644 index 0000000000..c67c3ddbf7 --- /dev/null +++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi @@ -0,0 +1,13 @@ +/* + * da850-lcdk U-Boot Additions + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + aliases { + i2c0 = &i2c0; + }; +}; diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts new file mode 100644 index 0000000000..a1f4d6d5a5 --- /dev/null +++ b/arch/arm/dts/da850-lcdk.dts @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2016 BayLibre, Inc. + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "da850.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "DA850/AM1808/OMAP-L138 LCDK"; + compatible = "ti,da850-lcdk", "ti,da850"; + + aliases { + serial2 = &serial2; + ethernet0 = ð0; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0xc0000000 0x08000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dsp_memory_region: dsp-memory@c3000000 { + compatible = "shared-dma-pool"; + reg = <0xc3000000 0x1000000>; + reusable; + status = "okay"; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "DA850/OMAP-L138 LCDK"; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out"; + simple-audio-card,routing = + "LINE1L", "Line In", + "LINE1R", "Line In", + "Line Out", "LLOUT", + "Line Out", "RLOUT"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + system-clock-frequency = <24576000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24576000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + user1 { + label = "GPIO Key USER1"; + linux,code = <BTN_0>; + gpios = <&gpio 36 GPIO_ACTIVE_LOW>; + }; + + user2 { + label = "GPIO Key USER2"; + linux,code = <BTN_1>; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + }; + }; + + vga-bridge { + compatible = "ti,ths8135"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&lcdc_out_vga>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + ddc-i2c-bus = <&i2c0>; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; +}; + +&pmx_core { + status = "okay"; + + mcasp0_pins: pinmux_mcasp0_pins { + pinctrl-single,bits = < + /* AHCLKX AFSX ACLKX */ + 0x00 0x00101010 0x00f0f0f0 + /* ARX13 ARX14 */ + 0x04 0x00000110 0x00000ff0 + >; + }; + + nand_pins: nand_pins { + pinctrl-single,bits = < + /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ + 0x1c 0x10110010 0xf0ff00f0 + /* + * EMA_D[0], EMA_D[1], EMA_D[2], + * EMA_D[3], EMA_D[4], EMA_D[5], + * EMA_D[6], EMA_D[7] + */ + 0x24 0x11111111 0xffffffff + /* + * EMA_D[8], EMA_D[9], EMA_D[10], + * EMA_D[11], EMA_D[12], EMA_D[13], + * EMA_D[14], EMA_D[15] + */ + 0x20 0x11111111 0xffffffff + /* EMA_A[1], EMA_A[2] */ + 0x30 0x01100000 0x0ff00000 + >; + }; +}; + +&serial2 { + pinctrl-names = "default"; + pinctrl-0 = <&serial2_rxtx_pins>; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&rtc0 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + bus_freq = <2200000>; + status = "okay"; +}; + +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&mii_pins>; + status = "okay"; +}; + +&mmc0 { + max-frequency = <50000000>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + tlv320aic3106: tlv320aic3106@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x18>; + status = "okay"; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + + op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 1 2 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&usb_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&aemif { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>; + status = "okay"; + cs3 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <3>; + + nand@2000000,0 { + compatible = "ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x02000000 0x02000000 + 1 0x00000000 0x00008000>; + + ti,davinci-chipselect = <1>; + ti,davinci-mask-ale = <0>; + ti,davinci-mask-cle = <0>; + ti,davinci-mask-chipsel = <0>; + + ti,davinci-nand-buswidth = <16>; + ti,davinci-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + ti,davinci-nand-use-bbt; + + /* + * The OMAP-L132/L138 Bootloader doc SPRAB41E reads: + * "To boot from NAND Flash, the AIS should be written + * to NAND block 1 (NAND block 0 is not used by default)". + * The same doc mentions that for ROM "Silicon Revision 2.1", + * "Updated NAND boot mode to offer boot from block 0 or block 1". + * However the limitaion is left here by default for compatibility + * with older silicon and because it needs new boot pin settings + * not possible in stock LCDK. + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot env"; + reg = <0 0x020000>; + }; + partition@20000 { + /* The LCDK defaults to booting from this partition */ + label = "u-boot"; + reg = <0x020000 0x080000>; + }; + partition@a0000 { + label = "free space"; + reg = <0x0a0000 0>; + }; + }; + }; + }; +}; + +&prictrl { + status = "okay"; +}; + +&memctrl { + status = "okay"; +}; + +&lcdc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + port { + lcdc_out_vga: endpoint { + remote-endpoint = <&vga_bridge_in>; + }; + }; +}; + +&vpif { + pinctrl-names = "default"; + pinctrl-0 = <&vpif_capture_pins>; + status = "okay"; +}; + +&dsp { + memory-region = <&dsp_memory_region>; + status = "okay"; +}; diff --git a/arch/arm/dts/da850.dtsi b/arch/arm/dts/da850.dtsi index 02e2f8f258..c66cf78953 100644 --- a/arch/arm/dts/da850.dtsi +++ b/arch/arm/dts/da850.dtsi @@ -23,11 +23,18 @@ reg = <0xfffee000 0x2000>; }; }; - - aliases { - spi0 = &spi0; + dsp: dsp@11800000 { + compatible = "ti,da850-dsp"; + reg = <0x11800000 0x40000>, + <0x11e00000 0x8000>, + <0x11f00000 0x8000>, + <0x01c14044 0x4>, + <0x01c14174 0x8>; + reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; + interrupt-parent = <&intc>; + interrupts = <28>; + status = "disabled"; }; - soc@1c00000 { compatible = "simple-bus"; model = "da850"; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts index 225c7c53c7..02000fcba8 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dts +++ b/arch/arm/dts/fsl-ls1088a-qds.dts @@ -19,6 +19,43 @@ }; }; +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0 0 0x5 0x80000000 0x08000000 + 2 0 0x5 0x30000000 0x00010000 + 3 0 0x5 0x20000000 0x00010000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@2,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1 0x0 0x10000>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus", "fsl,ls1088aqds-fpga", + "fsl,fpga-qixis"; + reg = <0x2 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 2 0 0x100>; + }; +}; + &dspi { bus-num = <0>; status = "okay"; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index f8f8654e15..b4a42cf5d0 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -75,6 +75,11 @@ reg-names = "QuadSPI", "QuadSPI-memory"; num-cs = <4>; }; + ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x2240000 0x0 0x20000>; + interrupts = <0 21 0x4>; /* Level high type */ + }; usb0: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 9e8d2a045c..e47f762e54 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -89,6 +89,37 @@ compatible = "st,button1"; button-gpio = <&gpioi 11 0>; }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiok 3 0>; + status = "okay"; + }; + + panel-rgb@0 { + compatible = "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpioi 12 0>; + status = "okay"; + + display-timings { + timing@0 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <2>; + hback-porch = <2>; + hsync-len = <41>; + vfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + }; }; &clk_hse { @@ -183,6 +214,40 @@ slew-rate = <2>; }; }; + + ltdc_pins: ltdc@0 { + pins { + pinmux = <STM32F746_PE4_FUNC_LCD_B0>, + <STM32F746_PG12_FUNC_LCD_B4>, + <STM32F746_PI9_FUNC_LCD_VSYNC>, + <STM32F746_PI10_FUNC_LCD_HSYNC>, + <STM32F746_PI14_FUNC_LCD_CLK>, + <STM32F746_PI15_FUNC_LCD_R0>, + <STM32F746_PJ0_FUNC_LCD_R1>, + <STM32F746_PJ1_FUNC_LCD_R2>, + <STM32F746_PJ2_FUNC_LCD_R3>, + <STM32F746_PJ3_FUNC_LCD_R4>, + <STM32F746_PJ4_FUNC_LCD_R5>, + <STM32F746_PJ5_FUNC_LCD_R6>, + <STM32F746_PJ6_FUNC_LCD_R7>, + <STM32F746_PJ7_FUNC_LCD_G0>, + <STM32F746_PJ8_FUNC_LCD_G1>, + <STM32F746_PJ9_FUNC_LCD_G2>, + <STM32F746_PJ10_FUNC_LCD_G3>, + <STM32F746_PJ11_FUNC_LCD_G4>, + <STM32F746_PJ13_FUNC_LCD_B1>, + <STM32F746_PJ14_FUNC_LCD_B2>, + <STM32F746_PJ15_FUNC_LCD_B3>, + <STM32F746_PK0_FUNC_LCD_G5>, + <STM32F746_PK1_FUNC_LCD_G6>, + <STM32F746_PK2_FUNC_LCD_G7>, + <STM32F746_PK4_FUNC_LCD_B5>, + <STM32F746_PK5_FUNC_LCD_B6>, + <STM32F746_PK6_FUNC_LCD_B7>, + <STM32F746_PK7_FUNC_LCD_DE>; + slew-rate = <2>; + }; + }; }; &usart1 { @@ -250,3 +315,8 @@ bus-width = <4>; max-frequency = <25000000>; }; + +<dc { + status = "okay"; + pinctrl-0 = <<dc_pins>; +}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 8c6fa133e0..8581df9a27 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -330,6 +330,15 @@ interrupts = <50>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; + + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x200>; + resets = <&rcc STM32F7_APB2_RESET(LTDC)>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; + u-boot,dm-pre-reloc; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi new file mode 100644 index 0000000000..ddfa0794d9 --- /dev/null +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -0,0 +1,155 @@ +/* + * Copyright : STMicroelectronics 2018 + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +/ { + soc { + ddr: ddr@0x5A003000{ + u-boot,dm-pre-reloc; + + compatible = "st,stm32mp1-ddr"; + + reg = <0x5A003000 0x550 + 0x5A004000 0x234>; + + clocks = <&rcc_clk AXIDCG>, + <&rcc_clk DDRC1>, + <&rcc_clk DDRC2>, + <&rcc_clk DDRPHYC>, + <&rcc_clk DDRCAPB>, + <&rcc_clk DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrc2", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + + st,mem-name = DDR_MEM_NAME; + st,mem-speed = <DDR_MEM_SPEED>; + st,mem-size = <DDR_MEM_SIZE>; + + st,ctl-reg = < + DDR_MSTR + DDR_MRCTRL0 + DDR_MRCTRL1 + DDR_DERATEEN + DDR_DERATEINT + DDR_PWRCTL + DDR_PWRTMG + DDR_HWLPCTL + DDR_RFSHCTL0 + DDR_RFSHCTL3 + DDR_CRCPARCTL0 + DDR_ZQCTL0 + DDR_DFITMG0 + DDR_DFITMG1 + DDR_DFILPCFG0 + DDR_DFIUPD0 + DDR_DFIUPD1 + DDR_DFIUPD2 + DDR_DFIPHYMSTR + DDR_ODTMAP + DDR_DBG0 + DDR_DBG1 + DDR_DBGCMD + DDR_POISONCFG + DDR_PCCFG + >; + + st,ctl-timing = < + DDR_RFSHTMG + DDR_DRAMTMG0 + DDR_DRAMTMG1 + DDR_DRAMTMG2 + DDR_DRAMTMG3 + DDR_DRAMTMG4 + DDR_DRAMTMG5 + DDR_DRAMTMG6 + DDR_DRAMTMG7 + DDR_DRAMTMG8 + DDR_DRAMTMG14 + DDR_ODTCFG + >; + + st,ctl-map = < + DDR_ADDRMAP1 + DDR_ADDRMAP2 + DDR_ADDRMAP3 + DDR_ADDRMAP4 + DDR_ADDRMAP5 + DDR_ADDRMAP6 + DDR_ADDRMAP9 + DDR_ADDRMAP10 + DDR_ADDRMAP11 + >; + + st,ctl-perf = < + DDR_SCHED + DDR_SCHED1 + DDR_PERFHPR1 + DDR_PERFLPR1 + DDR_PERFWR1 + DDR_PCFGR_0 + DDR_PCFGW_0 + DDR_PCFGQOS0_0 + DDR_PCFGQOS1_0 + DDR_PCFGWQOS0_0 + DDR_PCFGWQOS1_0 + DDR_PCFGR_1 + DDR_PCFGW_1 + DDR_PCFGQOS0_1 + DDR_PCFGQOS1_1 + DDR_PCFGWQOS0_1 + DDR_PCFGWQOS1_1 + >; + + st,phy-reg = < + DDR_PGCR + DDR_ACIOCR + DDR_DXCCR + DDR_DSGCR + DDR_DCR + DDR_ODTCR + DDR_ZQ0CR1 + DDR_DX0GCR + DDR_DX1GCR + DDR_DX2GCR + DDR_DX3GCR + >; + + st,phy-timing = < + DDR_PTR0 + DDR_PTR1 + DDR_PTR2 + DDR_DTPR0 + DDR_DTPR1 + DDR_DTPR2 + DDR_MR0 + DDR_MR1 + DDR_MR2 + DDR_MR3 + >; + + st,phy-cal = < + DDR_DX0DLLCR + DDR_DX0DQTR + DDR_DX0DQSTR + DDR_DX1DLLCR + DDR_DX1DQTR + DDR_DX1DQSTR + DDR_DX2DLLCR + DDR_DX2DQTR + DDR_DX2DQSTR + DDR_DX3DLLCR + DDR_DX3DQTR + DDR_DX3DQSTR + >; + + status = "okay"; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi new file mode 100644 index 0000000000..352e470fa9 --- /dev/null +++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +/* STM32MP157C ED1 and ED2 BOARD configuration + * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used NT5CC256M16DP-DI from NANYA + * + * DDR type / Platform DDR3/3L + * freq 533MHz + * width 32 + * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G + * DDR density 8 + * timing mode optimized + * Scheduling/QoS options : type = 2 + * address mapping : RBC + */ + +#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36" +#define DDR_MEM_SPEED 533 +#define DDR_MEM_SIZE 0x40000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041C +#define DDR_DRAMTMG2 0x0608090F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x08040608 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02060105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x0F070707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00001201 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x01000001 +#define DDR_PERFLPR1 0x08000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00010000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x02100B03 +#define DDR_PCFGQOS1_0 0x00800100 +#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PCFGR_1 0x00010000 +#define DDR_PCFGW_1 0x00000000 +#define DDR_PCFGQOS0_1 0x02100B03 +#define DDR_PCFGQOS1_1 0x00800100 +#define DDR_PCFGWQOS0_1 0x01100B03 +#define DDR_PCFGWQOS1_1 0x01000200 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200001F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x38D488D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000840 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x0000005B +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX0DLLCR 0x40000000 +#define DDR_DX0DQTR 0xFFFFFFFF +#define DDR_DX0DQSTR 0x3DB02000 +#define DDR_DX1GCR 0x0000CE81 +#define DDR_DX1DLLCR 0x40000000 +#define DDR_DX1DQTR 0xFFFFFFFF +#define DDR_DX1DQSTR 0x3DB02000 +#define DDR_DX2GCR 0x0000CE81 +#define DDR_DX2DLLCR 0x40000000 +#define DDR_DX2DQTR 0xFFFFFFFF +#define DDR_DX2DQSTR 0x3DB02000 +#define DDR_DX3GCR 0x0000CE81 +#define DDR_DX3DLLCR 0x40000000 +#define DDR_DX3DQTR 0xFFFFFFFF +#define DDR_DX3DQSTR 0x3DB02000 + +#include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi new file mode 100644 index 0000000000..d374b2bc08 --- /dev/null +++ b/arch/arm/dts/stm32mp157-u-boot.dtsi @@ -0,0 +1,134 @@ +/* + * Copyright : STMicroelectronics 2018 + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + gpio25 = &gpioz; + }; + + config { + u-boot,dm-pre-reloc; + }; + + clocks { + u-boot,dm-pre-reloc; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&clk_hsi { + u-boot,dm-pre-reloc; +}; + +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&clk_lse { + u-boot,dm-pre-reloc; +}; + +&clk_lsi { + u-boot,dm-pre-reloc; +}; + +&clk_csi { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&rcc_clk { + u-boot,dm-pre-reloc; +}; + +&rcc_rst { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pinctrl_z { + u-boot,dm-pre-reloc; +}; + +&gpioa { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiob { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioc { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiod { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioe { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiof { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiog { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioh { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioi { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioj { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiok { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioz { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi new file mode 100644 index 0000000000..32d3984259 --- /dev/null +++ b/arch/arm/dts/stm32mp157.dtsi @@ -0,0 +1,303 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/stm32mp1-clks.h> +#include <dt-bindings/reset-controller/stm32mp1-resets.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + aliases { + serial3 = &uart4; + }; + + intc: interrupt-controller@a0021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xa0021000 0x1000>, + <0xa0022000 0x2000>; + }; + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: clk-csi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + clocks = <&rcc_clk UART4_K>; + status = "disabled"; + }; + + rcc: rcc@50000000 { + compatible = "syscon", "simple-mfd"; + + reg = <0x50000000 0x1000>; + + rcc_clk: rcc-clk@50000000 { + #clock-cells = <1>; + compatible = "st,stm32mp1-rcc-clk"; + }; + + rcc_rst: rcc-reset@50000000 { + #reset-cells = <1>; + compatible = "st,stm32mp1-rcc-rst"; + }; + }; + + pinctrl: pin-controller { + compatible = "st,stm32mp157-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50002000 0xa400>; + pins-are-numbered; + + gpioa: gpio@50002000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc_clk GPIOA>; + st,bank-name = "GPIOA"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + status = "disabled"; + }; + + gpiob: gpio@50003000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc_clk GPIOB>; + st,bank-name = "GPIOB"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + status = "disabled"; + }; + + gpioc: gpio@50004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc_clk GPIOC>; + st,bank-name = "GPIOC"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + status = "disabled"; + }; + + gpiod: gpio@50005000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x400>; + clocks = <&rcc_clk GPIOD>; + st,bank-name = "GPIOD"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + status = "disabled"; + }; + + gpioe: gpio@50006000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x400>; + clocks = <&rcc_clk GPIOE>; + st,bank-name = "GPIOE"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + status = "disabled"; + }; + + gpiof: gpio@50007000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x400>; + clocks = <&rcc_clk GPIOF>; + st,bank-name = "GPIOF"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + status = "disabled"; + }; + + gpiog: gpio@50008000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x400>; + clocks = <&rcc_clk GPIOG>; + st,bank-name = "GPIOG"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + status = "disabled"; + }; + + gpioh: gpio@50009000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x400>; + clocks = <&rcc_clk GPIOH>; + st,bank-name = "GPIOH"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 112 16>; + status = "disabled"; + }; + + gpioi: gpio@5000a000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x400>; + clocks = <&rcc_clk GPIOI>; + st,bank-name = "GPIOI"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + status = "disabled"; + }; + + gpioj: gpio@5000b000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x9000 0x400>; + clocks = <&rcc_clk GPIOJ>; + st,bank-name = "GPIOJ"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + status = "disabled"; + }; + + gpiok: gpio@5000c000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa000 0x400>; + clocks = <&rcc_clk GPIOK>; + st,bank-name = "GPIOK"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + status = "disabled"; + }; + }; + + pinctrl_z: pin-controller-z { + compatible = "st,stm32mp157-z-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x54004000 0x400>; + pins-are-numbered; + + gpioz: gpio@54004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&rcc_clk GPIOZ>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + ngpios = <8>; + gpio-ranges = <&pinctrl_z 0 400 8>; + status = "disabled"; + }; + }; + + sdmmc1: sdmmc@58005000 { + compatible = "st,stm32-sdmmc2"; + reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + reg-names = "sdmmc", "delay"; + clocks = <&rcc_clk SDMMC1_K>; + resets = <&rcc_rst SDMMC1_R>; + st,idma = <1>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + i2c4: i2c@5c002000 { + compatible = "st,stm32f7-i2c"; + reg = <0x5c002000 0x400>; + interrupt-names = "event", "error", "wakeup"; + clocks = <&rcc_clk I2C4_K>; + resets = <&rcc_rst I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi new file mode 100644 index 0000000000..94d27fb398 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -0,0 +1,133 @@ +/* + * Copyright : STMicroelectronics 2018 + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#include <dt-bindings/clock/stm32mp1-clksrc.h> +#include "stm32mp157-u-boot.dtsi" +#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" + +/ { + aliases { + mmc0 = &sdmmc1; + i2c3 = &i2c4; + }; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; +}; + +&i2c4_pins_a { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&i2c4 { + u-boot,dm-pre-reloc; +}; + +&pmic { + u-boot,dm-pre-reloc; +}; + +/* CLOCK init */ +&rcc_clk { + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + + st,pkcs = < + CLK_CKPER_DISABLED + CLK_SDMMC12_PLL3R + CLK_I2C46_PCLK5 + CLK_I2C12_PCLK1 + CLK_I2C35_PCLK1 + CLK_UART1_PCLK5 + CLK_UART24_PCLK1 + CLK_UART35_PCLK1 + CLK_UART6_PCLK2 + CLK_UART78_PCLK1 + >; + + /* VCO = 1300.0 MHz => P = 650 (CPU) */ + pll1: st,pll@0 { + cfg = < 2 80 0 0 0 PQR(1,0,0) >; + frac = < 0x800 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ + pll2: st,pll@1 { + cfg = < 2 65 1 0 0 PQR(1,1,1) >; + frac = < 0x1400 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */ + pll3: st,pll@2 { + cfg = < 3 128 3 20 7 PQR(1,1,1) >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */ + pll4: st,pll@3 { + cfg = < 5 126 8 8 8 PQR(1,1,1) >; + u-boot,dm-pre-reloc; + }; +}; + +/* SPL part **************************************/ +/* MMC1 boot */ +&sdmmc1_b4_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&sdmmc1_dir_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&sdmmc1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts new file mode 100644 index 0000000000..4b20fabb71 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +/ { + model = "STMicroelectronics STM32MP157C pmic eval daughter"; + compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; + + chosen { + bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram"; + stdout-path = "serial3:115200n8"; + }; + + memory { + reg = <0xC0000000 0x40000000>; + }; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&gpiog { + status = "okay"; +}; + +&gpioh { + status = "okay"; +}; + +&gpioi { + status = "okay"; +}; + +&gpioj { + status = "okay"; +}; + +&gpiok { + status = "okay"; +}; + +&gpioz { + status = "okay"; +}; + +&pinctrl { + uart4_pins_a: uart4@0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4@0 { + pins { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir@0 { + pins { + pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */ + <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + slew-rate = <3>; + drive-push-pull; + bias-pull-up; + }; + }; +}; + +&pinctrl_z { + i2c4_pins_a: i2c4@0 { + pins { + pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ + <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic: stpmu1@33 { + compatible = "st,stpmu1"; + reg = <0x33>; + interrupts = <0 2>; + interrupt-parent = <&gpioa>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + broken-cd; + st,dirpol; + st,negedge; + st,pin-ckin; + bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index d342306293..a88a83c166 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -333,3 +333,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; + +&watchdog0 { + reset-on-timeout; +}; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi new file mode 100644 index 0000000000..4449d5b93d --- /dev/null +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -0,0 +1,290 @@ +/* + * Clock specification for Xilinx ZynqMP + * + * (C) Copyright 2017, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + fclk0: fclk0 { + status = "disabled"; + compatible = "xlnx,fclk"; + clocks = <&clkc 71>; + }; + + fclk1: fclk1 { + status = "disabled"; + compatible = "xlnx,fclk"; + clocks = <&clkc 72>; + }; + + fclk2: fclk2 { + status = "disabled"; + compatible = "xlnx,fclk"; + clocks = <&clkc 73>; + }; + + fclk3: fclk3 { + status = "disabled"; + compatible = "xlnx,fclk"; + clocks = <&clkc 74>; + }; + + pss_ref_clk: pss_ref_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33333333>; + }; + + video_clk: video_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + pss_alt_ref_clk: pss_alt_ref_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + gt_crx_ref_clk: gt_crx_ref_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <108000000>; + }; + + aux_ref_clk: aux_ref_clk { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clkc: clkc { + u-boot,dm-pre-reloc; + #clock-cells = <1>; + compatible = "xlnx,zynqmp-clkc"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; + clock-output-names = "iopll", "rpll", "apll", "dpll", + "vpll", "iopll_to_fpd", "rpll_to_fpd", + "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd", + "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", + "dbg_trace", "dbg_tstmp", "dp_video_ref", + "dp_audio_ref", "dp_stc_ref", "gdma_ref", + "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", + "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref", + "topsw_main", "topsw_lsbus", "gtgref0_ref", + "lpd_switch", "lpd_lsbus", "usb0_bus_ref", + "usb1_bus_ref", "usb3_dual_ref", "usb0", + "usb1", "cpu_r5", "cpu_r5_core", "csu_spb", + "csu_pll", "pcap", "iou_switch", "gem_tsu_ref", + "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", + "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", + "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", + "uart0_ref", "uart1_ref", "spi0_ref", + "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", + "can0_ref", "can1_ref", "can0", "can1", + "dll_ref", "adma_ref", "timestamp_ref", + "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"; + }; + + dp_aclk: dp_aclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-accuracy = <100>; + }; +}; + +&can0 { + clocks = <&clkc 63>, <&clkc 31>; +}; + +&can1 { + clocks = <&clkc 64>, <&clkc 31>; +}; + +&cpu0 { + clocks = <&clkc 10>; +}; + +&fpd_dma_chan1 { + clocks = <&clkc 19>, <&clkc 31>; +}; + +&fpd_dma_chan2 { + clocks = <&clkc 19>, <&clkc 31>; +}; + +&fpd_dma_chan3 { + clocks = <&clkc 19>, <&clkc 31>; +}; + +&fpd_dma_chan4 { + clocks = <&clkc 19>, <&clkc 31>; +}; + +&fpd_dma_chan5 { + clocks = <&clkc 19>, <&clkc 31>; +}; + +&fpd_dma_chan6 { + clocks = <&clkc 19>, <&clkc 31>; +}; + +&fpd_dma_chan7 { + clocks = <&clkc 19>, <&clkc 31>; +}; + +&fpd_dma_chan8 { + clocks = <&clkc 19>, <&clkc 31>; +}; + +&gpu { + clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>; +}; + +&lpd_dma_chan1 { + clocks = <&clkc 68>, <&clkc 31>; +}; + +&lpd_dma_chan2 { + clocks = <&clkc 68>, <&clkc 31>; +}; + +&lpd_dma_chan3 { + clocks = <&clkc 68>, <&clkc 31>; +}; + +&lpd_dma_chan4 { + clocks = <&clkc 68>, <&clkc 31>; +}; + +&lpd_dma_chan5 { + clocks = <&clkc 68>, <&clkc 31>; +}; + +&lpd_dma_chan6 { + clocks = <&clkc 68>, <&clkc 31>; +}; + +&lpd_dma_chan7 { + clocks = <&clkc 68>, <&clkc 31>; +}; + +&lpd_dma_chan8 { + clocks = <&clkc 68>, <&clkc 31>; +}; + +&nand0 { + clocks = <&clkc 60>, <&clkc 31>; +}; + +&gem0 { + clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gem1 { + clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gem2 { + clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gem3 { + clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; +}; + +&gpio { + clocks = <&clkc 31>; +}; + +&i2c0 { + clocks = <&clkc 61>; +}; + +&i2c1 { + clocks = <&clkc 62>; +}; + +&pcie { + clocks = <&clkc 23>; +}; + +&qspi { + clocks = <&clkc 53>, <&clkc 31>; +}; + +&sata { + clocks = <&clkc 22>; +}; + +&sdhci0 { + clocks = <&clkc 54>, <&clkc 31>; +}; + +&sdhci1 { + clocks = <&clkc 55>, <&clkc 31>; +}; + +&spi0 { + clocks = <&clkc 58>, <&clkc 31>; +}; + +&spi1 { + clocks = <&clkc 59>, <&clkc 31>; +}; + +&uart0 { + clocks = <&clkc 56>, <&clkc 31>; +}; + +&uart1 { + clocks = <&clkc 57>, <&clkc 31>; +}; + +&usb0 { + clocks = <&clkc 32>, <&clkc 34>; +}; + +&usb1 { + clocks = <&clkc 33>, <&clkc 34>; +}; + +&watchdog0 { + clocks = <&clkc 75>; +}; + +&xilinx_ams { + clocks = <&clkc 70>; +}; + +&xilinx_drm { + clocks = <&clkc 16>; +}; + +&xlnx_dp { + clocks = <&dp_aclk>, <&clkc 17>; +}; + +&xlnx_dpdma { + clocks = <&clkc 20>; +}; + +&xlnx_dp_snd_codec0 { + clocks = <&clkc 17>; +}; diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi deleted file mode 100644 index 12d9fe1498..0000000000 --- a/arch/arm/dts/zynqmp-ep108-clk.dtsi +++ /dev/null @@ -1,172 +0,0 @@ -/* - * clock specification for Xilinx ZynqMP ep108 development board - * - * (C) Copyright 2015, Xilinx, Inc. - * - * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/ { - misc_clk: misc_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - u-boot,dm-pre-reloc; - }; - - i2c_clk: i2c_clk { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <111111111>; - }; - - sata_clk: sata_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <75000000>; - }; - - dp_aclk: clock0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-accuracy = <100>; - }; - - clk100: clk100 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - clk600: clk600 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - }; - - dp_aud_clk: clock1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <22579200>; - clock-accuracy = <100>; - }; -}; - -&can0 { - clocks = <&misc_clk &misc_clk>; -}; - -&can1 { - clocks = <&misc_clk &misc_clk>; -}; - -&fpd_dma_chan1 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan2 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan3 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan4 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan5 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan6 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan7 { - clocks = <&clk600>, <&clk100>; -}; - -&fpd_dma_chan8 { - clocks = <&clk600>, <&clk100>; -}; - -&gem0 { - clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>; -}; - -&gpio { - clocks = <&misc_clk>; -}; - -&i2c0 { - clocks = <&i2c_clk>; -}; - -&i2c1 { - clocks = <&i2c_clk>; -}; - -&nand0 { - clocks = <&misc_clk &misc_clk>; -}; - -&qspi { - clocks = <&misc_clk &misc_clk>; -}; - -&sata { - clocks = <&sata_clk>; -}; - -&sdhci0 { - clocks = <&misc_clk>, <&misc_clk>; -}; - -&sdhci1 { - clocks = <&misc_clk>, <&misc_clk>; -}; - -&spi0 { - clocks = <&misc_clk &misc_clk>; -}; - -&spi1 { - clocks = <&misc_clk &misc_clk>; -}; - -&uart0 { - clocks = <&misc_clk &misc_clk>; -}; - -&usb0 { - clocks = <&misc_clk>, <&misc_clk>; -}; - -&usb1 { - clocks = <&misc_clk>, <&misc_clk>; -}; - -&watchdog0 { - clocks= <&misc_clk>; -}; - -&xilinx_drm { - clocks = <&misc_clk>; -}; - -&xlnx_dp { - clocks = <&dp_aclk>, <&dp_aud_clk>; -}; - -&xlnx_dp_snd_codec0 { - clocks = <&dp_aud_clk>; -}; - -&xlnx_dpdma { - clocks = <&misc_clk>; -}; diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts deleted file mode 100644 index a16ffdc3f0..0000000000 --- a/arch/arm/dts/zynqmp-ep108.dts +++ /dev/null @@ -1,235 +0,0 @@ -/* - * dts file for Xilinx ZynqMP ep108 development board - * - * (C) Copyright 2014 - 2015, Xilinx, Inc. - * - * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-ep108-clk.dtsi" - -/ { - model = "ZynqMP EP108"; - - aliases { - ethernet0 = &gem0; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - serial0 = &uart0; - spi0 = &qspi; - spi1 = &spi0; - spi2 = &spi1; - usb0 = &usb0; - usb1 = &usb1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&gem0 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: phy@0 { - reg = <0>; - max-speed = <100>; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - eeprom@54 { - compatible = "atmel,24c64"; - reg = <0x54>; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - eeprom@55 { - compatible = "atmel,24c64"; - reg = <0x55>; - }; -}; - -&nand0 { - status = "okay"; - arasan,has-mdma; - num-cs = <1>; - - partition@0 { /* for testing purpose */ - label = "nand-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand-rootfs"; - reg = <0x0 0x1C00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand-misc"; - reg = <0x0 0x3400000 0xFCC00000>; - }; -}; - -&qspi { - status = "okay"; - flash@0 { - compatible = "m25p80"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <10000000>; - partition@qspi-fsbl-uboot { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@qspi-linux { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@qspi-device-tree { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@qspi-rootfs { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5E0000>; - }; - }; -}; - -&sata { - status = "okay"; - ceva,broken-gen2; - /* SATA Phy OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; - ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; - ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; - ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; - ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; - ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; -}; - -&sdhci0 { - status = "okay"; - bus-width = <8>; - xlnx,mio_bank = <2>; -}; - -&sdhci1 { - status = "okay"; - xlnx,mio_bank = <1>; -}; - -&spi0 { - status = "okay"; - num-cs = <1>; - spi0_flash0: spi0_flash0@0 { - compatible = "m25p80"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - spi0_flash0@0 { - label = "spi0_flash0"; - reg = <0x0 0x100000>; - }; - }; -}; - -&spi1 { - status = "okay"; - num-cs = <1>; - spi1_flash0: spi1_flash0@0 { - compatible = "m25p80"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - spi1_flash0@0 { - label = "spi1_flash0"; - reg = <0x0 0x100000>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&dwc3_0 { - status = "okay"; - dr_mode = "peripheral"; - maximum-speed = "high-speed"; -}; - -&usb1 { - status = "okay"; -}; - -&dwc3_1 { - status = "okay"; - dr_mode = "host"; - maximum-speed = "high-speed"; -}; - -&watchdog0 { - status = "okay"; -}; - -&xlnx_dp { - xlnx,max-pclock-frequency = <200000>; -}; - -&xlnx_dpdma { - xlnx,axi-clock-freq = <200000000>; -}; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 04d82c4d2e..9062ffe919 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -11,7 +11,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 7dfe960135..bf43bf8748 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -11,7 +11,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 648e3ba799..39c82c592f 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -11,7 +11,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" / { model = "ZynqMP zc1751-xm018-dc4"; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index f3020a5760..c774b866fb 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -12,7 +12,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" / { model = "ZynqMP zc1751-xm019-dc5 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 64a883b96e..2be6eb0eb5 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -11,7 +11,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> #include <dt-bindings/phy/phy.h> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 1ff5cac344..af68af471e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -82,6 +82,11 @@ #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) +#define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) +#define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) +#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) +#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) + #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) @@ -200,6 +205,8 @@ struct sys_info { /* Device Configuration and Pin Control */ #define DCFG_DCSR_PORCR1 0x0 +#define DCFG_DCSR_ECCCR2 0x524 +#define DISABLE_PFE_ECC BIT(13) struct ccsr_gur { u32 porsr1; /* POR status 1 */ @@ -390,6 +397,29 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 +/* RGMIIPCR bit definitions*/ +#define SCFG_RGMIIPCR_EN_AUTO BIT(3) +#define SCFG_RGMIIPCR_SETSP_1000M BIT(2) +#define SCFG_RGMIIPCR_SETSP_100M 0 +#define SCFG_RGMIIPCR_SETSP_10M BIT(1) +#define SCFG_RGMIIPCR_SETFD BIT(0) + +/* PFEASBCR bit definitions */ +#define SCFG_PFEASBCR_ARCACHE0 BIT(31) +#define SCFG_PFEASBCR_AWCACHE0 BIT(30) +#define SCFG_PFEASBCR_ARCACHE1 BIT(29) +#define SCFG_PFEASBCR_AWCACHE1 BIT(28) +#define SCFG_PFEASBCR_ARSNP BIT(27) +#define SCFG_PFEASBCR_AWSNP BIT(26) + +/* WR_QoS1 PFE bit definitions */ +#define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24) +#define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20) + +/* RD_QoS1 PFE bit definitions */ +#define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24) +#define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20) + /* Supplemental Configuration Unit */ struct ccsr_scfg { u8 res_000[0x100-0x000]; @@ -407,7 +437,12 @@ struct ccsr_scfg { u8 res_140[0x158-0x140]; u32 altcbar; u32 qspi_cfg; - u8 res_160[0x180-0x160]; + u8 res_160[0x164 - 0x160]; + u32 wr_qos1; + u32 wr_qos2; + u32 rd_qos1; + u32 rd_qos2; + u8 res_174[0x180 - 0x174]; u32 dmamcr; u8 res_184[0x188-0x184]; u32 gic_align; @@ -438,7 +473,21 @@ struct ccsr_scfg { u32 usb_refclk_selcr1; u32 usb_refclk_selcr2; u32 usb_refclk_selcr3; - u8 res_424[0x600-0x424]; + u8 res_424[0x434 - 0x424]; + u32 rgmiipcr; + u32 res_438; + u32 rgmiipsr; + u32 pfepfcssr1; + u32 pfeintencr1; + u32 pfepfcssr2; + u32 pfeintencr2; + u32 pfeerrcr; + u32 pfeeerrintencr; + u32 pfeasbcr; + u32 pfebsbcr; + u8 res_460[0x484 - 0x460]; + u32 mdioselcr; + u8 res_468[0x600 - 0x488]; u32 scratchrw[4]; u8 res_610[0x680-0x610]; u32 corebcr; @@ -591,6 +640,16 @@ struct ccsr_serdes { u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ }; +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + /* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) #define SMMU_SCR1 (SMMU_BASE + 0x4) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index f46f1d866a..fe97a930e5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -26,6 +26,7 @@ enum csu_cslx_ind { CSU_CSLX_PCIE3_IO, CSU_CSLX_USB3 = 20, CSU_CSLX_USB2, + CSU_CSLX_PFE = 23, CSU_CSLX_SERDES = 32, CSU_CSLX_QDMA, CSU_CSLX_LPUART2, @@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = { {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, {CSU_CSLX_USB3, CSU_ALL_RW}, {CSU_CSLX_USB2, CSU_ALL_RW}, + {CSU_CSLX_PFE, CSU_ALL_RW}, {CSU_CSLX_SERDES, CSU_ALL_RW}, {CSU_CSLX_QDMA, CSU_ALL_RW}, {CSU_CSLX_LPUART2, CSU_ALL_RW}, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index cb760b5b38..d9bfddb23b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -127,6 +127,9 @@ void fsl_lsch2_early_init_f(void); int setup_chip_volt(void); /* Setup core vdd in unit mV */ int board_setup_core_volt(u32 vdd); +#ifdef CONFIG_FSL_PFE +void init_pfe_scfg_dcfg_regs(void); +#endif #endif void cpu_name(char *name); diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h index d995b7db14..eaae10bdeb 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h @@ -80,413 +80,4 @@ struct rk3036_grf { }; check_member(rk3036_grf, sdmmc_det_cnt, 0x304); -/* GRF_GPIO0A_IOMUX */ -enum { - GPIO0A3_SHIFT = 6, - GPIO0A3_MASK = 1 << GPIO0A3_SHIFT, - GPIO0A3_GPIO = 0, - GPIO0A3_I2C1_SDA, - - GPIO0A2_SHIFT = 4, - GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, - GPIO0A2_GPIO = 0, - GPIO0A2_I2C1_SCL, - - GPIO0A1_SHIFT = 2, - GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, - GPIO0A1_GPIO = 0, - GPIO0A1_I2C0_SDA, - GPIO0A1_PWM2, - - GPIO0A0_SHIFT = 0, - GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, - GPIO0A0_GPIO = 0, - GPIO0A0_I2C0_SCL, - GPIO0A0_PWM1, -}; - -/* GRF_GPIO0B_IOMUX */ -enum { - GPIO0B6_SHIFT = 12, - GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, - GPIO0B6_GPIO = 0, - GPIO0B6_MMC1_D3, - GPIO0B6_I2S1_SCLK, - - GPIO0B5_SHIFT = 10, - GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, - GPIO0B5_GPIO = 0, - GPIO0B5_MMC1_D2, - GPIO0B5_I2S1_SDI, - - GPIO0B4_SHIFT = 8, - GPIO0B4_MASK = 3 << GPIO0B4_SHIFT, - GPIO0B4_GPIO = 0, - GPIO0B4_MMC1_D1, - GPIO0B4_I2S1_LRCKTX, - - GPIO0B3_SHIFT = 6, - GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, - GPIO0B3_GPIO = 0, - GPIO0B3_MMC1_D0, - GPIO0B3_I2S1_LRCKRX, - - GPIO0B1_SHIFT = 2, - GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, - GPIO0B1_GPIO = 0, - GPIO0B1_MMC1_CLKOUT, - GPIO0B1_I2S1_MCLK, - - GPIO0B0_SHIFT = 0, - GPIO0B0_MASK = 3, - GPIO0B0_GPIO = 0, - GPIO0B0_MMC1_CMD, - GPIO0B0_I2S1_SDO, -}; - -/* GRF_GPIO0C_IOMUX */ -enum { - GPIO0C4_SHIFT = 8, - GPIO0C4_MASK = 1 << GPIO0C4_SHIFT, - GPIO0C4_GPIO = 0, - GPIO0C4_DRIVE_VBUS, - - GPIO0C3_SHIFT = 6, - GPIO0C3_MASK = 1 << GPIO0C3_SHIFT, - GPIO0C3_GPIO = 0, - GPIO0C3_UART0_CTSN, - - GPIO0C2_SHIFT = 4, - GPIO0C2_MASK = 1 << GPIO0C2_SHIFT, - GPIO0C2_GPIO = 0, - GPIO0C2_UART0_RTSN, - - GPIO0C1_SHIFT = 2, - GPIO0C1_MASK = 1 << GPIO0C1_SHIFT, - GPIO0C1_GPIO = 0, - GPIO0C1_UART0_SIN, - - - GPIO0C0_SHIFT = 0, - GPIO0C0_MASK = 1 << GPIO0C0_SHIFT, - GPIO0C0_GPIO = 0, - GPIO0C0_UART0_SOUT, -}; - -/* GRF_GPIO0D_IOMUX */ -enum { - GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, - GPIO0D4_GPIO = 0, - GPIO0D4_SPDIF, - - GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, - GPIO0D3_GPIO = 0, - GPIO0D3_PWM3, - - GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, - GPIO0D2_GPIO = 0, - GPIO0D2_PWM0, -}; - -/* GRF_GPIO1A_IOMUX */ -enum { - GPIO1A5_SHIFT = 10, - GPIO1A5_MASK = 1 << GPIO1A5_SHIFT, - GPIO1A5_GPIO = 0, - GPIO1A5_I2S_SDI, - - GPIO1A4_SHIFT = 8, - GPIO1A4_MASK = 1 << GPIO1A4_SHIFT, - GPIO1A4_GPIO = 0, - GPIO1A4_I2S_SD0, - - GPIO1A3_SHIFT = 6, - GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, - GPIO1A3_GPIO = 0, - GPIO1A3_I2S_LRCKTX, - - GPIO1A2_SHIFT = 4, - GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, - GPIO1A2_GPIO = 0, - GPIO1A2_I2S_LRCKRX, - GPIO1A2_PWM1_0, - - GPIO1A1_SHIFT = 2, - GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, - GPIO1A1_GPIO = 0, - GPIO1A1_I2S_SCLK, - - GPIO1A0_SHIFT = 0, - GPIO1A0_MASK = 1 << GPIO1A0_SHIFT, - GPIO1A0_GPIO = 0, - GPIO1A0_I2S_MCLK, - -}; - -/* GRF_GPIO1B_IOMUX */ -enum { - GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, - GPIO1B7_GPIO = 0, - GPIO1B7_MMC0_CMD, - - GPIO1B3_SHIFT = 6, - GPIO1B3_MASK = 1 << GPIO1B3_SHIFT, - GPIO1B3_GPIO = 0, - GPIO1B3_HDMI_HPD, - - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 1 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_HDMI_SCL, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 1 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_HDMI_SDA, - - GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 1 << GPIO1B0_SHIFT, - GPIO1B0_GPIO = 0, - GPIO1B0_HDMI_CEC, -}; - -/* GRF_GPIO1C_IOMUX */ -enum { - GPIO1C5_SHIFT = 10, - GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, - GPIO1C5_GPIO = 0, - GPIO1C5_MMC0_D3, - GPIO1C5_JTAG_TMS, - - GPIO1C4_SHIFT = 8, - GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, - GPIO1C4_GPIO = 0, - GPIO1C4_MMC0_D2, - GPIO1C4_JTAG_TCK, - - GPIO1C3_SHIFT = 6, - GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, - GPIO1C3_GPIO = 0, - GPIO1C3_MMC0_D1, - GPIO1C3_UART2_SOUT, - - GPIO1C2_SHIFT = 4, - GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , - GPIO1C2_GPIO = 0, - GPIO1C2_MMC0_D0, - GPIO1C2_UART2_SIN, - - GPIO1C1_SHIFT = 2, - GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, - GPIO1C1_GPIO = 0, - GPIO1C1_MMC0_DETN, - - GPIO1C0_SHIFT = 0, - GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, - GPIO1C0_GPIO = 0, - GPIO1C0_MMC0_CLKOUT, -}; - -/* GRF_GPIO1D_IOMUX */ -enum { - GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, - GPIO1D7_GPIO = 0, - GPIO1D7_NAND_D7, - GPIO1D7_EMMC_D7, - GPIO1D7_SPI_CSN1, - - GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, - GPIO1D6_GPIO = 0, - GPIO1D6_NAND_D6, - GPIO1D6_EMMC_D6, - GPIO1D6_SPI_CSN0, - - GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, - GPIO1D5_GPIO = 0, - GPIO1D5_NAND_D5, - GPIO1D5_EMMC_D5, - GPIO1D5_SPI_TXD, - - GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, - GPIO1D4_GPIO = 0, - GPIO1D4_NAND_D4, - GPIO1D4_EMMC_D4, - GPIO1D4_SPI_RXD, - - GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, - GPIO1D3_GPIO = 0, - GPIO1D3_NAND_D3, - GPIO1D3_EMMC_D3, - GPIO1D3_SFC_SIO3, - - GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, - GPIO1D2_GPIO = 0, - GPIO1D2_NAND_D2, - GPIO1D2_EMMC_D2, - GPIO1D2_SFC_SIO2, - - GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, - GPIO1D1_GPIO = 0, - GPIO1D1_NAND_D1, - GPIO1D1_EMMC_D1, - GPIO1D1_SFC_SIO1, - - GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, - GPIO1D0_GPIO = 0, - GPIO1D0_NAND_D0, - GPIO1D0_EMMC_D0, - GPIO1D0_SFC_SIO0, -}; - -/* GRF_GPIO2A_IOMUX */ -enum { - GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 1 << GPIO2A7_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_TESTCLK_OUT, - - GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, - GPIO2A6_GPIO = 0, - GPIO2A6_NAND_CS0, - - GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, - GPIO2A4_GPIO = 0, - GPIO2A4_NAND_RDY, - GPIO2A4_EMMC_CMD, - GPIO2A3_SFC_CLK, - - GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, - GPIO2A3_GPIO = 0, - GPIO2A3_NAND_RDN, - GPIO2A4_SFC_CSN1, - - GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, - GPIO2A2_GPIO = 0, - GPIO2A2_NAND_WRN, - GPIO2A4_SFC_CSN0, - - GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, - GPIO2A1_GPIO = 0, - GPIO2A1_NAND_CLE, - GPIO2A1_EMMC_CLKOUT, - - GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, - GPIO2A0_GPIO = 0, - GPIO2A0_NAND_ALE, - GPIO2A0_SPI_CLK, -}; - -/* GRF_GPIO2B_IOMUX */ -enum { - GPIO2B7_SHIFT = 14, - GPIO2B7_MASK = 1 << GPIO2B7_SHIFT, - GPIO2B7_GPIO = 0, - GPIO2B7_MAC_RXER, - - GPIO2B6_SHIFT = 12, - GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, - GPIO2B6_GPIO = 0, - GPIO2B6_MAC_CLKOUT, - GPIO2B6_MAC_CLKIN, - - GPIO2B5_SHIFT = 10, - GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, - GPIO2B5_GPIO = 0, - GPIO2B5_MAC_TXEN, - - GPIO2B4_SHIFT = 8, - GPIO2B4_MASK = 1 << GPIO2B4_SHIFT, - GPIO2B4_GPIO = 0, - GPIO2B4_MAC_MDIO, - - GPIO2B2_SHIFT = 4, - GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, - GPIO2B2_GPIO = 0, - GPIO2B2_MAC_CRS, -}; - -/* GRF_GPIO2C_IOMUX */ -enum { - GPIO2C7_SHIFT = 14, - GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, - GPIO2C7_GPIO = 0, - GPIO2C7_UART1_SOUT, - GPIO2C7_TESTCLK_OUT1, - - GPIO2C6_SHIFT = 12, - GPIO2C6_MASK = 1 << GPIO2C6_SHIFT, - GPIO2C6_GPIO = 0, - GPIO2C6_UART1_SIN, - - GPIO2C5_SHIFT = 10, - GPIO2C5_MASK = 1 << GPIO2C5_SHIFT, - GPIO2C5_GPIO = 0, - GPIO2C5_I2C2_SCL, - - GPIO2C4_SHIFT = 8, - GPIO2C4_MASK = 1 << GPIO2C4_SHIFT, - GPIO2C4_GPIO = 0, - GPIO2C4_I2C2_SDA, - - GPIO2C3_SHIFT = 6, - GPIO2C3_MASK = 1 << GPIO2C3_SHIFT, - GPIO2C3_GPIO = 0, - GPIO2C3_MAC_TXD0, - - GPIO2C2_SHIFT = 4, - GPIO2C2_MASK = 1 << GPIO2C2_SHIFT, - GPIO2C2_GPIO = 0, - GPIO2C2_MAC_TXD1, - - GPIO2C1_SHIFT = 2, - GPIO2C1_MASK = 1 << GPIO2C1_SHIFT, - GPIO2C1_GPIO = 0, - GPIO2C1_MAC_RXD0, - - GPIO2C0_SHIFT = 0, - GPIO2C0_MASK = 1 << GPIO2C0_SHIFT, - GPIO2C0_GPIO = 0, - GPIO2C0_MAC_RXD1, -}; - -/* GRF_GPIO2D_IOMUX */ -enum { - GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, - GPIO2D6_GPIO = 0, - GPIO2D6_I2S_SDO1, - - GPIO2D5_SHIFT = 10, - GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, - GPIO2D5_GPIO = 0, - GPIO2D5_I2S_SDO2, - - GPIO2D4_SHIFT = 8, - GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, - GPIO2D4_GPIO = 0, - GPIO2D4_I2S_SDO3, - - GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 1 << GPIO2D1_SHIFT, - GPIO2D1_GPIO = 0, - GPIO2D1_MAC_MDC, -}; #endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h index ce7bac5338..905288e0d5 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h @@ -69,386 +69,6 @@ struct rk3188_grf { }; check_member(rk3188_grf, flash_cmd_p, 0x01a4); -/* GRF_GPIO0D_IOMUX */ -enum { - GPIO0D7_SHIFT = 14, - GPIO0D7_MASK = 1, - GPIO0D7_GPIO = 0, - GPIO0D7_SPI1_CSN0, - - GPIO0D6_SHIFT = 12, - GPIO0D6_MASK = 1, - GPIO0D6_GPIO = 0, - GPIO0D6_SPI1_CLK, - - GPIO0D5_SHIFT = 10, - GPIO0D5_MASK = 1, - GPIO0D5_GPIO = 0, - GPIO0D5_SPI1_TXD, - - GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 1, - GPIO0D4_GPIO = 0, - GPIO0D4_SPI0_RXD, - - GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 3, - GPIO0D3_GPIO = 0, - GPIO0D3_FLASH_CSN3, - GPIO0D3_EMMC_RSTN_OUT, - - GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 3, - GPIO0D2_GPIO = 0, - GPIO0D2_FLASH_CSN2, - GPIO0D2_EMMC_CMD, - - GPIO0D1_SHIFT = 2, - GPIO0D1_MASK = 1, - GPIO0D1_GPIO = 0, - GPIO0D1_FLASH_CSN1, - - GPIO0D0_SHIFT = 0, - GPIO0D0_MASK = 3, - GPIO0D0_GPIO = 0, - GPIO0D0_FLASH_DQS, - GPIO0D0_EMMC_CLKOUT -}; - -/* GRF_GPIO1A_IOMUX */ -enum { - GPIO1A7_SHIFT = 14, - GPIO1A7_MASK = 3, - GPIO1A7_GPIO = 0, - GPIO1A7_UART1_RTS_N, - GPIO1A7_SPI0_CSN0, - - GPIO1A6_SHIFT = 12, - GPIO1A6_MASK = 3, - GPIO1A6_GPIO = 0, - GPIO1A6_UART1_CTS_N, - GPIO1A6_SPI0_CLK, - - GPIO1A5_SHIFT = 10, - GPIO1A5_MASK = 3, - GPIO1A5_GPIO = 0, - GPIO1A5_UART1_SOUT, - GPIO1A5_SPI0_TXD, - - GPIO1A4_SHIFT = 8, - GPIO1A4_MASK = 3, - GPIO1A4_GPIO = 0, - GPIO1A4_UART1_SIN, - GPIO1A4_SPI0_RXD, - - GPIO1A3_SHIFT = 6, - GPIO1A3_MASK = 1, - GPIO1A3_GPIO = 0, - GPIO1A3_UART0_RTS_N, - - GPIO1A2_SHIFT = 4, - GPIO1A2_MASK = 1, - GPIO1A2_GPIO = 0, - GPIO1A2_UART0_CTS_N, - - GPIO1A1_SHIFT = 2, - GPIO1A1_MASK = 1, - GPIO1A1_GPIO = 0, - GPIO1A1_UART0_SOUT, - - GPIO1A0_SHIFT = 0, - GPIO1A0_MASK = 1, - GPIO1A0_GPIO = 0, - GPIO1A0_UART0_SIN, -}; - -/* GRF_GPIO1B_IOMUX */ -enum { - GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 1, - GPIO1B7_GPIO = 0, - GPIO1B7_SPI0_CSN1, - - GPIO1B6_SHIFT = 12, - GPIO1B6_MASK = 3, - GPIO1B6_GPIO = 0, - GPIO1B6_SPDIF_TX, - GPIO1B6_SPI1_CSN1, - - GPIO1B5_SHIFT = 10, - GPIO1B5_MASK = 3, - GPIO1B5_GPIO = 0, - GPIO1B5_UART3_RTS_N, - GPIO1B5_RESERVED, - - GPIO1B4_SHIFT = 8, - GPIO1B4_MASK = 3, - GPIO1B4_GPIO = 0, - GPIO1B4_UART3_CTS_N, - GPIO1B4_GPS_RFCLK, - - GPIO1B3_SHIFT = 6, - GPIO1B3_MASK = 3, - GPIO1B3_GPIO = 0, - GPIO1B3_UART3_SOUT, - GPIO1B3_GPS_SIG, - - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3, - GPIO1B2_GPIO = 0, - GPIO1B2_UART3_SIN, - GPIO1B2_GPS_MAG, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3, - GPIO1B1_GPIO = 0, - GPIO1B1_UART2_SOUT, - GPIO1B1_JTAG_TDO, - - GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 3, - GPIO1B0_GPIO = 0, - GPIO1B0_UART2_SIN, - GPIO1B0_JTAG_TDI, -}; - -/* GRF_GPIO1D_IOMUX */ -enum { - GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 1, - GPIO1D7_GPIO = 0, - GPIO1D7_I2C4_SCL, - - GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 1, - GPIO1D6_GPIO = 0, - GPIO1D6_I2C4_SDA, - - GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 1, - GPIO1D5_GPIO = 0, - GPIO1D5_I2C2_SCL, - - GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 1, - GPIO1D4_GPIO = 0, - GPIO1D4_I2C2_SDA, - - GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 1, - GPIO1D3_GPIO = 0, - GPIO1D3_I2C1_SCL, - - GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 1, - GPIO1D2_GPIO = 0, - GPIO1D2_I2C1_SDA, - - GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 1, - GPIO1D1_GPIO = 0, - GPIO1D1_I2C0_SCL, - - GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 1, - GPIO1D0_GPIO = 0, - GPIO1D0_I2C0_SDA, -}; - -/* GRF_GPIO3A_IOMUX */ -enum { - GPIO3A7_SHIFT = 14, - GPIO3A7_MASK = 1, - GPIO3A7_GPIO = 0, - GPIO3A7_SDMMC0_DATA3, - - GPIO3A6_SHIFT = 12, - GPIO3A6_MASK = 1, - GPIO3A6_GPIO = 0, - GPIO3A6_SDMMC0_DATA2, - - GPIO3A5_SHIFT = 10, - GPIO3A5_MASK = 1, - GPIO3A5_GPIO = 0, - GPIO3A5_SDMMC0_DATA1, - - GPIO3A4_SHIFT = 8, - GPIO3A4_MASK = 1, - GPIO3A4_GPIO = 0, - GPIO3A4_SDMMC0_DATA0, - - GPIO3A3_SHIFT = 6, - GPIO3A3_MASK = 1, - GPIO3A3_GPIO = 0, - GPIO3A3_SDMMC0_CMD, - - GPIO3A2_SHIFT = 4, - GPIO3A2_MASK = 1, - GPIO3A2_GPIO = 0, - GPIO3A2_SDMMC0_CLKOUT, - - GPIO3A1_SHIFT = 2, - GPIO3A1_MASK = 1, - GPIO3A1_GPIO = 0, - GPIO3A1_SDMMC0_PWREN, - - GPIO3A0_SHIFT = 0, - GPIO3A0_MASK = 1, - GPIO3A0_GPIO = 0, - GPIO3A0_SDMMC0_RSTN, -}; - -/* GRF_GPIO3B_IOMUX */ -enum { - GPIO3B7_SHIFT = 14, - GPIO3B7_MASK = 3, - GPIO3B7_GPIO = 0, - GPIO3B7_CIF_DATA11, - GPIO3B7_I2C3_SCL, - - GPIO3B6_SHIFT = 12, - GPIO3B6_MASK = 3, - GPIO3B6_GPIO = 0, - GPIO3B6_CIF_DATA10, - GPIO3B6_I2C3_SDA, - - GPIO3B5_SHIFT = 10, - GPIO3B5_MASK = 3, - GPIO3B5_GPIO = 0, - GPIO3B5_CIF_DATA1, - GPIO3B5_HSADC_DATA9, - - GPIO3B4_SHIFT = 8, - GPIO3B4_MASK = 3, - GPIO3B4_GPIO = 0, - GPIO3B4_CIF_DATA0, - GPIO3B4_HSADC_DATA8, - - GPIO3B3_SHIFT = 6, - GPIO3B3_MASK = 1, - GPIO3B3_GPIO = 0, - GPIO3B3_CIF_CLKOUT, - - GPIO3B2_SHIFT = 4, - GPIO3B2_MASK = 1, - GPIO3B2_GPIO = 0, - /* no muxes */ - - GPIO3B1_SHIFT = 2, - GPIO3B1_MASK = 1, - GPIO3B1_GPIO = 0, - GPIO3B1_SDMMC0_WRITE_PRT, - - GPIO3B0_SHIFT = 0, - GPIO3B0_MASK = 1, - GPIO3B0_GPIO = 0, - GPIO3B0_SDMMC_DETECT_N, -}; - -/* GRF_GPIO3C_IOMUX */ -enum { - GPIO3C7_SHIFT = 14, - GPIO3C7_MASK = 3, - GPIO3C7_GPIO = 0, - GPIO3C7_SDMMC1_WRITE_PRT, - GPIO3C7_RMII_CRS_DVALID, - GPIO3C7_RESERVED, - - GPIO3C6_SHIFT = 12, - GPIO3C6_MASK = 3, - GPIO3C6_GPIO = 0, - GPIO3C6_SDMMC1_DECTN, - GPIO3C6_RMII_RX_ERR, - GPIO3C6_RESERVED, - - GPIO3C5_SHIFT = 10, - GPIO3C5_MASK = 3, - GPIO3C5_GPIO = 0, - GPIO3C5_SDMMC1_CLKOUT, - GPIO3C5_RMII_CLKOUT, - GPIO3C5_RMII_CLKIN, - - GPIO3C4_SHIFT = 8, - GPIO3C4_MASK = 3, - GPIO3C4_GPIO = 0, - GPIO3C4_SDMMC1_DATA3, - GPIO3C4_RMII_RXD1, - GPIO3C4_RESERVED, - - GPIO3C3_SHIFT = 6, - GPIO3C3_MASK = 3, - GPIO3C3_GPIO = 0, - GPIO3C3_SDMMC1_DATA2, - GPIO3C3_RMII_RXD0, - GPIO3C3_RESERVED, - - GPIO3C2_SHIFT = 4, - GPIO3C2_MASK = 3, - GPIO3C2_GPIO = 0, - GPIO3C2_SDMMC1_DATA1, - GPIO3C2_RMII_TXD0, - GPIO3C2_RESERVED, - - GPIO3C1_SHIFT = 2, - GPIO3C1_MASK = 3, - GPIO3C1_GPIO = 0, - GPIO3C1_SDMMC1_DATA0, - GPIO3C1_RMII_TXD1, - GPIO3C1_RESERVED, - - GPIO3C0_SHIFT = 0, - GPIO3C0_MASK = 3, - GPIO3C0_GPIO = 0, - GPIO3C0_SDMMC1_CMD, - GPIO3C0_RMII_TX_EN, - GPIO3C0_RESERVED, -}; - -/* GRF_GPIO3D_IOMUX */ -enum { - GPIO3D6_SHIFT = 12, - GPIO3D6_MASK = 3, - GPIO3D6_GPIO = 0, - GPIO3D6_PWM_3, - GPIO3D6_JTAG_TMS, - GPIO3D6_HOST_DRV_VBUS, - - GPIO3D5_SHIFT = 10, - GPIO3D5_MASK = 3, - GPIO3D5_GPIO = 0, - GPIO3D5_PWM_2, - GPIO3D5_JTAG_TCK, - GPIO3D5_OTG_DRV_VBUS, - - GPIO3D4_SHIFT = 8, - GPIO3D4_MASK = 3, - GPIO3D4_GPIO = 0, - GPIO3D4_PWM_1, - GPIO3D4_JTAG_TRSTN, - - GPIO3D3_SHIFT = 6, - GPIO3D3_MASK = 3, - GPIO3D3_GPIO = 0, - GPIO3D3_PWM_0, - - GPIO3D2_SHIFT = 4, - GPIO3D2_MASK = 3, - GPIO3D2_GPIO = 0, - GPIO3D2_SDMMC1_INT_N, - - GPIO3D1_SHIFT = 2, - GPIO3D1_MASK = 3, - GPIO3D1_GPIO = 0, - GPIO3D1_SDMMC1_BACKEND_PWR, - GPIO3D1_MII_MDCLK, - - GPIO3D0_SHIFT = 0, - GPIO3D0_MASK = 3, - GPIO3D0_GPIO = 0, - GPIO3D0_SDMMC1_PWR_EN, - GPIO3D0_MII_MD, -}; - /* GRF_SOC_CON0 */ enum { HSADC_CLK_DIR_SHIFT = 15, diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index b541e2caa1..91e8d2d216 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -324,13 +324,29 @@ struct rk3399_pmusgrf_regs { check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4); enum { + /* GRF_GPIO2A_IOMUX */ + GRF_GPIO2A0_SEL_SHIFT = 0, + GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT, + GRF_I2C2_SDA = 2, + GRF_GPIO2A1_SEL_SHIFT = 2, + GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT, + GRF_I2C2_SCL = 2, + GRF_GPIO2A7_SEL_SHIFT = 14, + GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT, + GRF_I2C7_SDA = 2, + /* GRF_GPIO2B_IOMUX */ - GRF_GPIO2B1_SEL_SHIFT = 0, + GRF_GPIO2B0_SEL_SHIFT = 0, + GRF_GPIO2B0_SEL_MASK = 3 << GRF_GPIO2B0_SEL_SHIFT, + GRF_I2C7_SCL = 2, + GRF_GPIO2B1_SEL_SHIFT = 2, GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT, GRF_SPI2TPM_RXD = 1, - GRF_GPIO2B2_SEL_SHIFT = 2, + GRF_I2C6_SDA = 2, + GRF_GPIO2B2_SEL_SHIFT = 4, GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT, GRF_SPI2TPM_TXD = 1, + GRF_I2C6_SCL = 2, GRF_GPIO2B3_SEL_SHIFT = 6, GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT, GRF_SPI2TPM_CLK = 1, @@ -414,6 +430,14 @@ enum { GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT, GRF_MAC_TXCLK = 1, + /* GRF_GPIO4A_IOMUX */ + GRF_GPIO4A1_SEL_SHIFT = 2, + GRF_GPIO4A1_SEL_MASK = 3 << GRF_GPIO4A1_SEL_SHIFT, + GRF_I2C1_SDA = 1, + GRF_GPIO4A2_SEL_SHIFT = 4, + GRF_GPIO4A2_SEL_MASK = 3 << GRF_GPIO4A2_SEL_SHIFT, + GRF_I2C1_SCL = 1, + /* GRF_GPIO4B_IOMUX */ GRF_GPIO4B0_SEL_SHIFT = 0, GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT, @@ -575,6 +599,12 @@ enum { PMUGRF_GPIO1B2_SEL_SHIFT = 4, PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT, PMUGRF_SPI1EC_CSN0 = 2, + PMUGRF_GPIO1B3_SEL_SHIFT = 6, + PMUGRF_GPIO1B3_SEL_MASK = 3 << PMUGRF_GPIO1B3_SEL_SHIFT, + PMUGRF_I2C4_SDA = 1, + PMUGRF_GPIO1B4_SEL_SHIFT = 8, + PMUGRF_GPIO1B4_SEL_MASK = 3 << PMUGRF_GPIO1B4_SEL_SHIFT, + PMUGRF_I2C4_SCL = 1, PMUGRF_GPIO1B6_SEL_SHIFT = 12, PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT, PMUGRF_PWM_3B = 1, diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 084d55a2b0..ad3dc9aba5 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -11,6 +11,8 @@ #define PAYLOAD_ARG_CNT 5 #define ZYNQMP_CSU_SILICON_VER_MASK 0xF +#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D +#define KEY_PTR_LEN 32 enum { IDCODE, diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 30752839a3..5e7baba3fe 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -58,6 +58,7 @@ config SOC_DA850 config SOC_DA8XX bool select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL + select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL config MACH_DAVINCI_DA850_EVM bool diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index b9214f7bd9..ab4164cbe0 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -46,6 +46,14 @@ static struct mm_region mvebu_mem_map[] = { PTE_BLOCK_NON_SHARE }, { + /* PCI regions */ + .phys = 0xe8000000UL, + .virt = 0xe8000000UL, + .size = 0x02000000UL, /* 32MiB master PCI space */ + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, + { /* List terminator */ 0, } diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig new file mode 100644 index 0000000000..8c755f8e64 --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig @@ -0,0 +1,43 @@ +if ARCH_STM32MP + +config SPL + select SPL_BOARD_INIT + select SPL_CLK + select SPL_DM + select SPL_DM_SEQ_ALIAS + select SPL_FRAMEWORK + select SPL_GPIO_SUPPORT + select SPL_LIBCOMMON_SUPPORT + select SPL_LIBGENERIC_SUPPORT + select SPL_OF_CONTROL + select SPL_OF_TRANSLATE + select SPL_PINCTRL + select SPL_REGMAP + select SPL_RESET_SUPPORT + select SPL_SERIAL_SUPPORT + select SPL_SYSCON + imply SPL_LIBDISK_SUPPORT + +config SYS_SOC + default "stm32mp" + +config TARGET_STM32MP1 + bool "Support stm32mp1xx" + select CPU_V7 + select PINCTRL_STM32 + select STM32_RESET + help + target STMicroelectronics SOC STM32MP1 family + STMicroelectronics MPU with core ARMv7 + +config SYS_TEXT_BASE + prompt "U-Boot base address" + default 0xC0100000 + help + configure the U-Boot base address + when DDR driver is used: + DDR + 1MB (0xC0100000) + +source "board/st/stm32mp1/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile new file mode 100644 index 0000000000..4620869b36 --- /dev/null +++ b/arch/arm/mach-stm32mp/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# +# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +# + +obj-y += cpu.o +obj-y += dram_init.o + +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/mach-stm32mp/config.mk b/arch/arm/mach-stm32mp/config.mk new file mode 100644 index 0000000000..34e59c61ac --- /dev/null +++ b/arch/arm/mach-stm32mp/config.mk @@ -0,0 +1,14 @@ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# +# SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause +# + +ALL-$(CONFIG_SPL_BUILD) += spl/u-boot-spl.stm32 + +MKIMAGEFLAGS_u-boot-spl.stm32 = -T stm32image -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) + +spl/u-boot-spl.stm32: MKIMAGEOUTPUT = spl/u-boot-spl.stm32.log + +spl/u-boot-spl.stm32: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c new file mode 100644 index 0000000000..7c43dc1294 --- /dev/null +++ b/arch/arm/mach-stm32mp/cpu.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ +#include <common.h> +#include <clk.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> + +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +/********************************************** + * Security init + *********************************************/ +#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) +#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) + +#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) +#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) +#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) + +#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) + +#define PWR_CR1 (STM32_PWR_BASE + 0x00) +#define PWR_CR1_DBP BIT(8) + +#define RCC_TZCR (STM32_RCC_BASE + 0x00) +#define RCC_BDCR (STM32_RCC_BASE + 0x0140) +#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) + +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_RTCSRC GENMASK(17, 16) + +static void security_init(void) +{ + /* Disable the backup domain write protection */ + /* the protection is enable at each reset by hardware */ + /* And must be disable by software */ + setbits_le32(PWR_CR1, PWR_CR1_DBP); + + while (!(readl(PWR_CR1) & PWR_CR1_DBP)) + ; + + /* If RTC clock isn't enable so this is a cold boot then we need + * to reset the backup domain + */ + if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { + setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) + ; + clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + } + + /* allow non secure access in Write/Read for all peripheral */ + writel(GENMASK(25, 0), ETZPC_DECPROT0); + + /* Open SYSRAM for no secure access */ + writel(0x0, ETZPC_TZMA1_SIZE); + + /* enable TZC1 TZC2 clock */ + writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); + + /* Region 0 set to no access by default */ + /* bit 0 / 16 => nsaid0 read/write Enable + * bit 1 / 17 => nsaid1 read/write Enable + * ... + * bit 15 / 31 => nsaid15 read/write Enable + */ + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); + /* bit 30 / 31 => Secure Global Enable : write/read */ + /* bit 0 / 1 => Region Enable for filter 0/1 */ + writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); + + /* Enable Filter 0 and 1 */ + setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); + + /* RCC trust zone deactivated */ + writel(0x0, RCC_TZCR); + + /* TAMP: deactivate the internal tamper + * Bit 23 ITAMP8E: monotonic counter overflow + * Bit 20 ITAMP5E: RTC calendar overflow + * Bit 19 ITAMP4E: HSE monitoring + * Bit 18 ITAMP3E: LSE monitoring + * Bit 16 ITAMP1E: RTC power domain supply monitoring + */ + writel(0x0, TAMP_CR1); +} + +/********************************************** + * Debug init + *********************************************/ +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) +#define RCC_DBGCFGR_DBGCKEN BIT(8) + +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) +#define DBGMCU_APB4FZ1_IWDG2 BIT(2) + +static void dbgmcu_init(void) +{ + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + + /* Freeze IWDG2 if Cortex-A7 is in debug mode */ + setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); +} +#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ + +int arch_cpu_init(void) +{ + /* early armv7 timer init: needed for polling */ + timer_init(); + +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + dbgmcu_init(); + + security_init(); +#endif + + return 0; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("CPU: STM32MP15x\n"); + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +void reset_cpu(ulong addr) +{ +} diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c new file mode 100644 index 0000000000..ecb4c988d2 --- /dev/null +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#include <common.h> +#include <dm.h> +#include <ram.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("RAM init failed: %d\n", ret); + return ret; + } + ret = ram_get_info(dev, &ram); + if (ret) { + debug("Cannot get RAM size: %d\n", ret); + return ret; + } + debug("RAM init base=%lx, size=%x\n", ram.base, ram.size); + + gd->ram_size = ram.size; + + return 0; +} diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h new file mode 100644 index 0000000000..b635001df8 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/ddr.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#ifndef __MACH_STM32MP_DDR_H_ +#define __MACH_STM32MP_DDR_H_ + +int board_ddr_power_init(void); + +#endif diff --git a/arch/arm/mach-stm32mp/include/mach/gpio.h b/arch/arm/mach-stm32mp/include/mach/gpio.h new file mode 100644 index 0000000000..5952557792 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/gpio.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STM32_GPIO_H_ +#define _STM32_GPIO_H_ +#include <asm/gpio.h> + +enum stm32_gpio_port { + STM32_GPIO_PORT_A = 0, + STM32_GPIO_PORT_B, + STM32_GPIO_PORT_C, + STM32_GPIO_PORT_D, + STM32_GPIO_PORT_E, + STM32_GPIO_PORT_F, + STM32_GPIO_PORT_G, + STM32_GPIO_PORT_H, + STM32_GPIO_PORT_I +}; + +enum stm32_gpio_pin { + STM32_GPIO_PIN_0 = 0, + STM32_GPIO_PIN_1, + STM32_GPIO_PIN_2, + STM32_GPIO_PIN_3, + STM32_GPIO_PIN_4, + STM32_GPIO_PIN_5, + STM32_GPIO_PIN_6, + STM32_GPIO_PIN_7, + STM32_GPIO_PIN_8, + STM32_GPIO_PIN_9, + STM32_GPIO_PIN_10, + STM32_GPIO_PIN_11, + STM32_GPIO_PIN_12, + STM32_GPIO_PIN_13, + STM32_GPIO_PIN_14, + STM32_GPIO_PIN_15 +}; + +enum stm32_gpio_mode { + STM32_GPIO_MODE_IN = 0, + STM32_GPIO_MODE_OUT, + STM32_GPIO_MODE_AF, + STM32_GPIO_MODE_AN +}; + +enum stm32_gpio_otype { + STM32_GPIO_OTYPE_PP = 0, + STM32_GPIO_OTYPE_OD +}; + +enum stm32_gpio_speed { + STM32_GPIO_SPEED_2M = 0, + STM32_GPIO_SPEED_25M, + STM32_GPIO_SPEED_50M, + STM32_GPIO_SPEED_100M +}; + +enum stm32_gpio_pupd { + STM32_GPIO_PUPD_NO = 0, + STM32_GPIO_PUPD_UP, + STM32_GPIO_PUPD_DOWN +}; + +enum stm32_gpio_af { + STM32_GPIO_AF0 = 0, + STM32_GPIO_AF1, + STM32_GPIO_AF2, + STM32_GPIO_AF3, + STM32_GPIO_AF4, + STM32_GPIO_AF5, + STM32_GPIO_AF6, + STM32_GPIO_AF7, + STM32_GPIO_AF8, + STM32_GPIO_AF9, + STM32_GPIO_AF10, + STM32_GPIO_AF11, + STM32_GPIO_AF12, + STM32_GPIO_AF13, + STM32_GPIO_AF14, + STM32_GPIO_AF15 +}; + +struct stm32_gpio_dsc { + enum stm32_gpio_port port; + enum stm32_gpio_pin pin; +}; + +struct stm32_gpio_ctl { + enum stm32_gpio_mode mode; + enum stm32_gpio_otype otype; + enum stm32_gpio_speed speed; + enum stm32_gpio_pupd pupd; + enum stm32_gpio_af af; +}; + +struct stm32_gpio_regs { + u32 moder; /* GPIO port mode */ + u32 otyper; /* GPIO port output type */ + u32 ospeedr; /* GPIO port output speed */ + u32 pupdr; /* GPIO port pull-up/pull-down */ + u32 idr; /* GPIO port input data */ + u32 odr; /* GPIO port output data */ + u32 bsrr; /* GPIO port bit set/reset */ + u32 lckr; /* GPIO port configuration lock */ + u32 afr[2]; /* GPIO alternate function */ +}; + +struct stm32_gpio_priv { + struct stm32_gpio_regs *regs; +}; +#endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h new file mode 100644 index 0000000000..ffbe0b1034 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#ifndef _MACH_STM32_H_ +#define _MACH_STM32_H_ + +/* + * Peripheral memory map + * only address used before device tree parsing + */ +#define STM32_RCC_BASE 0x50000000 +#define STM32_PWR_BASE 0x50001000 +#define STM32_DBGMCU_BASE 0x50081000 +#define STM32_TZC_BASE 0x5C006000 +#define STM32_ETZPC_BASE 0x5C007000 +#define STM32_TAMP_BASE 0x5C00A000 + +#define STM32_SYSRAM_BASE 0x2FFC0000 +#define STM32_SYSRAM_SIZE SZ_256K + +#define STM32_DDR_BASE 0xC0000000 +#define STM32_DDR_SIZE SZ_1G + +#endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c new file mode 100644 index 0000000000..8f5962a935 --- /dev/null +++ b/arch/arm/mach-stm32mp/spl.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause + */ + +#include <common.h> +#include <dm.h> +#include <spl.h> + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + arch_cpu_init(); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + debug("Clock init failed: %d\n", ret); + return; + } + + ret = uclass_get_device(UCLASS_RESET, 0, &dev); + if (ret) { + debug("Reset init failed: %d\n", ret); + return; + } + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + return; + } + + /* enable console uart printing */ + preloader_console_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 840dbf170d..e80905cf3a 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb +dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb diff --git a/arch/mips/dts/brcm,bcm6318.dtsi b/arch/mips/dts/brcm,bcm6318.dtsi index 54964a7009..015acc9173 100644 --- a/arch/mips/dts/brcm,bcm6318.dtsi +++ b/arch/mips/dts/brcm,bcm6318.dtsi @@ -153,5 +153,35 @@ reg = <0x10004000 0x38>; u-boot,dm-pre-reloc; }; + + ehci: usb-controller@10005000 { + compatible = "brcm,bcm6318-ehci", "generic-ehci"; + reg = <0x10005000 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10005100 { + compatible = "brcm,bcm6318-ohci", "generic-ohci"; + reg = <0x10005100 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10005200 { + compatible = "brcm,bcm6318-usbh"; + reg = <0x10005200 0x30>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6318_CLK_USB>; + clock-names = "usbh"; + power-domains = <&periph_pwr BCM6318_PWR_USB>; + resets = <&periph_rst BCM6318_RST_USBH>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 4d4e36cccc..ade0b49e68 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -183,6 +183,36 @@ status = "disabled"; }; + ehci: usb-controller@10002500 { + compatible = "brcm,bcm63268-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10002600 { + compatible = "brcm,bcm63268-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10002700 { + compatible = "brcm,bcm63268-usbh"; + reg = <0x10002700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM63268_CLK_USBH>, <&timer_clk BCM63268_TCLK_USB_REF>; + clock-names = "usbh", "usb_ref"; + power-domains = <&periph_pwr BCM63268_PWR_USBH>; + resets = <&periph_rst BCM63268_RST_USBH>; + + status = "disabled"; + }; + memory-controller@10003000 { compatible = "brcm,bcm6328-mc"; reg = <0x10003000 0x894>; diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index 67d9278be4..4fbbcec153 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -153,6 +153,36 @@ #power-domain-cells = <1>; }; + ehci: usb-controller@10002500 { + compatible = "brcm,bcm6328-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10002600 { + compatible = "brcm,bcm6328-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10002700 { + compatible = "brcm,bcm6328-usbh"; + reg = <0x10002700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6328_CLK_USBH>; + clock-names = "usbh"; + power-domains = <&periph_pwr BCM6328_PWR_USBH>; + resets = <&periph_rst BCM6328_RST_USBH>; + + status = "disabled"; + }; + memory-controller@10003000 { compatible = "brcm,bcm6328-mc"; reg = <0x10003000 0x864>; diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi index 540b9fea5b..92fb91afc1 100644 --- a/arch/mips/dts/brcm,bcm6348.dtsi +++ b/arch/mips/dts/brcm,bcm6348.dtsi @@ -135,6 +135,26 @@ status = "disabled"; }; + ohci: usb-controller@fffe1b00 { + compatible = "brcm,bcm6348-ohci", "generic-ohci"; + reg = <0xfffe1b00 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@fffe1c00 { + compatible = "brcm,bcm6348-usbh"; + reg = <0xfffe1c00 0x4>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6348_CLK_USBH>; + clock-names = "usbh"; + resets = <&periph_rst BCM6348_RST_USBH>; + + status = "disabled"; + }; + memory-controller@fffe2300 { compatible = "brcm,bcm6338-mc"; reg = <0xfffe2300 0x38>; diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 1662783279..b63b53baee 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -164,5 +164,32 @@ reg = <0xfffe1200 0x4c>; u-boot,dm-pre-reloc; }; + + ehci: usb-controller@fffe1300 { + compatible = "brcm,bcm6358-ehci", "generic-ehci"; + reg = <0xfffe1300 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@fffe1400 { + compatible = "brcm,bcm6358-ohci", "generic-ohci"; + reg = <0xfffe1400 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@fffe1500 { + compatible = "brcm,bcm6358-usbh"; + reg = <0xfffe1500 0x28>; + #phy-cells = <0>; + resets = <&periph_rst BCM6358_RST_USBH>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi new file mode 100644 index 0000000000..f695ec3253 --- /dev/null +++ b/arch/mips/dts/brcm,bcm6362.dtsi @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/clock/bcm6362-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power-domain/bcm6362-power-domain.h> +#include <dt-bindings/reset/bcm6362-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6362"; + + aliases { + spi0 = &lsspi; + spi1 = &hsspi; + }; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6362-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6362-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + }; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000008 { + compatible = "syscon"; + reg = <0x10000008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@1000005c { + compatible = "brcm,bcm6345-wdt"; + reg = <0x1000005c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + gpio1: gpio-controller@10000080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000080 0x4>, <0x10000088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + + status = "disabled"; + }; + + gpio0: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 0x4>, <0x1000008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + lsspi: spi@10000800 { + compatible = "brcm,bcm6358-spi"; + reg = <0x10000800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6362_CLK_SPI>; + resets = <&periph_rst BCM6362_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <8>; + + status = "disabled"; + }; + + hsspi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM6362_RST_SPI>; + spi-max-frequency = <50000000>; + num-cs = <8>; + + status = "disabled"; + }; + + leds: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10001900 0x24>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + periph_pwr: power-controller@10001848 { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x10001848 0x4>; + #power-domain-cells = <1>; + }; + + ehci: usb-controller@10002500 { + compatible = "brcm,bcm6362-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10002600 { + compatible = "brcm,bcm6362-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10002700 { + compatible = "brcm,bcm6368-usbh"; + reg = <0x10002700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6362_CLK_USBH>; + clock-names = "usbh"; + power-domains = <&periph_pwr BCM6362_PWR_USBH>; + resets = <&periph_rst BCM6362_RST_USBH>; + + status = "disabled"; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x864>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/dts/brcm,bcm6368.dtsi b/arch/mips/dts/brcm,bcm6368.dtsi index 1bb538a1f3..fc1c5a244f 100644 --- a/arch/mips/dts/brcm,bcm6368.dtsi +++ b/arch/mips/dts/brcm,bcm6368.dtsi @@ -164,5 +164,34 @@ reg = <0x10001200 0x4c>; u-boot,dm-pre-reloc; }; + + ehci: usb-controller@10001500 { + compatible = "brcm,bcm6368-ehci", "generic-ehci"; + reg = <0x10001500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10001600 { + compatible = "brcm,bcm6368-ohci", "generic-ohci"; + reg = <0x10001600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10001700 { + compatible = "brcm,bcm6368-usbh"; + reg = <0x10001700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6368_CLK_USBH>; + clock-names = "usbh"; + resets = <&periph_rst BCM6368_RST_USBH>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/comtrend,ar-5315u.dts b/arch/mips/dts/comtrend,ar-5315u.dts index 4e4d69b638..af3159a03a 100644 --- a/arch/mips/dts/comtrend,ar-5315u.dts +++ b/arch/mips/dts/comtrend,ar-5315u.dts @@ -21,6 +21,10 @@ }; }; +&ehci { + status = "okay"; +}; + &leds { status = "okay"; @@ -67,6 +71,10 @@ }; }; +&ohci { + status = "okay"; +}; + &spi { status = "okay"; @@ -83,3 +91,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts index 6067881a78..3a97315b3f 100644 --- a/arch/mips/dts/comtrend,ar-5387un.dts +++ b/arch/mips/dts/comtrend,ar-5387un.dts @@ -21,6 +21,10 @@ }; }; +&ehci { + status = "okay"; +}; + &leds { status = "okay"; @@ -51,6 +55,10 @@ }; }; +&ohci { + status = "okay"; +}; + &spi { status = "okay"; @@ -67,3 +75,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts index c909a528a9..74dc09046c 100644 --- a/arch/mips/dts/comtrend,ct-5361.dts +++ b/arch/mips/dts/comtrend,ct-5361.dts @@ -39,6 +39,10 @@ status = "okay"; }; +&ohci { + status = "okay"; +}; + &pflash { status = "okay"; }; @@ -47,3 +51,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts index 54e738c821..9bbecbcdff 100644 --- a/arch/mips/dts/comtrend,vr-3032u.dts +++ b/arch/mips/dts/comtrend,vr-3032u.dts @@ -21,6 +21,10 @@ }; }; +&ehci { + status = "okay"; +}; + &leds { status = "okay"; brcm,serial-leds; @@ -64,7 +68,15 @@ }; }; +&ohci { + status = "okay"; +}; + &uart0 { u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/comtrend,wap-5813n.dts b/arch/mips/dts/comtrend,wap-5813n.dts index 29386e2662..f1f5430b42 100644 --- a/arch/mips/dts/comtrend,wap-5813n.dts +++ b/arch/mips/dts/comtrend,wap-5813n.dts @@ -51,10 +51,18 @@ }; }; +&ehci { + status = "okay"; +}; + &gpio0 { status = "okay"; }; +&ohci { + status = "okay"; +}; + &pflash { status = "okay"; }; @@ -63,3 +71,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts index 31c7d7ed5c..a1e9c15ab9 100644 --- a/arch/mips/dts/huawei,hg556a.dts +++ b/arch/mips/dts/huawei,hg556a.dts @@ -90,10 +90,18 @@ }; }; +&ehci { + status = "okay"; +}; + &gpio0 { status = "okay"; }; +&ohci { + status = "okay"; +}; + &pflash { status = "okay"; }; @@ -102,3 +110,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts new file mode 100644 index 0000000000..8dc7d7ec32 --- /dev/null +++ b/arch/mips/dts/netgear,dgnd3700v2.dts @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6362.dtsi" + +/ { + model = "Netgear DGND3700v2"; + compatible = "netgear,dgnd3700v2", "brcm,bcm6362"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_green { + label = "DGND3700v2:green:inet"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + dsl_green { + label = "DGND3700v2:green:dsl"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + + power_amber { + label = "DGND3700v2:red:power"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&leds { + status = "okay"; + brcm,serial-leds; + brcm,serial-dat-low; + brcm,serial-shift-inv; + brcm,serial-mux; + + led@8 { + reg = <8>; + label = "DGND3700v2:green:power"; + }; + + led@9 { + reg = <9>; + active-low; + label = "DGND3700v2:green:wps"; + }; + + led@10 { + reg = <10>; + active-low; + label = "DGND3700v2:green:usb1"; + }; + + led@11 { + reg = <11>; + active-low; + label = "DGND3700v2:green:usb2"; + }; + + led@12 { + reg = <12>; + active-low; + label = "DGND3700v2:amber:inet"; + }; + + led@13 { + reg = <13>; + active-low; + label = "DGND3700v2:green:ethernet"; + }; + + led@14 { + reg = <14>; + active-low; + label = "DGND3700v2:amber:dsl"; + }; + + led@16 { + reg = <16>; + active-low; + label = "DGND3700v2:amber:usb1"; + }; + + led@17 { + reg = <17>; + active-low; + label = "DGND3700v2:amber:usb2"; + }; + + led@18 { + reg = <18>; + active-low; + label = "DGND3700v2:amber:ethernet"; + }; +}; + +&ohci { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/sfr,nb4-ser.dts b/arch/mips/dts/sfr,nb4-ser.dts index f2092e9f99..473372faa1 100644 --- a/arch/mips/dts/sfr,nb4-ser.dts +++ b/arch/mips/dts/sfr,nb4-ser.dts @@ -50,6 +50,10 @@ }; }; +&ehci { + status = "okay"; +}; + &gpio0 { status = "okay"; }; @@ -83,6 +87,10 @@ }; }; +&ohci { + status = "okay"; +}; + &pflash { status = "okay"; }; @@ -91,3 +99,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index e4a0118368..10900bf604 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -12,6 +12,7 @@ config SYS_SOC default "bcm6348" if SOC_BMIPS_BCM6348 default "bcm6358" if SOC_BMIPS_BCM6358 default "bcm6368" if SOC_BMIPS_BCM6368 + default "bcm6362" if SOC_BMIPS_BCM6362 default "bcm63268" if SOC_BMIPS_BCM63268 choice @@ -94,6 +95,17 @@ config SOC_BMIPS_BCM6368 help This supports BMIPS BCM6368 family including BCM6368 and BCM6369. +config SOC_BMIPS_BCM6362 + bool "BMIPS BCM6362 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6362 family including BCM6361 and BCM6362. + config SOC_BMIPS_BCM63268 bool "BMIPS BCM63268 family" select SUPPORTS_BIG_ENDIAN @@ -188,6 +200,17 @@ config BOARD_NETGEAR_CG3100D ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225 (miniPCIe). +config BOARD_NETGEAR_DGND3700V2 + bool "Netgear DGND3700v2" + depends on SOC_BMIPS_BCM6362 + select BMIPS_SUPPORTS_BOOT_RAM + help + Netgear DGND3700v2 boards have a BCM6362 SoC with 64 MB of RAM and + 32 MB of flash (NAND). + Between its different peripherals there's a BCM53125 switch with 5 + ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and a + BCM43228 (miniPCIe). + config BOARD_SAGEM_FAST1704 bool "Sagem F@ST1704" depends on SOC_BMIPS_BCM6338 @@ -235,6 +258,7 @@ source "board/comtrend/vr3032u/Kconfig" source "board/comtrend/wap5813n/Kconfig" source "board/huawei/hg556a/Kconfig" source "board/netgear/cg3100d/Kconfig" +source "board/netgear/dgnd3700v2/Kconfig" source "board/sagem/f@st1704/Kconfig" source "board/sfr/nb4_ser/Kconfig" diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts index 19dc36fa15..7832efb12f 100644 --- a/arch/nds32/dts/ag101p.dts +++ b/arch/nds32/dts/ag101p.dts @@ -67,5 +67,6 @@ fifo-depth = <0x10>; reg = <0x98e00000 0x1000>; interrupts = <5 4>; + cap-sd-highspeed; }; }; diff --git a/arch/nds32/include/asm/arch-ae3xx/ae3xx.h b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h index b074e8489a..9d55c9784c 100644 --- a/arch/nds32/include/asm/arch-ae3xx/ae3xx.h +++ b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h @@ -44,8 +44,6 @@ #define CONFIG_FTGPIO010_BASE 0xf0700000 /* I2C */ #define CONFIG_FTIIC010_BASE 0xf0a00000 -/* SD Controller */ -#define CONFIG_FTSDC010_BASE 0xf0e00000 /* The following address was not defined in Linux */ diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h index 490f28b62d..0f4c3efbd4 100644 --- a/arch/nds32/include/asm/arch-ag101/ag101.h +++ b/arch/nds32/include/asm/arch-ag101/ag101.h @@ -69,8 +69,6 @@ #define CONFIG_RESERVED_04_BASE 0x98C00000 /* Compat Flash Controller */ #define CONFIG_FTCFC010_BASE 0x98D00000 -/* SD Controller */ -#define CONFIG_FTSDC010_BASE 0x98E00000 /* Synchronous Serial Port Controller (SSP) I2S/AC97 */ #define CONFIG_FTSSP010_02_BASE 0x99400000 diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h b/arch/nds32/include/asm/arch-ag102/ag102.h index c5ee3d9498..a8aef9381f 100644 --- a/arch/nds32/include/asm/arch-ag102/ag102.h +++ b/arch/nds32/include/asm/arch-ag102/ag102.h @@ -56,8 +56,6 @@ #define CONFIG_FTSSP010_01_BASE 0x94100000 /* UART1 - APB STUART Controller (UART0 in Linux) */ #define CONFIG_FTUART010_01_BASE 0x94200000 -/* FTSDC010 SD Controller */ -#define CONFIG_FTSDC010_BASE 0x94400000 /* APB - SSP with HDA/AC97 Controller */ #define CONFIG_FTSSP010_02_BASE 0x94500000 /* UART2 - APB STUART Controller (UART1 in Linux) */ diff --git a/arch/riscv/cpu/nx25/start.S b/arch/riscv/cpu/nx25/start.S index 6a076639d3..cd0a66360d 100644 --- a/arch/riscv/cpu/nx25/start.S +++ b/arch/riscv/cpu/nx25/start.S @@ -45,6 +45,8 @@ trap_vector: .global trap_entry handle_reset: + li t0, CONFIG_SYS_SDRAM_BASE + SREG a2, 0(t0) la t0, trap_entry csrw mtvec, t0 csrwi mstatus, 0 diff --git a/arch/riscv/dts/ae250.dts b/arch/riscv/dts/ae250.dts index 5dc4fb04be..9a38345e36 100644 --- a/arch/riscv/dts/ae250.dts +++ b/arch/riscv/dts/ae250.dts @@ -74,6 +74,7 @@ fifo-depth = <0x10>; reg = <0xf0e00000 0x1000>; interrupts = <17 4>; + cap-sd-highspeed; }; spi: spi@f0b00000 { diff --git a/arch/riscv/include/asm/bootm.h b/arch/riscv/include/asm/bootm.h index 0a644bb58b..9a90f23a22 100644 --- a/arch/riscv/include/asm/bootm.h +++ b/arch/riscv/include/asm/bootm.h @@ -13,53 +13,4 @@ #include <asm/setup.h> -#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ - defined(CONFIG_CMDLINE_TAG) || \ - defined(CONFIG_INITRD_TAG) || \ - defined(CONFIG_SERIAL_TAG) || \ - defined(CONFIG_REVISION_TAG) -# define BOOTM_ENABLE_TAGS 1 -#else -# define BOOTM_ENABLE_TAGS 0 -#endif - -#ifdef CONFIG_SETUP_MEMORY_TAGS -# define BOOTM_ENABLE_MEMORY_TAGS 1 -#else -# define BOOTM_ENABLE_MEMORY_TAGS 0 -#endif - -#ifdef CONFIG_CMDLINE_TAG - #define BOOTM_ENABLE_CMDLINE_TAG 1 -#else - #define BOOTM_ENABLE_CMDLINE_TAG 0 -#endif - -#ifdef CONFIG_INITRD_TAG - #define BOOTM_ENABLE_INITRD_TAG 1 -#else - #define BOOTM_ENABLE_INITRD_TAG 0 -#endif - -#ifdef CONFIG_SERIAL_TAG - #define BOOTM_ENABLE_SERIAL_TAG 1 -void get_board_serial(struct tag_serialnr *serialnr); -#else - #define BOOTM_ENABLE_SERIAL_TAG 0 -static inline void get_board_serial(struct tag_serialnr *serialnr) -{ -} -#endif - -#ifdef CONFIG_REVISION_TAG - #define BOOTM_ENABLE_REVISION_TAG 1 -u32 get_board_rev(void); -#else - #define BOOTM_ENABLE_REVISION_TAG 0 -static inline u32 get_board_rev(void) -{ - return 0; -} -#endif - #endif diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 5ff6d59149..dbf8d45fb7 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -121,7 +121,9 @@ #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) -#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \ +#define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \ + typeof(_PTE) (PTE) = (_PTE); \ + typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \ ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) @@ -151,27 +153,31 @@ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; }) -#define write_csr(reg, val) ({ \ +#define write_csr(reg, _val) ({ \ +typeof(_val) (val) = (_val); \ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ else \ asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) -#define swap_csr(reg, val) ({ unsigned long __tmp; \ +#define swap_csr(reg, _val) ({ unsigned long __tmp; \ +typeof(_val) (val) = (_val); \ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ else \ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ __tmp; }) -#define set_csr(reg, bit) ({ unsigned long __tmp; \ +#define set_csr(reg, _bit) ({ unsigned long __tmp; \ +typeof(_bit) (bit) = (_bit); \ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ else \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ __tmp; }) -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ +#define clear_csr(reg, _bit) ({ unsigned long __tmp; \ +typeof(_bit) (bit) = (_bit); \ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ else \ diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 0cce98ab53..bd352c2cda 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -17,6 +17,6 @@ struct arch_global_data { #include <asm-generic/global_data.h> -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("gp") +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp") #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index e7f63ed8a9..1df6b1b2bf 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -416,19 +416,17 @@ static inline void writesl(unsigned int *addr, const void *data, int longlen) #define eth_io_copy_and_sum(s, c, l, b) \ eth_copy_and_sum((s), __mem_pci(c), (l), (b)) -static inline int -check_signature(unsigned long io_addr, const unsigned char *signature, - int length) +static inline int check_signature(ulong io_addr, const uchar *s, int len) { int retval = 0; do { - if (readb(io_addr) != *signature) + if (readb(io_addr) != *s) goto out; io_addr++; - signature++; - length--; - } while (length); + s++; + len--; + } while (len); retval = 1; out: return retval; @@ -455,18 +453,17 @@ out: eth_copy_and_sum((a), __mem_isa(b), (c), (d)) static inline int -isa_check_signature(unsigned long io_addr, const unsigned char *signature, - int length) +isa_check_signature(ulong io_addr, const uchar *s, int len) { int retval = 0; do { - if (isa_readb(io_addr) != *signature) + if (isa_readb(io_addr) != *s) goto out; io_addr++; - signature++; - length--; - } while (length); + s++; + len--; + } while (len); retval = 1; out: return retval; diff --git a/arch/riscv/include/asm/posix_types.h b/arch/riscv/include/asm/posix_types.h index 6892b66814..7438dbeb03 100644 --- a/arch/riscv/include/asm/posix_types.h +++ b/arch/riscv/include/asm/posix_types.h @@ -69,19 +69,23 @@ typedef struct { #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) #undef __FD_SET -#define __FD_SET(fd, fdsetp) \ +#define __FD_SET(_fd, fdsetp) \ + typeof(_fd) (fd) = (_fd); \ (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1 << (fd & 31))) #undef __FD_CLR -#define __FD_CLR(fd, fdsetp) \ +#define __FD_CLR(_fd, fdsetp) \ + typeof(_fd) (fd) = (_fd); \ (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1 << (fd & 31))) #undef __FD_ISSET -#define __FD_ISSET(fd, fdsetp) \ +#define __FD_ISSET(_fd, fdsetp) \ + typeof(_fd) (fd) = (_fd); \ ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1 << (fd & 31))) != 0) #undef __FD_ZERO -#define __FD_ZERO(fdsetp) \ +#define __FD_ZERO(_fdsetp) \ + typeof(_fdsetp) (fd) = (_fdsetp); \ (memset(fdsetp, 0, sizeof(*(fd_set *)fdsetp))) #endif diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h index 76d68698bb..651078fcfd 100644 --- a/arch/riscv/include/asm/ptrace.h +++ b/arch/riscv/include/asm/ptrace.h @@ -65,8 +65,7 @@ static inline unsigned long instruction_pointer(struct pt_regs *regs) return GET_IP(regs); } -static inline void instruction_pointer_set(struct pt_regs *regs, - unsigned long val) +static inline void instruction_pointer_set(struct pt_regs *regs, ulong val) { SET_IP(regs, val); } @@ -82,8 +81,7 @@ static inline unsigned long user_stack_pointer(struct pt_regs *regs) return GET_USP(regs); } -static inline void user_stack_pointer_set(struct pt_regs *regs, - unsigned long val) +static inline void user_stack_pointer_set(struct pt_regs *regs, ulong val) { SET_USP(regs, val); } @@ -97,8 +95,7 @@ static inline unsigned long frame_pointer(struct pt_regs *regs) return GET_FP(regs); } -static inline void frame_pointer_set(struct pt_regs *regs, - unsigned long val) +static inline void frame_pointer_set(struct pt_regs *regs, ulong val) { SET_FP(regs, val); } diff --git a/arch/riscv/include/asm/setup.h b/arch/riscv/include/asm/setup.h index 731b0d96aa..4b182432f1 100644 --- a/arch/riscv/include/asm/setup.h +++ b/arch/riscv/include/asm/setup.h @@ -145,14 +145,18 @@ struct tagtable { int (*parse)(const struct tag *); }; -#define tag_member_present(tag, member) \ +#define tag_member_present(_tag, member) \ + typeof(_tag) (tag) = (_tag); \ ((unsigned long)(&((struct tag *)0L)->member + 1) \ <= (tag)->hdr.size * 4) -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_next(_t) \ + typeof(_t) (t) = (_t); \ + ((struct tag *)((u32 *)(t) + (t)->hdr.size)) #define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) -#define for_each_tag(t, base) \ +#define for_each_tag(_t, base) \ + typeof(_t) (t) = (_t); \ for (t = base; t->hdr.size; t = tag_next(t)) #ifdef __KERNEL__ diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h index 038cdaea72..0fc3424a2f 100644 --- a/arch/riscv/include/asm/string.h +++ b/arch/riscv/include/asm/string.h @@ -26,8 +26,11 @@ #undef __HAVE_ARCH_MEMSET #ifdef CONFIG_MARCO_MEMSET -#define memset(p, v, n) \ - ({ \ +#define memset(_p, _v, _n) \ + (typeof(_p) (p) = (_p); \ + typeof(_v) (v) = (_v); \ + typeof(_n) (n) = (_n); \ + { \ if ((n) != 0) { \ if (__builtin_constant_p((v)) && (v) == 0) \ __memzero((p), (n)); \ @@ -37,7 +40,10 @@ (p); \ }) -#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); }) +#define memzero(_p, _n) \ + (typeof(_p) (p) = (_p); \ + typeof(_n) (n) = (_n); \ + { if ((n) != 0) __memzero((p), (n)); (p); }) #endif #endif /* __ASM_RISCV_STRING_H */ diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 44ce38b614..9242fa891a 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -21,36 +21,12 @@ int arch_fixup_fdt(void *blob) return 0; } -#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ - defined(CONFIG_CMDLINE_TAG) || \ - defined(CONFIG_INITRD_TAG) || \ - defined(CONFIG_SERIAL_TAG) || \ - defined(CONFIG_REVISION_TAG) -static void setup_start_tag(bd_t *bd); - -# ifdef CONFIG_SETUP_MEMORY_TAGS -static void setup_memory_tags(bd_t *bd); -# endif -static void setup_commandline_tag(bd_t *bd, char *commandline); - -# ifdef CONFIG_INITRD_TAG -static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end); -# endif -static void setup_end_tag(bd_t *bd); - -static struct tag *params; -#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ - int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { bd_t *bd = gd->bd; char *s; int machid = bd->bi_arch_number; - void (*theKernel)(int zero, int arch, uint params); - -#ifdef CONFIG_CMDLINE_TAG - char *commandline = env_get("bootargs"); -#endif + void (*theKernel)(int arch, uint params); /* * allow the PREP bootm subcommand, it is required for bootm to work @@ -61,7 +37,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; - theKernel = (void (*)(int, int, uint))images->ep; + theKernel = (void (*)(int, uint))images->ep; s = env_get("machid"); if (s) { @@ -82,167 +58,16 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) hang(); } #endif - } else if (BOOTM_ENABLE_TAGS) { -#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ - defined(CONFIG_CMDLINE_TAG) || \ - defined(CONFIG_INITRD_TAG) || \ - defined(CONFIG_SERIAL_TAG) || \ - defined(CONFIG_REVISION_TAG) - setup_start_tag(bd); -#ifdef CONFIG_SERIAL_TAG - setup_serial_tag(¶ms); -#endif -#ifdef CONFIG_REVISION_TAG - setup_revision_tag(¶ms); -#endif -#ifdef CONFIG_SETUP_MEMORY_TAGS - setup_memory_tags(bd); -#endif -#ifdef CONFIG_CMDLINE_TAG - setup_commandline_tag(bd, commandline); -#endif -#ifdef CONFIG_INITRD_TAG - if (images->rd_start && images->rd_end) - setup_initrd_tag(bd, images->rd_start, images->rd_end); -#endif - setup_end_tag(bd); -#endif + } /* we assume that the kernel is in place */ printf("\nStarting kernel ...\n\n"); -#ifdef CONFIG_USB_DEVICE - { - extern void udc_disconnect(void); - udc_disconnect(); - } -#endif - } cleanup_before_linux(); if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) - theKernel(0, machid, (unsigned long)images->ft_addr); - else - theKernel(0, machid, bd->bi_boot_params); + theKernel(machid, (unsigned long)images->ft_addr); + /* does not return */ return 1; } - -#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ - defined(CONFIG_CMDLINE_TAG) || \ - defined(CONFIG_INITRD_TAG) || \ - defined(CONFIG_SERIAL_TAG) || \ - defined(CONFIG_REVISION_TAG) -static void setup_start_tag(bd_t *bd) -{ - params = (struct tag *)bd->bi_boot_params; - - params->hdr.tag = ATAG_CORE; - params->hdr.size = tag_size(tag_core); - - params->u.core.flags = 0; - params->u.core.pagesize = 0; - params->u.core.rootdev = 0; - - params = tag_next(params); -} - -#ifdef CONFIG_SETUP_MEMORY_TAGS -static void setup_memory_tags(bd_t *bd) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - params->hdr.tag = ATAG_MEM; - params->hdr.size = tag_size(tag_mem32); - - params->u.mem.start = bd->bi_dram[i].start; - params->u.mem.size = bd->bi_dram[i].size; - - params = tag_next(params); - } -} -#endif /* CONFIG_SETUP_MEMORY_TAGS */ - -static void setup_commandline_tag(bd_t *bd, char *commandline) -{ - char *p; - - if (!commandline) - return; - - /* eat leading white space */ - for (p = commandline; *p == ' '; p++) - ; - - /* skip non-existent command lines so the kernel will still - * use its default command line. - */ - if (*p == '\0') - return; - - params->hdr.tag = ATAG_CMDLINE; - params->hdr.size = - (sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2; - - strcpy(params->u.cmdline.cmdline, p) - ; - - params = tag_next(params); -} - -#ifdef CONFIG_INITRD_TAG -static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end) -{ - /* an ATAG_INITRD node tells the kernel where the compressed - * ramdisk can be found. ATAG_RDIMG is a better name, actually. - */ - params->hdr.tag = ATAG_INITRD2; - params->hdr.size = tag_size(tag_initrd); - - params->u.initrd.start = initrd_start; - params->u.initrd.size = initrd_end - initrd_start; - - params = tag_next(params); -} -#endif /* CONFIG_INITRD_TAG */ - -#ifdef CONFIG_SERIAL_TAG -void setup_serial_tag(struct tag **tmp) -{ - struct tag *params; - struct tag_serialnr serialnr; - void get_board_serial(struct tag_serialnr *serialnr); - - params = *tmp; - get_board_serial(&serialnr); - params->hdr.tag = ATAG_SERIAL; - params->hdr.size = tag_size(tag_serialnr); - params->u.serialnr.low = serialnr.low; - params->u.serialnr.high = serialnr.high; - params = tag_next(params); - *tmp = params; -} -#endif - -#ifdef CONFIG_REVISION_TAG -void setup_revision_tag(struct tag **in_params) -{ - u32 rev; - u32 get_board_rev(void); - - rev = get_board_rev(); - params->hdr.tag = ATAG_REVISION; - params->hdr.size = tag_size(tag_revision); - params->u.revision.rev = rev; - params = tag_next(params); -} -#endif /* CONFIG_REVISION_TAG */ - -static void setup_end_tag(bd_t *bd) -{ - params->hdr.tag = ATAG_NONE; - params->hdr.size = 0; -} - -#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 075db8ba46..923f75275b 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -63,7 +63,7 @@ __attribute__((weak)) void timer_interrupt(struct pt_regs *regs) static void _exit_trap(int code, uint epc, struct pt_regs *regs) { - static const char *exception_code[] = { + static const char * const exception_code[] = { "Instruction address misaligned", "Instruction access fault", "Illegal instruction", diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index b0f0ca8f19..06d0e8ce85 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -27,6 +27,10 @@ testfdt3 = "/b-test"; testfdt5 = "/some-bus/c-test@5"; testfdt8 = "/a-test"; + fdt_dummy0 = "/translation-test@8000/dev@0,0"; + fdt_dummy1 = "/translation-test@8000/dev@1,100"; + fdt_dummy2 = "/translation-test@8000/dev@2,200"; + fdt_dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42"; usb0 = &usb_0; usb1 = &usb_1; usb2 = &usb_2; @@ -487,6 +491,50 @@ reg = <9 1>; }; }; + + translation-test@8000 { + compatible = "simple-bus"; + reg = <0x8000 0x4000>; + + #address-cells = <0x2>; + #size-cells = <0x1>; + + ranges = <0 0x0 0x8000 0x1000 + 1 0x100 0x9000 0x1000 + 2 0x200 0xA000 0x1000 + 3 0x300 0xB000 0x1000 + >; + + dev@0,0 { + compatible = "denx,u-boot-fdt-dummy"; + reg = <0 0x0 0x1000>; + }; + + dev@1,100 { + compatible = "denx,u-boot-fdt-dummy"; + reg = <1 0x100 0x1000>; + + }; + + dev@2,200 { + compatible = "denx,u-boot-fdt-dummy"; + reg = <2 0x200 0x1000>; + }; + + + noxlatebus@3,300 { + compatible = "simple-bus"; + reg = <3 0x300 0x1000>; + + #address-cells = <0x1>; + #size-cells = <0x0>; + + dev@42 { + compatible = "denx,u-boot-fdt-dummy"; + reg = <0x42>; + }; + }; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h index 90768a99ce..6aba614361 100644 --- a/arch/x86/include/asm/bootparam.h +++ b/arch/x86/include/asm/bootparam.h @@ -10,8 +10,11 @@ #include <asm/video/edid.h> /* setup data types */ -#define SETUP_NONE 0 -#define SETUP_E820_EXT 1 +enum { + SETUP_NONE = 0, + SETUP_E820_EXT, + SETUP_DTB, +}; /* extensible setup data list node */ struct setup_data { diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 2a82bc83d6..6af1bf4678 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -14,6 +14,7 @@ */ #include <common.h> +#include <malloc.h> #include <asm/acpi_table.h> #include <asm/io.h> #include <asm/ptrace.h> @@ -25,6 +26,7 @@ #include <asm/arch/timestamp.h> #endif #include <linux/compiler.h> +#include <linux/libfdt.h> DECLARE_GLOBAL_DATA_PTR; @@ -95,6 +97,38 @@ static int get_boot_protocol(struct setup_header *hdr) } } +static int setup_device_tree(struct setup_header *hdr, const void *fdt_blob) +{ + int bootproto = get_boot_protocol(hdr); + struct setup_data *sd; + int size; + + if (bootproto < 0x0209) + return -ENOTSUPP; + + if (!fdt_blob) + return 0; + + size = fdt_totalsize(fdt_blob); + if (size < 0) + return -EINVAL; + + size += sizeof(struct setup_data); + sd = (struct setup_data *)malloc(size); + if (!sd) { + printf("Not enough memory for DTB setup data\n"); + return -ENOMEM; + } + + sd->next = hdr->setup_data; + sd->type = SETUP_DTB; + sd->len = fdt_totalsize(fdt_blob); + memcpy(sd->data, fdt_blob, sd->len); + hdr->setup_data = (unsigned long)sd; + + return 0; +} + struct boot_params *load_zimage(char *image, unsigned long kernel_size, ulong *load_addressp) { @@ -261,6 +295,7 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, hdr->acpi_rsdp_addr = acpi_get_rsdp_addr(); #endif + setup_device_tree(hdr, (const void *)env_get_hex("fdtaddr", 0)); setup_video(&setup_base->screen_info); return 0; |