diff options
Diffstat (limited to 'arch')
88 files changed, 1891 insertions, 564 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index ae9c93ed7b..91e049b322 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -96,6 +96,7 @@ config SANDBOX select DM_SPI_FLASH select HAVE_BLOCK_DEVICE select LZO + select OF_BOARD_SETUP select PCI_ENDPOINT select SPI select SUPPORT_OF_CONTROL diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts index 34ef3a620a..cf2ce8a1f6 100644 --- a/arch/arc/dts/hsdk.dts +++ b/arch/arc/dts/hsdk.dts @@ -6,6 +6,7 @@ #include "skeleton.dtsi" #include "dt-bindings/clock/snps,hsdk-cgu.h" +#include "dt-bindings/reset/snps,hsdk-reset.h" / { model = "snps,hsdk"; @@ -62,6 +63,12 @@ #clock-cells = <1>; }; + cgu_rst: reset-controller@f00008a0 { + compatible = "snps,hsdk-reset"; + #reset-cells = <1>; + reg = <0xf00008a0 0x4>, <0xf0000ff0 0x4>; + }; + uart0: serial0@f0005000 { compatible = "snps,dw-apb-uart"; reg = <0xf0005000 0x1000>; diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 0fdcf2d2dd..ab61846b5a 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -40,6 +40,13 @@ static const inline int is_ioc_enabled(void) return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE); } +/* + * We export SLC control functions to use them in platform configuration code. + * They maust not be used in any generic code! + */ +void slc_enable(void); +void slc_disable(void); + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARC_CACHE_H */ diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 1340776c66..8a1d67870a 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -89,8 +89,7 @@ * * [ NOTE 2 ]: * As of today we only support the following cache configurations on ARC. - * Other configurations may exist in HW (for example, since version 3.0 HS - * supports SL$ (L2 system level cache) disable) but we don't support it in SW. + * Other configurations may exist in HW but we don't support it in SW. * Configuration 1: * ______________________ * | | @@ -120,7 +119,8 @@ * | | * | L2 (SL$) | * |______________________| - * always must be on + * always on (ARCv2, HS < 3.0) + * on/off (ARCv2, HS >= 3.0) * ___|______________|____ * | | * | main memory | @@ -178,6 +178,8 @@ DECLARE_GLOBAL_DATA_PTR; static inlined_cachefunc void __ic_entire_invalidate(void); static inlined_cachefunc void __dc_entire_op(const int cacheop); +static inlined_cachefunc void __slc_entire_op(const int op); +static inlined_cachefunc bool ioc_enabled(void); static inline bool pae_exists(void) { @@ -238,6 +240,70 @@ static inlined_cachefunc bool slc_exists(void) return false; } +enum slc_dis_status { + ST_SLC_MISSING = 0, + ST_SLC_NO_DISABLE_CTRL, + ST_SLC_DISABLE_CTRL +}; + +/* + * ARCv1 -> ST_SLC_MISSING + * ARCv2 && SLC absent -> ST_SLC_MISSING + * ARCv2 && SLC exists && SLC version <= 2 -> ST_SLC_NO_DISABLE_CTRL + * ARCv2 && SLC exists && SLC version > 2 -> ST_SLC_DISABLE_CTRL + */ +static inlined_cachefunc enum slc_dis_status slc_disable_supported(void) +{ + if (is_isa_arcv2()) { + union bcr_generic sbcr; + + sbcr.word = read_aux_reg(ARC_BCR_SLC); + if (sbcr.fields.ver == 0) + return ST_SLC_MISSING; + else if (sbcr.fields.ver <= 2) + return ST_SLC_NO_DISABLE_CTRL; + else + return ST_SLC_DISABLE_CTRL; + } + + return ST_SLC_MISSING; +} + +static inlined_cachefunc bool __slc_enabled(void) +{ + return !(read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_DIS); +} + +static inlined_cachefunc void __slc_enable(void) +{ + unsigned int ctrl; + + ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); + ctrl &= ~SLC_CTRL_DIS; + write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); +} + +static inlined_cachefunc void __slc_disable(void) +{ + unsigned int ctrl; + + ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); + ctrl |= SLC_CTRL_DIS; + write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); +} + +static inlined_cachefunc bool slc_enabled(void) +{ + enum slc_dis_status slc_status = slc_disable_supported(); + + if (slc_status == ST_SLC_MISSING) + return false; + else if (slc_status == ST_SLC_NO_DISABLE_CTRL) + return true; + else + return __slc_enabled(); +} + static inlined_cachefunc bool slc_data_bypass(void) { /* @@ -247,7 +313,40 @@ static inlined_cachefunc bool slc_data_bypass(void) return !dcache_enabled(); } -static inline bool ioc_exists(void) +void slc_enable(void) +{ + if (slc_disable_supported() != ST_SLC_DISABLE_CTRL) + return; + + if (__slc_enabled()) + return; + + __slc_enable(); +} + +/* TODO: warn if we are not able to disable SLC */ +void slc_disable(void) +{ + if (slc_disable_supported() != ST_SLC_DISABLE_CTRL) + return; + + /* we don't support SLC disabling if we use IOC */ + if (ioc_enabled()) + return; + + if (!__slc_enabled()) + return; + + /* + * We need to flush L1D$ to guarantee that we won't have any + * writeback operations during SLC disabling. + */ + __dc_entire_op(OP_FLUSH); + __slc_entire_op(OP_FLUSH_N_INV); + __slc_disable(); +} + +static inlined_cachefunc bool ioc_exists(void) { if (is_isa_arcv2()) { union bcr_clust_cfg cbcr; @@ -259,7 +358,7 @@ static inline bool ioc_exists(void) return false; } -static inline bool ioc_enabled(void) +static inlined_cachefunc bool ioc_enabled(void) { /* * We check only CONFIG option instead of IOC HW state check as IOC @@ -275,7 +374,7 @@ static inlined_cachefunc void __slc_entire_op(const int op) { unsigned int ctrl; - if (!slc_exists()) + if (!slc_enabled()) return; ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); @@ -324,7 +423,7 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) unsigned int ctrl; unsigned long end; - if (!slc_exists()) + if (!slc_enabled()) return; /* @@ -382,6 +481,9 @@ static void arc_ioc_setup(void) if (!slc_exists()) panic("Try to enable IOC but SLC is not present"); + if (!slc_enabled()) + panic("Try to enable IOC but SLC is disabled"); + /* Unsupported configuration. See [ NOTE 2 ] for more details. */ if (!dcache_enabled()) panic("Try to enable IOC but L1 D$ is disabled"); @@ -517,8 +619,6 @@ void invalidate_icache_all(void) /* * If SL$ is bypassed for data it is used only for instructions, * so we need to invalidate it too. - * TODO: HS 3.0 supports SLC disable so we need to check slc - * enable/disable status here. */ if (is_isa_arcv2() && slc_data_bypass()) __slc_entire_op(OP_INV); diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index eee4538c7e..33b484753c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1587,6 +1587,7 @@ config ARCH_STI config ARCH_STM32MP bool "Support STMicroelectronics STM32MP Socs with cortex A" select ARCH_MISC_INIT + select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT select CLK select DM diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6d1e8668e7..bb979550c4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -620,12 +620,14 @@ dtb-y += \ imx6dl-icore.dtb \ imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ + imx6dl-mba6a.dtb \ + imx6dl-mba6b.dtb \ imx6dl-mamoj.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-pico.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ - imx6dl-wandboard-revb1.dtb \ + imx6dl-wandboard-revd1.dtb \ endif @@ -649,6 +651,8 @@ dtb-y += \ imx6q-icore-rqs.dtb \ imx6q-kp.dtb \ imx6q-logicpd.dtb \ + imx6q-mba6a.dtb \ + imx6q-mba6b.dtb \ imx6q-mccmon6.dtb\ imx6q-nitrogen6x.dtb \ imx6q-novena.dtb \ @@ -657,7 +661,7 @@ dtb-y += \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ imx6q-tbs2910.dtb \ - imx6q-wandboard-revb1.dtb \ + imx6q-wandboard-revd1.dtb \ imx6qp-sabreauto.dtb \ imx6qp-sabresd.dtb \ imx6qp-wandboard-revd1.dtb \ @@ -728,7 +732,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-evk.dtb \ imx8mp-evk.dtb -dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb +dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ + imxrt1020-evk.dtb dtb-$(CONFIG_RCAR_GEN2) += \ r8a7790-lager-u-boot.dtb \ diff --git a/arch/arm/dts/am335x-guardian.dts b/arch/arm/dts/am335x-guardian.dts index 5ed2133e78..7e70a96d25 100644 --- a/arch/arm/dts/am335x-guardian.dts +++ b/arch/arm/dts/am335x-guardian.dts @@ -58,7 +58,7 @@ label = "guardian:life-led"; gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; - default-state = "off"; + default-state = "on"; }; }; @@ -202,8 +202,33 @@ }; partition@6 { + label = "u-boot-2"; + reg = <0x300000 0x100000>; + }; + + partition@7 { + label = "u-boot-2.backup1"; + reg = <0x400000 0x100000>; + }; + + partition@8 { + label = "u-boot-env"; + reg = <0x500000 0x40000>; + }; + + partition@9 { + label = "u-boot-env.backup1"; + reg = <0x540000 0x40000>; + }; + + partition@10 { + label = "splash-screen"; + reg = <0x580000 0x40000>; + }; + + partition@11 { label = "UBI"; - reg = <0x300000 0x1fd00000>; + reg = <0x5c0000 0x1fa40000>; }; }; }; diff --git a/arch/arm/dts/imx53-kp-u-boot.dtsi b/arch/arm/dts/imx53-kp-u-boot.dtsi index acab9b3657..a112db9d1a 100644 --- a/arch/arm/dts/imx53-kp-u-boot.dtsi +++ b/arch/arm/dts/imx53-kp-u-boot.dtsi @@ -5,6 +5,13 @@ * SPDX-License-Identifier: GPL-2.0+ or X11 */ +&fec { + fixed-link { /* RMII fixed link for both HSC|DDC */ + speed = <100>; + full-duplex; + }; +}; + &pmic { u-boot,i2c-transaction-bytes = <3>; }; diff --git a/arch/arm/dts/imx6dl-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx6dl-dhcom-pdk2-u-boot.dtsi new file mode 100644 index 0000000000..fc7dffea2a --- /dev/null +++ b/arch/arm/dts/imx6dl-dhcom-pdk2-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+) +/* + * Copyright (C) 2020 Harald Seiler <hws@denx.de> + */ + +#include "imx6qdl-dhcom-pdk2-u-boot.dtsi" diff --git a/arch/arm/dts/imx6dl-mba6.dtsi b/arch/arm/dts/imx6dl-mba6.dtsi new file mode 100644 index 0000000000..d74adf2b28 --- /dev/null +++ b/arch/arm/dts/imx6dl-mba6.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +ðphy { + rxdv-skew-ps = <180>; + txen-skew-ps = <0>; + rxd3-skew-ps = <180>; + rxd2-skew-ps = <180>; + rxd1-skew-ps = <180>; + rxd0-skew-ps = <180>; + txd3-skew-ps = <120>; + txd2-skew-ps = <0>; + txd1-skew-ps = <300>; + txd0-skew-ps = <120>; + txc-skew-ps = <1860>; + rxc-skew-ps = <1860>; +}; diff --git a/arch/arm/dts/imx6dl-mba6a.dts b/arch/arm/dts/imx6dl-mba6a.dts new file mode 100644 index 0000000000..fc9cc2c056 --- /dev/null +++ b/arch/arm/dts/imx6dl-mba6a.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx6dl-tqma6a.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6a.dtsi" +#include "imx6dl-mba6.dtsi" + +/ { + model = "TQ TQMa6S on MBa6x"; + compatible = "tq,mba6a", "tq,tqma6dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-mba6b.dts b/arch/arm/dts/imx6dl-mba6b.dts new file mode 100644 index 0000000000..a3c8d9d4c6 --- /dev/null +++ b/arch/arm/dts/imx6dl-mba6b.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx6dl-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6dl-mba6.dtsi" + +/ { + model = "TQ TQMa6S on MBa6x"; + compatible = "tq,mba6b", "tq,tqma6dl", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6dl-tqma6a.dtsi b/arch/arm/dts/imx6dl-tqma6a.dtsi new file mode 100644 index 0000000000..df87b381ca --- /dev/null +++ b/arch/arm/dts/imx6dl-tqma6a.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +#include "imx6dl.dtsi" +#include "imx6qdl-tqma6a.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory { + reg = <0x10000000 0x20000000>; + }; +}; + diff --git a/arch/arm/dts/imx6dl-tqma6b.dtsi b/arch/arm/dts/imx6dl-tqma6b.dtsi new file mode 100644 index 0000000000..47ffbc4d95 --- /dev/null +++ b/arch/arm/dts/imx6dl-tqma6b.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +#include "imx6dl.dtsi" +#include "imx6qdl-tqma6b.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory { + reg = <0x10000000 0x20000000>; + }; +}; + diff --git a/arch/arm/dts/imx6dl-wandboard-revb1.dts b/arch/arm/dts/imx6dl-wandboard-revd1.dts index c2946fbaa0..6d1d863c2e 100644 --- a/arch/arm/dts/imx6dl-wandboard-revb1.dts +++ b/arch/arm/dts/imx6dl-wandboard-revd1.dts @@ -6,10 +6,10 @@ */ /dts-v1/; #include "imx6dl.dtsi" -#include "imx6qdl-wandboard-revb1.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" / { - model = "Wandboard i.MX6 Dual Lite Board rev B1"; + model = "Wandboard i.MX6 Dual Lite Board revD1"; compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; memory@10000000 { diff --git a/arch/arm/dts/imx6q-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx6q-dhcom-pdk2-u-boot.dtsi index b94231edb3..026342df5a 100644 --- a/arch/arm/dts/imx6q-dhcom-pdk2-u-boot.dtsi +++ b/arch/arm/dts/imx6q-dhcom-pdk2-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2019 Claudius Heine <ch@denx.de> */ +#include "imx6qdl-dhcom-pdk2-u-boot.dtsi" + / { wdt-reboot { compatible = "wdt-reboot"; diff --git a/arch/arm/dts/imx6q-mba6.dtsi b/arch/arm/dts/imx6q-mba6.dtsi new file mode 100644 index 0000000000..76e8410f8e --- /dev/null +++ b/arch/arm/dts/imx6q-mba6.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +ðphy { + rxdv-skew-ps = <180>; + txen-skew-ps = <120>; + rxd3-skew-ps = <180>; + rxd2-skew-ps = <180>; + rxd1-skew-ps = <180>; + rxd0-skew-ps = <180>; + txd3-skew-ps = <120>; + txd2-skew-ps = <0>; + txd1-skew-ps = <180>; + txd0-skew-ps = <360>; + txc-skew-ps = <1860>; + rxc-skew-ps = <1860>; +}; diff --git a/arch/arm/dts/imx6q-mba6a.dts b/arch/arm/dts/imx6q-mba6a.dts new file mode 100644 index 0000000000..7983ad94f8 --- /dev/null +++ b/arch/arm/dts/imx6q-mba6a.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx6q-tqma6a.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6a.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6Q on MBa6x"; + compatible = "tq,mba6a", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6q-mba6b.dts b/arch/arm/dts/imx6q-mba6b.dts new file mode 100644 index 0000000000..9d117dd190 --- /dev/null +++ b/arch/arm/dts/imx6q-mba6b.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx6q-tqma6b.dtsi" +#include "imx6qdl-mba6.dtsi" +#include "imx6qdl-mba6b.dtsi" +#include "imx6q-mba6.dtsi" + +/ { + model = "TQ TQMa6Q on MBa6x"; + compatible = "tq,mba6b", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6q-tqma6a.dtsi b/arch/arm/dts/imx6q-tqma6a.dtsi new file mode 100644 index 0000000000..b252077f49 --- /dev/null +++ b/arch/arm/dts/imx6q-tqma6a.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +#include "imx6q.dtsi" +#include "imx6qdl-tqma6a.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory { + reg = <0x10000000 0x40000000>; + }; +}; + diff --git a/arch/arm/dts/imx6q-tqma6b.dtsi b/arch/arm/dts/imx6q-tqma6b.dtsi new file mode 100644 index 0000000000..107a9eb037 --- /dev/null +++ b/arch/arm/dts/imx6q-tqma6b.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +#include "imx6q.dtsi" +#include "imx6qdl-tqma6b.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory { + reg = <0x10000000 0x40000000>; + }; +}; + diff --git a/arch/arm/dts/imx6q-wandboard-revb1.dts b/arch/arm/dts/imx6q-wandboard-revd1.dts index f6ccbecff9..55331021d8 100644 --- a/arch/arm/dts/imx6q-wandboard-revb1.dts +++ b/arch/arm/dts/imx6q-wandboard-revd1.dts @@ -6,10 +6,10 @@ */ /dts-v1/; #include "imx6q.dtsi" -#include "imx6qdl-wandboard-revb1.dtsi" +#include "imx6qdl-wandboard-revd1.dtsi" / { - model = "Wandboard i.MX6 Quad Board rev B1"; + model = "Wandboard i.MX6 Quad Board revD1"; compatible = "wand,imx6q-wandboard", "fsl,imx6q"; memory@10000000 { diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi new file mode 100644 index 0000000000..32128d4d2a --- /dev/null +++ b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+) +/* + * Copyright (C) 2020 Harald Seiler <hws@denx.de> + */ + +#include "imx6qdl-dhcom-u-boot.dtsi" + +/ { + fec_vio: regulator-fec { + compatible = "regulator-fixed"; + + regulator-name = "fec-vio"; + gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; +}; + +&fec { + phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-reset-post-delay = <10>; + + phy-supply = <&fec_vio>; +}; diff --git a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi new file mode 100644 index 0000000000..4c3b5e82d6 --- /dev/null +++ b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+) +/* + * Copyright (C) 2020 Harald Seiler <hws@denx.de> + */ + +®_usb_otg_vbus { + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/arch/arm/dts/imx6qdl-mba6.dtsi b/arch/arm/dts/imx6qdl-mba6.dtsi new file mode 100644 index 0000000000..874b68564a --- /dev/null +++ b/arch/arm/dts/imx6qdl-mba6.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +/ { + aliases { + mmc1 = &usdhc2; + }; + + chosen { + linux,stdout-path = &uart2; + stdout-path = &uart2; + }; + + regulators { + reg_mba6_3p3v: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6-3p3v"; + reg = <1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_otgvbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_otgpwr>; + regulator-name = "otg-vbus-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin_supply = <®_3p3v>; + }; + }; +}; + +&fec { + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-reset-post-delay = <100>; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + force-master; + max-speed = <1000>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + mba6 { + pinctrl_enet: enetgrp { + fsl,pins = < + /* FEC phy IRQ */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008 + /* FEC phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099 + /* DSE = 100, 100k up, SPEED = MED */ + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0 + /* DSE = 111, pull 100k up */ + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038 + /* DSE = 111, pull external */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038 + /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b099 /* LCD.PWR_EN */ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0001b099 /* LCD.RESET */ + /* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 + + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099 + + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099 + + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099 + + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099 + + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099 + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099 + + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099 + >; + }; + + pinctrl_reg_otgpwr: regotgpwrgrp { + fsl,pins = < + /* OTG_PWR */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b099 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */ + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071 + /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */ + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059 + + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059 + >; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + vbus-supply = <®_otgvbus>; + status = "okay"; +}; + +&usdhc2 { /* Baseboard Slot */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_mba6_3p3v>; + bus-width = <4>; + no-1-8-v; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qdl-mba6a.dtsi b/arch/arm/dts/imx6qdl-mba6a.dtsi new file mode 100644 index 0000000000..d8b4d00d85 --- /dev/null +++ b/arch/arm/dts/imx6qdl-mba6a.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; +}; + +&i2c1 { + sensor1: lm75@49 { + compatible = "lm75"; + reg = <0x49>; + }; + + eeprom1: m24c64@57 { + compatible = "st,24c64", "at24"; + reg = <0x57>; + pagesize = <32>; + }; + + rtc1: ds1339@68 { + compatible = "ds1339"; + reg = <0x68>; + }; +}; + +&iomuxc { + mba6 { + pinctrl_enet_fix: enetfixgrp { + fsl,pins = < + /* ENET ping patch */ + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6qdl-mba6b.dtsi b/arch/arm/dts/imx6qdl-mba6b.dtsi new file mode 100644 index 0000000000..7489b48d82 --- /dev/null +++ b/arch/arm/dts/imx6qdl-mba6b.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + sensor1: lm75@49 { + compatible = "lm75"; + reg = <0x49>; + }; + + eeprom1: m24c64@57 { + compatible = "st,24c64", "at24"; + reg = <0x57>; + pagesize = <32>; + }; + + rtc1: ds1339@68 { + compatible = "ds1339"; + reg = <0x68>; + }; +}; + +&iomuxc { + mba6 { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 + >; + }; + }; + +}; diff --git a/arch/arm/dts/imx6qdl-tqma6.dtsi b/arch/arm/dts/imx6qdl-tqma6.dtsi new file mode 100644 index 0000000000..85eb3d8da1 --- /dev/null +++ b/arch/arm/dts/imx6qdl-tqma6.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +/ { + aliases { + mmc0 = &usdhc3; + /delete-property/ mmc1; + /delete-property/ mmc2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "supply-3p3v"; + reg = <0>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + status = "okay"; + + flash: m25p80@0 { + status = "okay"; + compatible = "micron,n25q128a13", "n25q128a13"; + spi-max-frequency = <50000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + }; +}; + +&iomuxc { + tqma6 { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099 + /* eCSPI1 SS1 */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099 + >; + }; + + pinctrl_i2c1_tqma6: i2c1-tqma6grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 + >; + }; + + pinctrl_i2c3_tqma6: i2c3-tqma6grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + }; +}; + +&pmic { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio6>; + interrupts = <10 8>; + + regulators { + reg_vddcore: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_vddsoc: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_gen_3v3: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_ddr_1v5a: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_1v5b: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v_600mA: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-always-on; + }; + + reg_snvs_3v: vsnvs { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vgen1_1v5: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vgen2_1v2_eth: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + reg_vgen3_2v8: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen4_1v8: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen5_1v8_eth: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen6_3v3: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + non-removable; + disable-wp; + bus-width = <8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mmccard: mmccard@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/dts/imx6qdl-tqma6a.dtsi b/arch/arm/dts/imx6qdl-tqma6a.dtsi new file mode 100644 index 0000000000..f94a5d80c2 --- /dev/null +++ b/arch/arm/dts/imx6qdl-tqma6a.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_tqma6>; + clock-frequency = <100000>; + status = "okay"; + + pmic: pf0100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + }; + + sensor0: lm75@48 { + compatible = "lm75"; + reg = <0x48>; + }; + + eeprom0: m24c64@50 { + compatible = "st,24c64", "at24"; + reg = <0x50>; + pagesize = <32>; + }; +}; + diff --git a/arch/arm/dts/imx6qdl-tqma6b.dtsi b/arch/arm/dts/imx6qdl-tqma6b.dtsi new file mode 100644 index 0000000000..682f553701 --- /dev/null +++ b/arch/arm/dts/imx6qdl-tqma6b.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2020 TQ-Systems GmbH + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_tqma6>; + clock-frequency = <100000>; + status = "okay"; + + pmic: pf0100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + }; + + sensor0: lm75@48 { + compatible = "lm75"; + reg = <0x48>; + }; + + eeprom0: m24c64@50 { + compatible = "st,24c64", "at24"; + reg = <0x50>; + pagesize = <32>; + }; +}; + diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi new file mode 100644 index 0000000000..d32c98de9c --- /dev/null +++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +/ { + chosen { + u-boot,dm-spl; + }; +}; + +&lpuart1 { /* console */ + u-boot,dm-spl; +}; + +&semc { + bank1: bank@0 { + u-boot,dm-spl; + }; +}; + +&iomuxc { + u-boot,dm-spl; + + imxrt1020-evk { + u-boot,dm-spl; + pinctrl_lpuart1: lpuart1grp { + u-boot,dm-spl; + }; + + pinctrl_semc: semcgrp { + u-boot,dm-spl; + }; + + pinctrl_usdhc0: usdhc0grp { + u-boot,dm-spl; + }; + }; +}; + +&usdhc1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts new file mode 100644 index 0000000000..ece13601bd --- /dev/null +++ b/arch/arm/dts/imxrt1020-evk.dts @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +/dts-v1/; +#include "imxrt1020.dtsi" +#include "imxrt1020-evk-u-boot.dtsi" +#include <dt-bindings/pinctrl/pins-imxrt1020.h> + +/ { + model = "NXP IMXRT1020-evk board"; + compatible = "fsl,imxrt1020-evk", "fsl,imxrt1020"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x80000000 0x2000000>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&semc { + /* + * Memory configuration from sdram datasheet IS42S16160J-6TLI + */ + fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8 + MUX_CSX0_SDRAM_CS1 + 0 + 0 + 0 + 0>; + fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS + BL_8 + COL_9BITS + CL_3>; + fsl,sdram-timing = /bits/ 8 <0x2 + 0x2 + 0x9 + 0x1 + 0x5 + 0x6 + + 0x20 + 0x09 + 0x01 + 0x00 + + 0x04 + 0x0A + 0x21 + 0x50>; + + bank1: bank@0 { + fsl,base-address = <0x80000000>; + fsl,memory-size = <MEM_SIZE_32M>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + + imxrt1020-evk { + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX + 0xf1 + MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX + 0xf1 + >; + }; + + pinctrl_semc: semcgrp { + fsl,pins = < + MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00 + 0xf1 /* SEMC_D0 */ + MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01 + 0xf1 /* SEMC_D1 */ + MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02 + 0xf1 /* SEMC_D2 */ + MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03 + 0xf1 /* SEMC_D3 */ + MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04 + 0xf1 /* SEMC_D4 */ + MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05 + 0xf1 /* SEMC_D5 */ + MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06 + 0xf1 /* SEMC_D6 */ + MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07 + 0xf1 /* SEMC_D7 */ + MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00 + 0xf1 /* SEMC_DM0 */ + MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 + 0xf1 /* SEMC_A0 */ + MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS + 0xf1 /* SEMC_CAS */ + MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS + 0xf1 /* SEMC_RAS */ + MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0 + 0xf1 /* SEMC_CS0 */ + MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0 + 0xf1 /* SEMC_BA0 */ + MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1 + 0xf1 /* SEMC_BA1 */ + MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10 + 0xf1 /* SEMC_A10 */ + MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00 + 0xf1 /* SEMC_A0 */ + MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01 + 0xf1 /* SEMC_A1 */ + MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02 + 0xf1 /* SEMC_A2 */ + MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03 + 0xf1 /* SEMC_A3 */ + MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04 + 0xf1 /* SEMC_A4 */ + MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05 + 0xf1 /* SEMC_A5 */ + MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06 + 0xf1 /* SEMC_A6 */ + MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07 + 0xf1 /* SEMC_A7 */ + MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08 + 0xf1 /* SEMC_A8 */ + MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09 + 0xf1 /* SEMC_A9 */ + MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11 + 0xf1 /* SEMC_A11 */ + MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12 + 0xf1 /* SEMC_A12 */ + MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS + (IMX_PAD_SION | 0xf1) /* SEMC_DQS */ + MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE + 0xf1 /* SEMC_CKE */ + MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK + 0xf1 /* SEMC_CLK */ + MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01 + 0xf1 /* SEMC_DM01 */ + MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08 + 0xf1 /* SEMC_D8 */ + MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09 + 0xf1 /* SEMC_D9 */ + MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10 + 0xf1 /* SEMC_D10 */ + MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11 + 0xf1 /* SEMC_D11 */ + MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12 + 0xf1 /* SEMC_D12 */ + MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13 + 0xf1 /* SEMC_D13 */ + MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14 + 0xf1 /* SEMC_D14 */ + MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15 + 0xf1 /* SEMC_D15 */ + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B + 0x1B000 + MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD + 0x17061 + MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK + 0x17061 + MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3 + 0x17061 + MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2 + 0x17061 + MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1 + 0x17061 + MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0 + 0x17061 + >; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + status = "okay"; + + cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi new file mode 100644 index 0000000000..97f3cec9f3 --- /dev/null +++ b/arch/arm/dts/imxrt1020.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +#include "armv7-m.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/imxrt1020-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/memory/imxrt-sdram.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + mmc0 = &usdhc1; + serial0 = &lpuart1; + }; + + clocks { + u-boot,dm-spl; + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + osc { + u-boot,dm-spl; + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + soc { + u-boot,dm-spl; + + semc: semc@402f0000 { + u-boot,dm-spl; + compatible = "fsl,imxrt-semc"; + reg = <0x402f0000 0x4000>; + clocks = <&clks IMXRT1020_CLK_SEMC>; + pinctrl-0 = <&pinctrl_semc>; + pinctrl-names = "default"; + status = "okay"; + }; + + lpuart1: serial@40184000 { + compatible = "fsl,imxrt-lpuart"; + reg = <0x40184000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMXRT1020_CLK_LPUART1>; + clock-names = "per"; + status = "disabled"; + }; + + iomuxc: iomuxc@401f8000 { + compatible = "fsl,imxrt-iomuxc"; + reg = <0x401f8000 0x4000>; + fsl,mux_mask = <0x7>; + }; + + clks: ccm@400fc000 { + u-boot,dm-spl; + compatible = "fsl,imxrt1020-ccm"; + reg = <0x400fc000 0x4000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + }; + + usdhc1: usdhc@402c0000 { + u-boot,dm-spl; + compatible = "fsl,imxrt-usdhc"; + reg = <0x402c0000 0x10000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMXRT1020_CLK_USDHC1>; + clock-names = "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + gpio1: gpio@401b8000 { + u-boot,dm-spl; + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x401b8000 0x4000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@401bc000 { + u-boot,dm-spl; + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x401bc000 0x4000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@401c0000 { + u-boot,dm-spl; + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x401c0000 0x4000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts index 56b75986e2..b5e781275e 100644 --- a/arch/arm/dts/imxrt1050-evk.dts +++ b/arch/arm/dts/imxrt1050-evk.dts @@ -185,6 +185,33 @@ 0x17061 >; }; + + pinctrl_lcdif: lcdifgrp { + u-boot,dm-spl; + fsl,pins = < + MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1 + MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069 + MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069 + >; + }; }; }; @@ -198,3 +225,36 @@ cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; }; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + display = <&display0>; + status = "okay"; + + assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>; + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <16>; + + display-timings { + timing0: timing0 { + clock-frequency = <9300000>; + hactive = <480>; + vactive = <272>; + hback-porch = <4>; + hfront-porch = <8>; + vback-porch = <4>; + vfront-porch = <8>; + hsync-len = <41>; + vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index b1d98e6feb..7cfe5f5c95 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -4,7 +4,6 @@ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/imxrt1050-clock.h> @@ -12,7 +11,11 @@ #include <dt-bindings/memory/imxrt-sdram.h> / { + #address-cells = <1>; + #size-cells = <1>; + aliases { + display0 = &lcdif; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -142,5 +145,14 @@ interrupt-controller; #interrupt-cells = <2>; }; + + lcdif: lcdif@402b8000 { + compatible = "fsl,imxrt-lcdif"; + reg = <0x402b8000 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMXRT1050_CLK_LCDIF>; + clock-names = "per"; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index 5058b6c88e..3ebf4af5e4 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -191,7 +191,7 @@ reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; + spi-max-frequency = <50000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 257b56a1b0..e6b78643c1 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -268,7 +268,7 @@ reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; + spi-max-frequency = <50000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 403b158f49..2dde65d968 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -309,7 +309,7 @@ reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; + spi-max-frequency = <50000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi index 8497ff3e3e..946de9c3fc 100644 --- a/arch/arm/dts/k3-j721e-som-p0.dtsi +++ b/arch/arm/dts/k3-j721e-som-p0.dtsi @@ -87,7 +87,7 @@ reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; + spi-max-frequency = <50000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index f577d79afb..11e7e6367d 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -38,21 +38,21 @@ led { compatible = "gpio-leds"; led1 { - label = "green:user1"; + label = "green:user0"; gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; led2 { - label = "green:user2"; + label = "green:user1"; gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; led3 { - label = "green:user3"; + label = "green:user2"; gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc1"; default-state = "off"; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 62c45def43..b57f3d520c 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -37,6 +37,12 @@ default-state = "on"; }; }; + + /* This is actually on FMC2, but we do not have bus driver for that */ + ksz8851: ks8851mll@64000000 { + compatible = "micrel,ks8851-mll"; + reg = <0x64000000 0x20000>; + }; }; &i2c4 { @@ -50,6 +56,68 @@ }; }; +&pinctrl { + /* These should bound to FMC2 bus driver, but we do not have one */ + pinctrl-0 = <&fmc_pins_b>; + pinctrl-1 = <&fmc_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + + fmc_pins_b: fmc-0 { + pins1 { + pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ + <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ + <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */ + <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ + <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ + <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ + <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ + <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ + <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ + <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ + <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ + <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */ + <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */ + <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */ + <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */ + <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */ + <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */ + <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */ + <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */ + <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */ + <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + fmc_sleep_pins_b: fmc-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ + <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ + <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */ + <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ + <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ + <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ + <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ + <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ + <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ + <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ + <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ + <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */ + <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */ + <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */ + <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */ + <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */ + <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */ + <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */ + <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */ + <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */ + <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */ + }; + }; +}; + &pmic { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h b/arch/arm/include/asm/arch-imxrt/imx-regs.h index 4f1d439f6f..44c95dcd11 100644 --- a/arch/arm/include/asm/arch-imxrt/imx-regs.h +++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h @@ -17,4 +17,10 @@ #define ANATOP_BASE_ADDR 0x400d8000 +#define MXS_LCDIF_BASE 0x402b8000 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/mach-imx/regs-lcdif.h> +#endif + #endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index e0fadb9b1c..dbc97b25df 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -306,6 +306,25 @@ struct mx6dq_iomux_grp_regs { u32 grp_b6ds; }; +/* + * NoC scheduler registers - only on IMX6DQP + */ +#define MX6DQP_NOC_SCHED_BASE 0x00bb0000 +struct mx6dqp_noc_sched_regs { + u32 coreid; + u32 revid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 rlat; + u32 res1[4]; + u32 ipu1; + u32 ipu2; + u32 res2[2]; + u32 activate; + u32 res3[16]; +}; + #define MX6SDL_IOM_DDR_BASE 0x020e0400 struct mx6sdl_iomux_ddr_regs { u32 res1[25]; diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h index b4c430a35c..5874638796 100644 --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h @@ -22,7 +22,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_IMX8M) + defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ @@ -49,7 +49,7 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */ mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */ mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */ - mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */ + mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */ mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */ #if defined(CONFIG_MX23) @@ -61,7 +61,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_IMX8M) + defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index fb6c37cf51..df9dd83e40 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -127,8 +127,7 @@ ENTRY(_main) ldr r0, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ mov sp, r0 - ldr r9, [r9, #GD_BD] /* r9 = gd->bd */ - sub r9, r9, #GD_SIZE /* new GD is below bd */ + ldr r9, [r9, #GD_NEW_GD] /* r9 <- gd->new_gd */ adr lr, here ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index aa140c4798..329149900a 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -41,7 +41,7 @@ config IMX_HAB imply CMD_DEKBLOB help This option enables the support for secure boot (HAB). - See doc/README.mxc_hab for more details. + See doc/imx/habv4/* for more details. config CSF_SIZE hex "Maximum size for Command Sequence File (CSF) binary" @@ -69,7 +69,7 @@ config CMD_DEKBLOB help This enables the 'dek_blob' command which is used with the Freescale secure boot mechanism. This command encapsulates and - creates a blob of data. See also CMD_BLOB and doc/README.mxc_hab for + creates a blob of data. See also CMD_BLOB and doc/imx/habv4/* for more information. config CMD_HDMIDETECT diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig index e3aff11d48..d275fdf72e 100644 --- a/arch/arm/mach-imx/imxrt/Kconfig +++ b/arch/arm/mach-imx/imxrt/Kconfig @@ -3,6 +3,10 @@ if ARCH_IMXRT config IMXRT bool +config IMXRT1020 + bool + select IMXRT + config IMXRT1050 bool select IMXRT @@ -14,12 +18,17 @@ choice prompt "NXP i.MXRT board select" optional +config TARGET_IMXRT1020_EVK + bool "Support imxrt1020 EVK board" + select IMXRT1020 + config TARGET_IMXRT1050_EVK bool "Support imxrt1050 EVK board" select IMXRT1050 endchoice +source "board/freescale/imxrt1020-evk/Kconfig" source "board/freescale/imxrt1050-evk/Kconfig" endif diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index f9f576d403..fa6e1112e6 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -590,7 +590,18 @@ config TARGET_KP_IMX6Q_TPC config TARGET_TQMA6 bool "TQ Systems TQMa6 board" + select BOARD_EARLY_INIT_F select BOARD_LATE_INIT + select MXC_SPI + select SPI + imply DM + imply DM_GPIO + imply DM_MMC + imply DM_SPI + imply DM_SPI_FLASH + imply DM_I2C + imply CMD_SF + imply CMD_DM config TARGET_UDOO bool "udoo" diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 4396880b74..69fe756b0b 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -945,6 +945,27 @@ void mx6sdl_dram_iocfg(unsigned width, mmdc1->entry = value; \ } while (0) +/* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */ +#define BOOT_CFG3_DDR_MASK 0x30 +#define BOOT_CFG3_EXT_DDR_MASK 0x33 + +#define DDR_MMAP_NOC_SINGLE 0 +#define DDR_MMAP_NOC_DUAL 0x31 + +/* NoC ACTIVATE shifts */ +#define NOC_RD_SHIFT 0 +#define NOC_FAW_PERIOD_SHIFT 4 +#define NOC_FAW_BANKS_SHIFT 10 + +/* NoC DdrTiming shifts */ +#define NOC_ACT_TO_ACT_SHIFT 0 +#define NOC_RD_TO_MISS_SHIFT 6 +#define NOC_WR_TO_MISS_SHIFT 12 +#define NOC_BURST_LEN_SHIFT 18 +#define NOC_RD_TO_WR_SHIFT 21 +#define NOC_WR_TO_RD_SHIFT 26 +#define NOC_BW_RATIO_SHIFT 31 + /* * According JESD209-2B-LPDDR2: Table 103 * WL: write latency @@ -1234,6 +1255,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, { volatile struct mmdc_p_regs *mmdc0; volatile struct mmdc_p_regs *mmdc1; + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff; u32 val; u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; @@ -1526,6 +1549,79 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, /* Step 12: Configure and activate periodic refresh */ mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); + /* + * Step 13: i.MX6DQP only: If the NoC scheduler is enabled, + * configure it and disable MMDC arbitration/reordering (see EB828) + */ + if (is_mx6dqp() && + ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE || + (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) { + struct mx6dqp_noc_sched_regs *noc_sched = + (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE; + + /* + * These values are fixed based on integration parameters and + * should not be modified + */ + noc_sched->rlat = 0x00000040; + noc_sched->ipu1 = 0x00000020; + noc_sched->ipu2 = 0x00000020; + + noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) | + (tfaw << NOC_FAW_PERIOD_SHIFT) | + (trrd << NOC_RD_SHIFT); + noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0) + << NOC_BW_RATIO_SHIFT) | + ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) | + ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) | + (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */ + ((tcwl + twr + trp + trcd) + << NOC_WR_TO_MISS_SHIFT) | + ((trtp + trp + trcd - 4) + << NOC_RD_TO_MISS_SHIFT) | + (trc << NOC_ACT_TO_ACT_SHIFT); + + if (sysinfo->dsize == 2) { + if (ddr3_cfg->coladdr == 10) { + if (ddr3_cfg->rowaddr == 15 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 4; + else + noc_sched->ddrconf = 0; + } else if (ddr3_cfg->coladdr == 11) { + noc_sched->ddrconf = 1; + } + } else { + if (ddr3_cfg->coladdr == 9) { + if (ddr3_cfg->rowaddr == 13) + noc_sched->ddrconf = 2; + else if (ddr3_cfg->rowaddr == 14) + noc_sched->ddrconf = 15; + } else if (ddr3_cfg->coladdr == 10) { + if (ddr3_cfg->rowaddr == 14 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 14; + else if (ddr3_cfg->rowaddr == 15 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 9; + else + noc_sched->ddrconf = 3; + } else if (ddr3_cfg->coladdr == 11) { + if (ddr3_cfg->rowaddr == 15 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 4; + else + noc_sched->ddrconf = 0; + } else if (ddr3_cfg->coladdr == 12) { + if (ddr3_cfg->rowaddr == 14) + noc_sched->ddrconf = 1; + } + } + + /* Disable MMDC arbitration/reordering */ + mmdc0->maarcr = 0x14420000; + } + /* Step 13: Deassert config request - init complete */ mmdc0->mdscr = 0x00000000; diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 46484813d2..0d39dab7ea 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -118,12 +118,26 @@ void init_wdog(void) disable_wdog(WDG2_RBASE); } +static bool ldo_mode_is_enabled(void) +{ + unsigned int reg; + + reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); + if (reg & PMC0_CTRL_LDOEN) + return true; + else + return false; +} + #if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) #if defined(CONFIG_LDO_ENABLED_MODE) static void init_ldo_mode(void) { unsigned int reg; + if (ldo_mode_is_enabled()) + return; + /* Set LDOOKDIS */ setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); @@ -193,21 +207,6 @@ const char *get_imx_type(u32 imxtype) return "7ULP"; } -#define PMC0_BASE_ADDR 0x410a1000 -#define PMC0_CTRL 0x28 -#define PMC0_CTRL_LDOEN BIT(31) - -static bool ldo_mode_is_enabled(void) -{ - unsigned int reg; - - reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); - if (reg & PMC0_CTRL_LDOEN) - return true; - else - return false; -} - int print_cpuinfo(void) { u32 cpurev; diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index efd84ec7eb..80dfa5f0fd 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -307,15 +307,15 @@ int print_cpuinfo(void) u32 soc, rev; char *name; - soc = (readl(CTRLMMR_WKUP_JTAG_DEVICE_ID) & - DEVICE_ID_FAMILY_MASK) >> DEVICE_ID_FAMILY_SHIFT; + soc = (readl(CTRLMMR_WKUP_JTAG_ID) & + JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; rev = (readl(CTRLMMR_WKUP_JTAG_ID) & JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT; printf("SoC: "); switch (soc) { - case AM654: - name = "AM654"; + case AM65X: + name = "AM65x"; break; case J721E: name = "J721E"; diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index b1cbe116ef..57682e1973 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -8,8 +8,8 @@ #include <asm/armv7_mpu.h> -#define AM654 2 -#define J721E 4 +#define AM65X 0xbb5a +#define J721E 0xbb64 #define REV_PG1_0 0 #define REV_PG2_0 1 diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index d670d5a56e..0ad761418b 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -15,20 +15,10 @@ #endif /* Assuming these addresses and definitions stay common across K3 devices */ -#define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018 -#define DEVICE_ID_FAMILY_SHIFT 26 -#define DEVICE_ID_FAMILY_MASK (0x3f << 26) -#define DEVICE_ID_BASE_SHIFT 11 -#define DEVICE_ID_BASE_MASK (0x1fff << 11) -#define DEVICE_ID_SPEED_SHIFT 6 -#define DEVICE_ID_SPEED_MASK (0x1f << 6) -#define DEVICE_ID_TEMP_SHIFT 3 -#define DEVICE_ID_TEMP_MASK (0x7 << 3) - -#define CTRLMMR_WKUP_JTAG_ID 0x43000014 +#define CTRLMMR_WKUP_JTAG_ID 0x43000014 #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) #define JTAG_ID_PARTNO_SHIFT 12 -#define JTAG_ID_PARTNO_MASK (0x7ff << 1) +#define JTAG_ID_PARTNO_MASK (0xffff << 12) #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 96153693a7..ba965e7b3b 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -35,9 +35,10 @@ config ENV_SIZE config STM32MP15x bool "Support STMicroelectronics STM32MP15x Soc" - select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED + select ARCH_SUPPORT_PSCI if !TFABOOT + select ARM_SMCCC if TFABOOT select CPU_V7A - select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED + select CPU_V7_HAS_NONSEC if !TFABOOT select CPU_V7_HAS_VIRT select OF_BOARD_SETUP select PINCTRL_STM32 @@ -45,8 +46,8 @@ config STM32MP15x select STM32_RESET select STM32_SERIAL select SYS_ARCH_TIMER - imply SYSRESET_PSCI if STM32MP1_TRUSTED - imply SYSRESET_SYSCON if !STM32MP1_TRUSTED + imply SYSRESET_PSCI if TFABOOT + imply SYSRESET_SYSCON if !TFABOOT help support of STMicroelectronics SOC STM32MP15x family STM32MP157, STM32MP153 or STM32MP151 @@ -62,7 +63,9 @@ config TARGET_ST_STM32MP15x bool "STMicroelectronics STM32MP15x boards" select STM32MP15x imply BOOTCOUNT_LIMIT + imply BOOTSTAGE imply CMD_BOOTCOUNT + imply CMD_BOOTSTAGE imply CMD_CLS if CMD_BMP imply DISABLE_CONSOLE imply PRE_CONSOLE_BUFFER @@ -83,19 +86,9 @@ config TARGET_DH_STM32MP1_PDK2 endchoice -config STM32MP1_TRUSTED - bool "Support trusted boot with TF-A" - default y if !SPL - select ARM_SMCCC - help - Say Y here to enable boot with TF-A - Trusted boot chain is : - BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32 - TF-A monitor provides proprietary SMC to manage secure devices - config STM32MP1_OPTEE bool "Support trusted boot with TF-A and OP-TEE" - depends on STM32MP1_TRUSTED + depends on TFABOOT default n help Say Y here to enable boot with TF-A and OP-TEE diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 3b923f088e..0d5850b4a9 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -68,7 +68,7 @@ static bool bsec_read_lock(u32 address, u32 otp) return !!(readl(address + bank) & bit); } -#ifndef CONFIG_STM32MP1_TRUSTED +#ifndef CONFIG_TFABOOT /** * bsec_check_error() - Check status of one otp * @base: base address of bsec IP @@ -273,7 +273,7 @@ static int bsec_program_otp(long base, u32 val, u32 otp) return ret; } -#endif /* CONFIG_STM32MP1_TRUSTED */ +#endif /* CONFIG_TFABOOT */ /* BSEC MISC driver *******************************************************/ struct stm32mp_bsec_platdata { @@ -282,7 +282,7 @@ struct stm32mp_bsec_platdata { static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) { -#ifdef CONFIG_STM32MP1_TRUSTED +#ifdef CONFIG_TFABOOT return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_OTP, otp, 0, val); @@ -313,7 +313,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) { -#ifdef CONFIG_STM32MP1_TRUSTED +#ifdef CONFIG_TFABOOT return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_SHADOW, otp, 0, val); @@ -336,7 +336,7 @@ static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp) static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) { -#ifdef CONFIG_STM32MP1_TRUSTED +#ifdef CONFIG_TFABOOT return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_PROG_OTP, otp, val); @@ -349,7 +349,7 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) { -#ifdef CONFIG_STM32MP1_TRUSTED +#ifdef CONFIG_TFABOOT return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRITE_SHADOW, otp, val); @@ -362,7 +362,7 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp) { -#ifdef CONFIG_STM32MP1_TRUSTED +#ifdef CONFIG_TFABOOT if (val == 1) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRLOCK_OTP, @@ -473,7 +473,7 @@ static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev) return 0; } -#ifndef CONFIG_STM32MP1_TRUSTED +#ifndef CONFIG_TFABOOT static int stm32mp_bsec_probe(struct udevice *dev) { int otp; @@ -500,7 +500,7 @@ U_BOOT_DRIVER(stm32mp_bsec) = { .ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata), .ops = &stm32mp_bsec_ops, -#ifndef CONFIG_STM32MP1_TRUSTED +#ifndef CONFIG_TFABOOT .probe = stm32mp_bsec_probe, #endif }; diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 9aa5794334..74d03fa7dd 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -76,7 +76,7 @@ #define PKG_MASK GENMASK(2, 0) #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) -#ifndef CONFIG_STM32MP1_TRUSTED +#ifndef CONFIG_TFABOOT static void security_init(void) { /* Disable the backup domain write protection */ @@ -136,7 +136,7 @@ static void security_init(void) writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); } -#endif /* CONFIG_STM32MP1_TRUSTED */ +#endif /* CONFIG_TFABOOT */ /* * Debug init @@ -150,7 +150,7 @@ static void dbgmcu_init(void) } #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ -#if !defined(CONFIG_STM32MP1_TRUSTED) && \ +#if !defined(CONFIG_TFABOOT) && \ (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) /* get bootmode from ROM code boot context: saved in TAMP register */ static void update_bootmode(void) @@ -198,7 +198,7 @@ int arch_cpu_init(void) #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) dbgmcu_init(); -#ifndef CONFIG_STM32MP1_TRUSTED +#ifndef CONFIG_TFABOOT security_init(); update_bootmode(); #endif @@ -214,7 +214,7 @@ int arch_cpu_init(void) if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; #if defined(CONFIG_DEBUG_UART) && \ - !defined(CONFIG_STM32MP1_TRUSTED) && \ + !defined(CONFIG_TFABOOT) && \ (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) else debug_uart_init(); diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 6daf9f7121..76d593d785 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -13,6 +13,7 @@ #define STM32_RCC_BASE 0x50000000 #define STM32_PWR_BASE 0x50001000 #define STM32_DBGMCU_BASE 0x50081000 +#define STM32_FMC2_BASE 0x58002000 #define STM32_TZC_BASE 0x5C006000 #define STM32_ETZPC_BASE 0x5C007000 #define STM32_STGEN_BASE 0x5C008000 diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index f7c73e3a0b..e7ec892bdf 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -8,6 +8,7 @@ #include <fcntl.h> #include <getopt.h> #include <setjmp.h> +#include <signal.h> #include <stdio.h> #include <stdint.h> #include <stdlib.h> @@ -175,6 +176,13 @@ void os_fd_restore(void) } } +static void os_sigint_handler(int sig) +{ + os_fd_restore(); + signal(SIGINT, SIG_DFL); + raise(SIGINT); +} + /* Put tty into raw mode so <tab> and <ctrl+c> work */ void os_tty_raw(int fd, bool allow_sigs) { @@ -205,6 +213,7 @@ void os_tty_raw(int fd, bool allow_sigs) term_setup = true; atexit(os_fd_restore); + signal(SIGINT, os_sigint_handler); } void *os_malloc(size_t length) diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 4dd82f6a32..20f6893829 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -10,7 +10,7 @@ aliases { i2c0 = &i2c_0; - pci0 = &pci; + pci0 = &pcic; rtc0 = &rtc_0; axi0 = &axi; spi0 = &spi; @@ -20,6 +20,25 @@ reg = <0 CONFIG_SYS_SDRAM_SIZE>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + reservation_test0 { + size = <0x4000>; + alignment = <0x2000>; + }; + + reservation_test1: restest@a000 { + reg = <0x00d0a000 0x2000>; + }; + + reservation_test2: restest@7000 { + reg = <0x00d07000 0x1000>; + }; + }; + cros_ec: cros-ec { reg = <0 0>; u-boot,dm-pre-reloc; @@ -52,9 +71,10 @@ pinctrl-0 = <&pinctrl_i2c0>; }; - pci: pci-controller { + pcic: pci@0 { compatible = "sandbox,pci"; device_type = "pci"; + bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000 diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index 7cd56c14f2..e1f68cd552 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -100,7 +100,7 @@ }; }; - pci-controller { + pci@0 { pci@1e,0 { compatible = "sandbox,pmc"; reg = <0xf000 0 0 0 0>; diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts index 5c95cee9d7..a39f94feec 100644 --- a/arch/sandbox/dts/sandbox64.dts +++ b/arch/sandbox/dts/sandbox64.dts @@ -10,7 +10,7 @@ aliases { i2c0 = &i2c_0; - pci0 = &pci; + pci0 = &pcic; rtc0 = &rtc_0; axi0 = &axi; spi0 = &spi; @@ -20,6 +20,26 @@ reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reservation_test_size { + size = <0 0x4000>; + alignment = <0 0x2000>; + }; + + reservation_test@a000 { + reg = <0 0x00d0a000 0 0x2000>; + }; + + reservation_test@7000 { + reg = <0 0x00d07000 0 0x1000>; + }; + }; + + /* ... */ cros_ec: cros-ec { reg = <0 0 0 0>; u-boot,dm-pre-reloc; @@ -47,9 +67,10 @@ pinctrl-0 = <&pinctrl_i2c0>; }; - pci: pci-controller { + pcic: pci@0 { compatible = "sandbox,pci"; device_type = "pci"; + bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; ranges = <0x02000000 0 0x10000000 0 0x10000000 0 0x2000 diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 4a277934a7..df9f1835c9 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1,5 +1,8 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/gpio/sandbox-gpio.h> + / { model = "sandbox"; compatible = "sandbox"; @@ -13,6 +16,7 @@ eth5 = ð_5; gpio1 = &gpio_a; gpio2 = &gpio_b; + gpio3 = &gpio_c; i2c0 = "/i2c@0"; mmc0 = "/mmc0"; mmc1 = "/mmc1"; @@ -86,13 +90,25 @@ ping-expect = <0>; ping-add = <0>; u-boot,dm-pre-reloc; - test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>, + test-gpios = <&gpio_a 1>, <&gpio_a 4>, + <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>, <0>, <&gpio_a 12>; - test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>, - <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>, - <&gpio_b 9 0xc 3 2 1>; + test2-gpios = <&gpio_a 1>, <&gpio_a 4>, + <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>, + <&gpio_b 7 GPIO_IN 3 2 1>, + <&gpio_b 8 GPIO_OUT 3 2 1>, + <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>; + test3-gpios = + <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>, + <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>, + <&gpio_c 2 GPIO_OUT>, + <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>, + <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>, + <&gpio_c 5 GPIO_IN>; int-value = <1234>; uint-value = <(-1234)>; + int64-value = /bits/ 64 <0x1111222233334444>; + int-array = <5678 9123 4567>; interrupts-extended = <&irq 3 0>; }; @@ -206,6 +222,10 @@ compatible = "denx,u-boot-devres-test"; }; + acpi-test { + compatible = "denx,u-boot-acpi-test"; + }; + clocks { clk_fixed: clk-fixed { compatible = "fixed-clock"; @@ -279,20 +299,32 @@ }; }; - gpio_a: base-gpios { - compatible = "sandbox,gpio"; - gpio-controller; - #gpio-cells = <1>; - gpio-bank-name = "a"; - sandbox,gpio-count = <20>; - }; + pinctrl-gpio { + compatible = "sandbox,pinctrl-gpio"; + + gpio_a: base-gpios { + compatible = "sandbox,gpio"; + gpio-controller; + #gpio-cells = <1>; + gpio-bank-name = "a"; + sandbox,gpio-count = <20>; + }; + + gpio_b: extra-gpios { + compatible = "sandbox,gpio"; + gpio-controller; + #gpio-cells = <5>; + gpio-bank-name = "b"; + sandbox,gpio-count = <10>; + }; - gpio_b: extra-gpios { - compatible = "sandbox,gpio"; - gpio-controller; - #gpio-cells = <5>; - gpio-bank-name = "b"; - sandbox,gpio-count = <10>; + gpio_c: pinmux-gpios { + compatible = "sandbox,gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-bank-name = "c"; + sandbox,gpio-count = <10>; + }; }; i2c@0 { @@ -463,9 +495,10 @@ compatible = "sandbox,pch"; }; - pci0: pci-controller0 { + pci0: pci@0 { compatible = "sandbox,pci"; device_type = "pci"; + bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000 @@ -531,9 +564,10 @@ }; }; - pci1: pci-controller1 { + pci1: pci@1 { compatible = "sandbox,pci"; device_type = "pci"; + bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 @@ -546,9 +580,10 @@ }; }; - pci2: pci-controller2 { + pci2: pci@2 { compatible = "sandbox,pci"; device_type = "pci"; + bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000 @@ -896,6 +931,31 @@ pinctrl { compatible = "sandbox,pinctrl"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpios>; + + gpios: gpios { + gpio0 { + pins = "GPIO0"; + bias-pull-up; + input-disable; + }; + gpio1 { + pins = "GPIO1"; + output-high; + drive-open-drain; + }; + gpio2 { + pins = "GPIO2"; + bias-pull-down; + input-enable; + }; + gpio3 { + pins = "GPIO3"; + bias-disable; + }; + }; }; hwspinlock@0 { diff --git a/arch/sandbox/include/asm/acpi_table.h b/arch/sandbox/include/asm/acpi_table.h new file mode 100644 index 0000000000..921c7f4201 --- /dev/null +++ b/arch/sandbox/include/asm/acpi_table.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __ASM_ACPI_TABLE_H__ +#define __ASM_ACPI_TABLE_H__ + +#endif /* __ASM_ACPI_TABLE_H__ */ diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h index de8ac37f42..df4ba4fb5f 100644 --- a/arch/sandbox/include/asm/gpio.h +++ b/arch/sandbox/include/asm/gpio.h @@ -43,43 +43,43 @@ int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset); int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value); /** - * Set or reset the simulated open drain mode of a GPIO (used only in sandbox - * test code) + * Return the simulated direction of a GPIO (used only in sandbox test code) * - * @param gp GPIO number - * @param value value to set (0 for enabled open drain mode, non-zero for - * disabled) - * @return -1 on error, 0 if ok + * @param dev device to use + * @param offset GPIO offset within bank + * @return -1 on error, 0 if GPIO is input, >0 if output */ -int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value); +int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset); /** - * Return the state of the simulated open drain mode of a GPIO (used only in - * sandbox test code) + * Set the simulated direction of a GPIO (used only in sandbox test code) * - * @param gp GPIO number - * @return -1 on error, 0 if GPIO is input, >0 if output + * @param dev device to use + * @param offset GPIO offset within bank + * @param output 0 to set as input, 1 to set as output + * @return -1 on error, 0 if ok */ -int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset); +int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset, + int output); /** - * Return the simulated direction of a GPIO (used only in sandbox test code) + * Return the simulated flags of a GPIO (used only in sandbox test code) * * @param dev device to use * @param offset GPIO offset within bank - * @return -1 on error, 0 if GPIO is input, >0 if output + * @return dir_flags: bitfield accesses by GPIOD_ defines */ -int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset); +ulong sandbox_gpio_get_dir_flags(struct udevice *dev, unsigned int offset); /** - * Set the simulated direction of a GPIO (used only in sandbox test code) + * Set the simulated flags of a GPIO (used only in sandbox test code) * * @param dev device to use * @param offset GPIO offset within bank - * @param output 0 to set as input, 1 to set as output + * @param flags dir_flags: bitfield accesses by GPIOD_ defines * @return -1 on error, 0 if ok */ -int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset, - int output); +int sandbox_gpio_set_dir_flags(struct udevice *dev, unsigned int offset, + ulong flags); #endif diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 8a39c3128e..e2509e391f 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -6,13 +6,13 @@ */ #include <common.h> -#include <acpi_s3.h> #include <dm.h> #include <ec_commands.h> #include <log.h> #include <spi_flash.h> #include <spl.h> #include <syscon.h> +#include <acpi/acpi_s3.h> #include <asm/cpu.h> #include <asm/cpu_common.h> #include <asm/cpu_x86.h> diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index 1f22c1ea3c..17cf1682ad 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -5,11 +5,11 @@ */ #include <common.h> -#include <acpi_s3.h> #include <binman.h> #include <dm.h> #include <irq.h> #include <malloc.h> +#include <acpi/acpi_s3.h> #include <asm/intel_pinctrl.h> #include <asm/io.h> #include <asm/intel_regs.h> diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c index aec0c8394c..4ea7c7447b 100644 --- a/arch/x86/cpu/apollolake/pmc.c +++ b/arch/x86/cpu/apollolake/pmc.c @@ -9,10 +9,10 @@ #define LOG_CATEGORY UCLASS_ACPI_PMC #include <common.h> -#include <acpi_s3.h> #include <dt-structs.h> #include <dm.h> #include <spl.h> +#include <acpi/acpi_s3.h> #include <asm/io.h> #include <asm/pci.h> #include <power/acpi_pmc.h> diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index f44228e693..5772310979 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -4,15 +4,15 @@ */ #include <common.h> -#include <acpi_s3.h> #include <cpu.h> #include <dm.h> -#include <dm/uclass-internal.h> -#include <asm/acpi_table.h> +#include <acpi/acpi_s3.h> +#include <acpi/acpi_table.h> #include <asm/io.h> #include <asm/tables.h> #include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> +#include <dm/uclass-internal.h> void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, void *dsdt) diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c index e698200d70..e8ccaf2212 100644 --- a/arch/x86/cpu/coreboot/timestamp.c +++ b/arch/x86/cpu/coreboot/timestamp.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * This file is part of the coreboot project. - * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * Modified from the coreboot version */ #include <common.h> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index dae06949cc..cec04b481b 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -19,7 +19,6 @@ */ #include <common.h> -#include <acpi_s3.h> #include <command.h> #include <cpu_func.h> #include <dm.h> @@ -27,8 +26,9 @@ #include <init.h> #include <malloc.h> #include <syscon.h> +#include <acpi/acpi_s3.h> +#include <acpi/acpi_table.h> #include <asm/acpi.h> -#include <asm/acpi_table.h> #include <asm/control_regs.h> #include <asm/coreboot_tables.h> #include <asm/cpu.h> diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index d5b4846e0a..6f3c441618 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -92,46 +92,35 @@ int p2sb_ofdata_to_platdata(struct udevice *dev) #if !CONFIG_IS_ENABLED(OF_PLATDATA) int ret; + u32 base[2]; + ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base)); + if (ret) + return log_msg_ret("Missing/short early-regs", ret); + plat->mmio_base = base[0]; + /* TPL sets up the initial BAR */ if (spl_phase() == PHASE_TPL) { - u32 base[2]; - - /* TPL sets up the initial BAR */ - ret = dev_read_u32_array(dev, "early-regs", base, - ARRAY_SIZE(base)); - if (ret) - return log_msg_ret("Missing/short early-regs", ret); - plat->mmio_base = base[0]; plat->bdf = pci_get_devfn(dev); if (plat->bdf < 0) return log_msg_ret("Cannot get p2sb PCI address", plat->bdf); } + upriv->mmio_base = plat->mmio_base; #else plat->mmio_base = plat->dtplat.early_regs[0]; plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); -#endif upriv->mmio_base = plat->mmio_base; - debug("p2sb: mmio_base=%x\n", (uint)plat->mmio_base); +#endif return 0; } static int p2sb_probe(struct udevice *dev) { - if (spl_phase() == PHASE_TPL) { + if (spl_phase() == PHASE_TPL) return p2sb_early_init(dev); - } else { - struct p2sb_platdata *plat = dev_get_platdata(dev); - - plat->mmio_base = dev_read_addr_pci(dev); - /* Don't set BDF since it should not be used */ - if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE) - return -EINVAL; - - if (spl_phase() == PHASE_SPL) - return p2sb_spl_init(dev); - } + else if (spl_phase() == PHASE_SPL) + return p2sb_spl_init(dev); return 0; } diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 7b6fc2f4a5..26cda3b337 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -4,7 +4,7 @@ */ #include <common.h> -#include <asm/acpi_table.h> +#include <acpi/acpi_table.h> #include <asm/tables.h> #include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 8b128138b0..4ec8fdd6f8 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -8,13 +8,13 @@ #include <common.h> #include <cpu.h> #include <dm.h> -#include <dm/uclass-internal.h> -#include <asm/acpi_table.h> +#include <acpi/acpi_table.h> #include <asm/ioapic.h> #include <asm/mpspec.h> #include <asm/tables.h> #include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> +#include <dm/uclass-internal.h> void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, void *dsdt) diff --git a/arch/x86/cpu/wakeup.S b/arch/x86/cpu/wakeup.S index 244ca1276a..093bf3bcc5 100644 --- a/arch/x86/cpu/wakeup.S +++ b/arch/x86/cpu/wakeup.S @@ -5,7 +5,7 @@ * From coreboot src/arch/x86/wakeup.S */ -#include <acpi_s3.h> +#include <acpi/acpi_s3.h> #include <asm/processor.h> #include <asm/processor-flags.h> diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index af52e11c89..d48ef3573e 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -292,7 +292,7 @@ reg = <0x50>; compatible = "google,cr50"; u-boot,i2c-offset-len = <0>; - ready-gpio = <&gpio_n 28 GPIO_ACTIVE_LOW>; + ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>; interrupts-extended = <&acpi_gpe 0x3c 0>; }; }; diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 7588913f93..928475cef4 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -9,381 +9,14 @@ #ifndef __ASM_ACPI_TABLE_H__ #define __ASM_ACPI_TABLE_H__ -#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */ -#define OEM_ID "U-BOOT" /* U-Boot */ -#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */ -#define ASLC_ID "INTL" /* Intel ASL Compiler */ - -#define ACPI_RSDP_REV_ACPI_1_0 0 -#define ACPI_RSDP_REV_ACPI_2_0 2 - -/* - * RSDP (Root System Description Pointer) - * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum - */ -struct acpi_rsdp { - char signature[8]; /* RSDP signature */ - u8 checksum; /* Checksum of the first 20 bytes */ - char oem_id[6]; /* OEM ID */ - u8 revision; /* 0 for ACPI 1.0, others 2 */ - u32 rsdt_address; /* Physical address of RSDT (32 bits) */ - u32 length; /* Total RSDP length (incl. extended part) */ - u64 xsdt_address; /* Physical address of XSDT (64 bits) */ - u8 ext_checksum; /* Checksum of the whole table */ - u8 reserved[3]; -}; - -/* Generic ACPI header, provided by (almost) all tables */ -struct __packed acpi_table_header { - char signature[4]; /* ACPI signature (4 ASCII characters) */ - u32 length; /* Table length in bytes (incl. header) */ - u8 revision; /* Table version (not ACPI version!) */ - volatile u8 checksum; /* To make sum of entire table == 0 */ - char oem_id[6]; /* OEM identification */ - char oem_table_id[8]; /* OEM table identification */ - u32 oem_revision; /* OEM revision number */ - char aslc_id[4]; /* ASL compiler vendor ID */ - u32 aslc_revision; /* ASL compiler revision number */ -}; - -/* A maximum number of 32 ACPI tables ought to be enough for now */ -#define MAX_ACPI_TABLES 32 - -/* RSDT (Root System Description Table) */ -struct acpi_rsdt { - struct acpi_table_header header; - u32 entry[MAX_ACPI_TABLES]; -}; - -/* XSDT (Extended System Description Table) */ -struct acpi_xsdt { - struct acpi_table_header header; - u64 entry[MAX_ACPI_TABLES]; -}; - -/* FADT Preferred Power Management Profile */ -enum acpi_pm_profile { - ACPI_PM_UNSPECIFIED = 0, - ACPI_PM_DESKTOP, - ACPI_PM_MOBILE, - ACPI_PM_WORKSTATION, - ACPI_PM_ENTERPRISE_SERVER, - ACPI_PM_SOHO_SERVER, - ACPI_PM_APPLIANCE_PC, - ACPI_PM_PERFORMANCE_SERVER, - ACPI_PM_TABLET -}; - -/* FADT flags for p_lvl2_lat and p_lvl3_lat */ -#define ACPI_FADT_C2_NOT_SUPPORTED 101 -#define ACPI_FADT_C3_NOT_SUPPORTED 1001 - -/* FADT Boot Architecture Flags */ -#define ACPI_FADT_LEGACY_FREE 0x00 -#define ACPI_FADT_LEGACY_DEVICES (1 << 0) -#define ACPI_FADT_8042 (1 << 1) -#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2) -#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3) -#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4) - -/* FADT Feature Flags */ -#define ACPI_FADT_WBINVD (1 << 0) -#define ACPI_FADT_WBINVD_FLUSH (1 << 1) -#define ACPI_FADT_C1_SUPPORTED (1 << 2) -#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3) -#define ACPI_FADT_POWER_BUTTON (1 << 4) -#define ACPI_FADT_SLEEP_BUTTON (1 << 5) -#define ACPI_FADT_FIXED_RTC (1 << 6) -#define ACPI_FADT_S4_RTC_WAKE (1 << 7) -#define ACPI_FADT_32BIT_TIMER (1 << 8) -#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9) -#define ACPI_FADT_RESET_REGISTER (1 << 10) -#define ACPI_FADT_SEALED_CASE (1 << 11) -#define ACPI_FADT_HEADLESS (1 << 12) -#define ACPI_FADT_SLEEP_TYPE (1 << 13) -#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14) -#define ACPI_FADT_PLATFORM_CLOCK (1 << 15) -#define ACPI_FADT_S4_RTC_VALID (1 << 16) -#define ACPI_FADT_REMOTE_POWER_ON (1 << 17) -#define ACPI_FADT_APIC_CLUSTER (1 << 18) -#define ACPI_FADT_APIC_PHYSICAL (1 << 19) -#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20) -#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21) - -enum acpi_address_space_type { - ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */ - ACPI_ADDRESS_SPACE_IO, /* System I/O */ - ACPI_ADDRESS_SPACE_PCI, /* PCI config space */ - ACPI_ADDRESS_SPACE_EC, /* Embedded controller */ - ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */ - ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */ - ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */ -}; - -enum acpi_address_space_size { - ACPI_ACCESS_SIZE_UNDEFINED = 0, - ACPI_ACCESS_SIZE_BYTE_ACCESS, - ACPI_ACCESS_SIZE_WORD_ACCESS, - ACPI_ACCESS_SIZE_DWORD_ACCESS, - ACPI_ACCESS_SIZE_QWORD_ACCESS -}; - -struct acpi_gen_regaddr { - u8 space_id; /* Address space ID */ - u8 bit_width; /* Register size in bits */ - u8 bit_offset; /* Register bit offset */ - u8 access_size; /* Access size */ - u32 addrl; /* Register address, low 32 bits */ - u32 addrh; /* Register address, high 32 bits */ -}; - -/* FADT (Fixed ACPI Description Table) */ -struct __packed acpi_fadt { - struct acpi_table_header header; - u32 firmware_ctrl; - u32 dsdt; - u8 res1; - u8 preferred_pm_profile; - u16 sci_int; - u32 smi_cmd; - u8 acpi_enable; - u8 acpi_disable; - u8 s4bios_req; - u8 pstate_cnt; - u32 pm1a_evt_blk; - u32 pm1b_evt_blk; - u32 pm1a_cnt_blk; - u32 pm1b_cnt_blk; - u32 pm2_cnt_blk; - u32 pm_tmr_blk; - u32 gpe0_blk; - u32 gpe1_blk; - u8 pm1_evt_len; - u8 pm1_cnt_len; - u8 pm2_cnt_len; - u8 pm_tmr_len; - u8 gpe0_blk_len; - u8 gpe1_blk_len; - u8 gpe1_base; - u8 cst_cnt; - u16 p_lvl2_lat; - u16 p_lvl3_lat; - u16 flush_size; - u16 flush_stride; - u8 duty_offset; - u8 duty_width; - u8 day_alrm; - u8 mon_alrm; - u8 century; - u16 iapc_boot_arch; - u8 res2; - u32 flags; - struct acpi_gen_regaddr reset_reg; - u8 reset_value; - u16 arm_boot_arch; - u8 minor_revision; - u32 x_firmware_ctl_l; - u32 x_firmware_ctl_h; - u32 x_dsdt_l; - u32 x_dsdt_h; - struct acpi_gen_regaddr x_pm1a_evt_blk; - struct acpi_gen_regaddr x_pm1b_evt_blk; - struct acpi_gen_regaddr x_pm1a_cnt_blk; - struct acpi_gen_regaddr x_pm1b_cnt_blk; - struct acpi_gen_regaddr x_pm2_cnt_blk; - struct acpi_gen_regaddr x_pm_tmr_blk; - struct acpi_gen_regaddr x_gpe0_blk; - struct acpi_gen_regaddr x_gpe1_blk; -}; - -/* FACS flags */ -#define ACPI_FACS_S4BIOS_F (1 << 0) -#define ACPI_FACS_64BIT_WAKE_F (1 << 1) - -/* FACS (Firmware ACPI Control Structure) */ -struct acpi_facs { - char signature[4]; /* "FACS" */ - u32 length; /* Length in bytes (>= 64) */ - u32 hardware_signature; /* Hardware signature */ - u32 firmware_waking_vector; /* Firmware waking vector */ - u32 global_lock; /* Global lock */ - u32 flags; /* FACS flags */ - u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ - u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ - u8 version; /* Version 2 */ - u8 res1[3]; - u32 ospm_flags; /* OSPM enabled flags */ - u8 res2[24]; -}; - -/* MADT flags */ -#define ACPI_MADT_PCAT_COMPAT (1 << 0) - -/* MADT (Multiple APIC Description Table) */ -struct acpi_madt { - struct acpi_table_header header; - u32 lapic_addr; /* Local APIC address */ - u32 flags; /* Multiple APIC flags */ -}; - -/* MADT: APIC Structure Type*/ -enum acpi_apic_types { - ACPI_APIC_LAPIC = 0, /* Processor local APIC */ - ACPI_APIC_IOAPIC, /* I/O APIC */ - ACPI_APIC_IRQ_SRC_OVERRIDE, /* Interrupt source override */ - ACPI_APIC_NMI_SRC, /* NMI source */ - ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */ - ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */ - ACPI_APIC_IOSAPIC, /* I/O SAPIC */ - ACPI_APIC_LSAPIC, /* Local SAPIC */ - ACPI_APIC_PLATFORM_IRQ_SRC, /* Platform interrupt sources */ - ACPI_APIC_LX2APIC, /* Processor local x2APIC */ - ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */ -}; - -/* MADT: Processor Local APIC Structure */ - -#define LOCAL_APIC_FLAG_ENABLED (1 << 0) - -struct acpi_madt_lapic { - u8 type; /* Type (0) */ - u8 length; /* Length in bytes (8) */ - u8 processor_id; /* ACPI processor ID */ - u8 apic_id; /* Local APIC ID */ - u32 flags; /* Local APIC flags */ -}; - -/* MADT: I/O APIC Structure */ -struct acpi_madt_ioapic { - u8 type; /* Type (1) */ - u8 length; /* Length in bytes (12) */ - u8 ioapic_id; /* I/O APIC ID */ - u8 reserved; - u32 ioapic_addr; /* I/O APIC address */ - u32 gsi_base; /* Global system interrupt base */ -}; - -/* MADT: Interrupt Source Override Structure */ -struct __packed acpi_madt_irqoverride { - u8 type; /* Type (2) */ - u8 length; /* Length in bytes (10) */ - u8 bus; /* ISA (0) */ - u8 source; /* Bus-relative int. source (IRQ) */ - u32 gsirq; /* Global system interrupt */ - u16 flags; /* MPS INTI flags */ -}; - -/* MADT: Local APIC NMI Structure */ -struct __packed acpi_madt_lapic_nmi { - u8 type; /* Type (4) */ - u8 length; /* Length in bytes (6) */ - u8 processor_id; /* ACPI processor ID */ - u16 flags; /* MPS INTI flags */ - u8 lint; /* Local APIC LINT# */ -}; - -/* MCFG (PCI Express MMIO config space BAR description table) */ -struct acpi_mcfg { - struct acpi_table_header header; - u8 reserved[8]; -}; - -struct acpi_mcfg_mmconfig { - u32 base_address_l; - u32 base_address_h; - u16 pci_segment_group_number; - u8 start_bus_number; - u8 end_bus_number; - u8 reserved[4]; -}; - -/* PM1_CNT bit defines */ -#define PM1_CNT_SCI_EN (1 << 0) - -/* ACPI global NVS structure */ +struct acpi_facs; +struct acpi_fadt; struct acpi_global_nvs; - -/* CSRT (Core System Resource Table) */ -struct acpi_csrt { - struct acpi_table_header header; -}; - -struct acpi_csrt_group { - u32 length; - u32 vendor_id; - u32 subvendor_id; - u16 device_id; - u16 subdevice_id; - u16 revision; - u16 reserved; - u32 shared_info_length; -}; - -struct acpi_csrt_shared_info { - u16 major_version; - u16 minor_version; - u32 mmio_base_low; - u32 mmio_base_high; - u32 gsi_interrupt; - u8 interrupt_polarity; - u8 interrupt_mode; - u8 num_channels; - u8 dma_address_width; - u16 base_request_line; - u16 num_handshake_signals; - u32 max_block_size; -}; - -/* DBG2 definitions are partially used for SPCR interface_type */ - -/* Types for port_type field */ - -#define ACPI_DBG2_SERIAL_PORT 0x8000 -#define ACPI_DBG2_1394_PORT 0x8001 -#define ACPI_DBG2_USB_PORT 0x8002 -#define ACPI_DBG2_NET_PORT 0x8003 - -/* Subtypes for port_subtype field */ - -#define ACPI_DBG2_16550_COMPATIBLE 0x0000 -#define ACPI_DBG2_16550_SUBSET 0x0001 -#define ACPI_DBG2_ARM_PL011 0x0003 -#define ACPI_DBG2_ARM_SBSA_32BIT 0x000D -#define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E -#define ACPI_DBG2_ARM_DCC 0x000F -#define ACPI_DBG2_BCM2835 0x0010 - -#define ACPI_DBG2_1394_STANDARD 0x0000 - -#define ACPI_DBG2_USB_XHCI 0x0000 -#define ACPI_DBG2_USB_EHCI 0x0001 - -#define ACPI_DBG2_UNKNOWN 0x00FF - -/* SPCR (Serial Port Console Redirection table) */ -struct __packed acpi_spcr { - struct acpi_table_header header; - u8 interface_type; - u8 reserved[3]; - struct acpi_gen_regaddr serial_port; - u8 interrupt_type; - u8 pc_interrupt; - u32 interrupt; /* Global system interrupt */ - u8 baud_rate; - u8 parity; - u8 stop_bits; - u8 flow_control; - u8 terminal_type; - u8 reserved1; - u16 pci_device_id; /* Must be 0xffff if not PCI device */ - u16 pci_vendor_id; /* Must be 0xffff if not PCI device */ - u8 pci_bus; - u8 pci_device; - u8 pci_function; - u32 pci_flags; - u8 pci_segment; - u32 reserved2; -}; +struct acpi_madt_ioapic; +struct acpi_madt_irqoverride; +struct acpi_madt_lapic_nmi; +struct acpi_mcfg_mmconfig; +struct acpi_table_header; /* These can be used by the target port */ diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h b/arch/x86/include/asm/arch-apollolake/global_nvs.h new file mode 100644 index 0000000000..fe62194b02 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015-2017 Intel Corp. + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + * Copyright Google LLC 2019 + * + * Modified from coreboot apollolake/include/soc/nvs.h + */ + +#ifndef _GLOBAL_NVS_H_ +#define _GLOBAL_NVS_H_ + +struct __packed acpi_global_nvs { + /* Miscellaneous */ + u8 pcnt; /* 0x00 - Processor Count */ + u8 ppcm; /* 0x01 - Max PPC State */ + u8 lids; /* 0x02 - LID State */ + u8 pwrs; /* 0x03 - AC Power State */ + u8 dpte; /* 0x04 - Enable DPTF */ + u32 cbmc; /* 0x05 - 0x08 - U-Boot Console */ + u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ + u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */ + u64 nhla; /* 0x19 - 0x20 - NHLT Address */ + u32 nhll; /* 0x21 - 0x24 - NHLT Length */ + u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */ + u8 scdp; /* 0x29 - SD_CD GPIO portid */ + u8 scdo; /* 0x2a - GPIO pad offset relative to the community */ + u8 uior; /* 0x2b - UART debug controller init on S3 resume */ + u8 ecps; /* 0x2c - SGX Enabled status */ + u64 emna; /* 0x2d - 0x34 EPC base address */ + u64 elng; /* 0x35 - 0x3c EPC Length */ + u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */ + u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ +}; + +#endif /* _GLOBAL_NVS_H_ */ diff --git a/arch/x86/include/asm/arch-coreboot/timestamp.h b/arch/x86/include/asm/arch-coreboot/timestamp.h index 9320afba56..85d42c02c4 100644 --- a/arch/x86/include/asm/arch-coreboot/timestamp.h +++ b/arch/x86/include/asm/arch-coreboot/timestamp.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * Taken from the coreboot version */ #ifndef __COREBOOT_TIMESTAMP_H__ diff --git a/arch/x86/include/asm/intel_pinctrl_defs.h b/arch/x86/include/asm/intel_pinctrl_defs.h index 6da06bb52b..1ea141f082 100644 --- a/arch/x86/include/asm/intel_pinctrl_defs.h +++ b/arch/x86/include/asm/intel_pinctrl_defs.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2015-2016 Intel Corp. * Copyright 2019 Google LLC * diff --git a/arch/x86/lib/acpi.c b/arch/x86/lib/acpi.c index cba9c24dd4..7431458dcf 100644 --- a/arch/x86/lib/acpi.c +++ b/arch/x86/lib/acpi.c @@ -4,7 +4,7 @@ */ #include <common.h> -#include <asm/acpi_table.h> +#include <acpi/acpi_table.h> #include <asm/io.h> #include <asm/tables.h> diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c index 197636c4b5..52410a515d 100644 --- a/arch/x86/lib/acpi_s3.c +++ b/arch/x86/lib/acpi_s3.c @@ -4,9 +4,9 @@ */ #include <common.h> -#include <acpi_s3.h> +#include <acpi/acpi_s3.h> +#include <acpi/acpi_table.h> #include <asm/acpi.h> -#include <asm/acpi_table.h> #include <asm/post.h> #include <linux/linkage.h> diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 66e32f21bd..9346e165d8 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -12,8 +12,8 @@ #include <dm/uclass-internal.h> #include <serial.h> #include <version.h> +#include <acpi/acpi_table.h> #include <asm/acpi/global_nvs.h> -#include <asm/acpi_table.h> #include <asm/ioapic.h> #include <asm/lapic.h> #include <asm/mpspec.h> @@ -471,6 +471,15 @@ static void acpi_create_spcr(struct acpi_spcr *spcr) spcr->pci_device_id = 0xffff; spcr->pci_vendor_id = 0xffff; + /* + * SPCR has no clue if the UART base clock speed is different + * to the default one. However, the SPCR 1.04 defines baud rate + * 0 as a preconfigured state of UART and OS is supposed not + * to touch the configuration of the serial device. + */ + if (serial_info.clock != SERIAL_DEFAULT_CLOCK) + spcr->baud_rate = 0; + /* Fix checksum */ header->checksum = table_compute_checksum((void *)spcr, header->length); } diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index 2943e11d2a..c996fc588d 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -4,9 +4,9 @@ */ #include <common.h> -#include <acpi_s3.h> #include <malloc.h> #include <vbe.h> +#include <acpi/acpi_s3.h> #include <asm/coreboot_tables.h> #include <asm/e820.h> diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 5eff0f99aa..267527eb34 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -4,11 +4,11 @@ */ #include <common.h> -#include <acpi_s3.h> #include <cpu_func.h> #include <dm.h> #include <errno.h> #include <rtc.h> +#include <acpi/acpi_s3.h> #include <asm/cmos_layout.h> #include <asm/early_cmos.h> #include <asm/io.h> diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c index aee2a05044..0a726807c2 100644 --- a/arch/x86/lib/fsp1/fsp_common.c +++ b/arch/x86/lib/fsp1/fsp_common.c @@ -4,11 +4,11 @@ */ #include <common.h> -#include <acpi_s3.h> #include <dm.h> #include <errno.h> #include <malloc.h> #include <rtc.h> +#include <acpi/acpi_s3.h> #include <asm/cmos_layout.h> #include <asm/early_cmos.h> #include <asm/io.h> diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index 90a238a224..c8f2c09b6a 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -5,9 +5,9 @@ */ #include <common.h> -#include <acpi_s3.h> #include <handoff.h> #include <spl.h> +#include <acpi/acpi_s3.h> #include <asm/arch/cpu.h> #include <asm/fsp/fsp_support.h> #include <asm/fsp2/fsp_api.h> diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 7aea722d0b..574d331d76 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -6,10 +6,10 @@ #include <common.h> #include <malloc.h> #include <smbios.h> +#include <acpi/acpi_table.h> #include <asm/sfi.h> #include <asm/mpspec.h> #include <asm/tables.h> -#include <asm/acpi_table.h> #include <asm/coreboot_tables.h> /** diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 9b5e767ccc..ffc09630b7 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -16,7 +16,7 @@ #include <env.h> #include <irq_func.h> #include <malloc.h> -#include <asm/acpi_table.h> +#include <acpi/acpi_table.h> #include <asm/io.h> #include <asm/ptrace.h> #include <asm/zimage.h> |