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-rw-r--r--arch/powerpc/cpu/mpc85xx/b4860_ids.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c10
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c73
-rw-r--r--arch/powerpc/cpu/mpc85xx/t1024_serdes.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/t1040_serdes.c8
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c5
-rw-r--r--arch/powerpc/include/asm/arch-mpc85xx/gpio.h15
-rw-r--r--arch/powerpc/include/asm/fsl_secure_boot.h2
-rw-r--r--arch/powerpc/include/asm/fsl_serdes.h7
-rw-r--r--arch/powerpc/lib/board.c21
10 files changed, 80 insertions, 65 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 598f7bd92e..fd7f5fa7e1 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -57,7 +57,7 @@ struct liodn_id_table liodn_tbl[] = {
SET_USB_LIODN(1, "fsl-usb2-dr", 553),
- SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 85d32fc612..4cf8853b72 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -424,7 +424,6 @@ void fsl_erratum_a007212_workaround(void)
ulong cpu_init_f(void)
{
- ulong flag = 0;
extern void m8560_cpm_reset (void);
#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
@@ -499,18 +498,11 @@ ulong cpu_init_f(void)
in_be32(&gur->dcsrcr);
#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-#ifdef CONFIG_DEEP_SLEEP
- /* disable the console if boot from deep sleep */
- if (in_be32(&gur->scrtsr[0]) & (1 << 3))
- flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
-#endif
-#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
- return flag;
+ return 0;
}
/* Implement a dummy function for those platforms w/o SERDES */
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 5cfae47069..acb1353e5d 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -15,16 +15,16 @@
#include "fsl_corenet2_serdes.h"
#ifdef CONFIG_SYS_FSL_SRDS_1
-static u64 serdes1_prtcl_map;
+static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
-static u64 serdes2_prtcl_map;
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
-static u64 serdes3_prtcl_map;
+static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
-static u64 serdes4_prtcl_map;
+static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef DEBUG
@@ -78,24 +78,30 @@ static const char *serdes_prtcl_str[] = {
[INTERLAKEN] = "INTERLAKEN",
[QSGMII_SW1_A] = "QSGMII_SW1_A",
[QSGMII_SW1_B] = "QSGMII_SW1_B",
+ [SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
+ [SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
+ [SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
+ [SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
+ [SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
+ [SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
};
#endif
int is_serdes_configured(enum srds_prtcl device)
{
- u64 ret = 0;
+ int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1
- ret |= (1ULL << device) & serdes1_prtcl_map;
+ ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
- ret |= (1ULL << device) & serdes2_prtcl_map;
+ ret |= serdes2_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
- ret |= (1ULL << device) & serdes3_prtcl_map;
+ ret |= serdes3_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
- ret |= (1ULL << device) & serdes4_prtcl_map;
+ ret |= serdes4_prtcl_map[device];
#endif
return !!ret;
@@ -171,12 +177,14 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
#define BCAP_OVD_MASK 0x10000000
#define BYP_CAL_MASK 0x02000000
-u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
+void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
+ u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
+
+ memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
struct ccsr_sfp_regs __iomem *sfp_regs =
(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
@@ -312,38 +320,43 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
- serdes_prtcl_map |= (1ULL << lane_prtcl);
+ if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
+ debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
+ else
+ serdes_prtcl_map[lane_prtcl] = 1;
}
-
- return serdes_prtcl_map;
}
void fsl_serdes_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
- serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+ serdes_init(FSL_SRDS_1,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
+ serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
- serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+ serdes_init(FSL_SRDS_2,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
+ serdes2_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
- serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
- FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
- FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
+ serdes_init(FSL_SRDS_3,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
+ serdes3_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
- serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
- FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
- FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
+ serdes_init(FSL_SRDS_4,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
+ serdes4_prtcl_map);
#endif
}
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
index 7dc8385aa6..2ba314a7f6 100644
--- a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c
@@ -11,6 +11,7 @@
static u8 serdes_cfg_tbl[][4] = {
+ [0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
[0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
[0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
@@ -20,6 +21,7 @@ static u8 serdes_cfg_tbl[][4] = {
[0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
[0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
[0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
+ [0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1},
[0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
[0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
[0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
index d86bb27372..d5dccd5cf2 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
@@ -33,10 +33,10 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
- [0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
- PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
- [0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
- PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
+ [0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
+ PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
+ [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
+ PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 2d28eb2655..c92589fb9d 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -15,6 +15,7 @@
#include <netdev.h>
#include <asm/cache.h>
#include <asm/io.h>
+#include <vsc9953.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -271,5 +272,9 @@ int cpu_eth_init(bd_t *bis)
#ifdef CONFIG_FMAN_ENET
fm_standard_init(bis);
#endif
+
+#ifdef CONFIG_VSC9953
+ vsc9953_init(bis);
+#endif
return 0;
}
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
new file mode 100644
index 0000000000..8beed3037a
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_MX85XX_GPIO_H
+#define __ASM_ARCH_MX85XX_GPIO_H
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 14c6fc3cfe..b4c0c99b39 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -12,6 +12,8 @@
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
#elif defined(CONFIG_BSC9132QDS)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
+#elif defined(CONFIG_C29XPCIE)
+#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
#else
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
#endif
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 8e0e190003..45e248eba1 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -87,6 +87,13 @@ enum srds_prtcl {
SGMII_2500_FM2_DTSEC6,
SGMII_2500_FM2_DTSEC9,
SGMII_2500_FM2_DTSEC10,
+ SGMII_SW1_MAC1,
+ SGMII_SW1_MAC2,
+ SGMII_SW1_MAC3,
+ SGMII_SW1_MAC4,
+ SGMII_SW1_MAC5,
+ SGMII_SW1_MAC6,
+ SERDES_PRCTL_COUNT /* Keep this item the last one */
};
enum srds {
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index e6d5355f26..91645d36ee 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -346,13 +346,6 @@ void board_init_f(ulong bootflag)
#ifdef CONFIG_PRAM
ulong reg;
#endif
-#ifdef CONFIG_DEEP_SLEEP
- const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
- u32 start_addr;
- typedef void (*func_t)(void);
- func_t kernel_resume;
-#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -372,20 +365,6 @@ void board_init_f(ulong bootflag)
if ((*init_fnc_ptr) () != 0)
hang();
-#ifdef CONFIG_DEEP_SLEEP
- /* Jump to kernel in deep sleep case */
- if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
- l2cache_init();
-#if defined(CONFIG_RAMBOOT_PBL)
- disable_cpc_sram();
-#endif
- enable_cpc();
- start_addr = in_be32(&scfg->sparecr[1]);
- kernel_resume = (func_t)start_addr;
- kernel_resume();
- }
-#endif
-
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
generated by cgit (git 2.34.1) at 2024-12-24 20:01:15 +0000