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-rw-r--r--arch/arm/cpu/armv7/at91/cpu.c2
-rw-r--r--arch/arm/cpu/armv8/transition.S2
-rw-r--r--arch/arm/include/asm/arch-vf610/crm_regs.h11
-rw-r--r--arch/arm/include/asm/arch-vf610/imx-regs.h4
-rw-r--r--arch/arm/include/asm/arch-vf610/iomux-vf610.h17
-rw-r--r--arch/arm/include/asm/imx-common/iomux-v3.h2
-rw-r--r--arch/arm/lib/vectors.S2
-rw-r--r--arch/avr32/cpu/cache.c20
-rw-r--r--arch/avr32/include/asm/arch-at32ap700x/cacheflush.h2
-rw-r--r--arch/avr32/include/asm/dma-mapping.h6
-rw-r--r--arch/avr32/lib/board.c4
11 files changed, 50 insertions, 22 deletions
diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c
index 2fbf60d542..8d86f97e3d 100644
--- a/arch/arm/cpu/armv7/at91/cpu.c
+++ b/arch/arm/cpu/armv7/at91/cpu.c
@@ -61,6 +61,8 @@ int print_cpuinfo(void)
void enable_caches(void)
{
+ icache_enable();
+ dcache_enable();
}
unsigned int get_chip_id(void)
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
index e0a5946009..38dea5c518 100644
--- a/arch/arm/cpu/armv8/transition.S
+++ b/arch/arm/cpu/armv8/transition.S
@@ -43,7 +43,7 @@ ENTRY(armv8_switch_to_el1)
mrs x0, cnthctl_el2
orr x0, x0, #0x3 /* Enable EL1 access to timers */
msr cnthctl_el2, x0
- msr cntvoff_el2, x0
+ msr cntvoff_el2, xzr
mrs x0, cntkctl_el1
orr x0, x0, #0x3 /* Enable EL0 access to timers */
msr cntkctl_el1, x0
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index e17c7d1f70..5256624adf 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -150,6 +150,9 @@ struct anadig_reg {
#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
+#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22
+#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
+#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22)
#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
@@ -161,6 +164,11 @@ struct anadig_reg {
#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
+#define CCM_CSCDR3_QSPI0_EN (1 << 4)
+#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3)
+#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2)
+#define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3)
+
#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
@@ -170,6 +178,7 @@ struct anadig_reg {
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
+#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 0c28e1b840..bd6f680b63 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -87,6 +87,8 @@
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
+#define QSPI0_AMBA_BASE 0x20000000
+
/* MUX mode and PAD ctrl are in one register */
#define CONFIG_IOMUX_SHARE_CONF_REG
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index 88807d8db4..a965641681 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -20,6 +20,9 @@
#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
+
enum {
VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
@@ -53,6 +56,18 @@ enum {
VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
+ VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+ VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index cca920b28e..ff45618e45 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -123,12 +123,14 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_SPEED_MED (1 << 12)
#define PAD_CTL_SPEED_HIGH (3 << 12)
+#define PAD_CTL_DSE_150ohm (1 << 6)
#define PAD_CTL_DSE_50ohm (3 << 6)
#define PAD_CTL_DSE_25ohm (6 << 6)
#define PAD_CTL_DSE_20ohm (7 << 6)
#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PKE (1 << 3)
#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index d68cc477dc..e6538eff43 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -43,8 +43,6 @@
*************************************************************************
*/
-_start:
-
#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
.word CONFIG_SYS_DV_NOR_BOOT_CFG
#endif
diff --git a/arch/avr32/cpu/cache.c b/arch/avr32/cpu/cache.c
index ab0374e587..b3ffc3348b 100644
--- a/arch/avr32/cpu/cache.c
+++ b/arch/avr32/cpu/cache.c
@@ -24,31 +24,31 @@ void dcache_clean_range(volatile void *start, size_t size)
sync_write_buffer();
}
-void dcache_invalidate_range(volatile void *start, size_t size)
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
- unsigned long v, begin, end, linesz;
+ unsigned long v, linesz;
linesz = CONFIG_SYS_DCACHE_LINESZ;
/* You asked for it, you got it */
- begin = (unsigned long)start & ~(linesz - 1);
- end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+ start = start & ~(linesz - 1);
+ stop = (stop + linesz - 1) & ~(linesz - 1);
- for (v = begin; v < end; v += linesz)
+ for (v = start; v < stop; v += linesz)
dcache_invalidate_line((void *)v);
}
-void dcache_flush_range(volatile void *start, size_t size)
+void flush_dcache_range(unsigned long start, unsigned long stop)
{
- unsigned long v, begin, end, linesz;
+ unsigned long v, linesz;
linesz = CONFIG_SYS_DCACHE_LINESZ;
/* You asked for it, you got it */
- begin = (unsigned long)start & ~(linesz - 1);
- end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+ start = start & ~(linesz - 1);
+ stop = (stop + linesz - 1) & ~(linesz - 1);
- for (v = begin; v < end; v += linesz)
+ for (v = start; v < stop; v += linesz)
dcache_flush_line((void *)v);
sync_write_buffer();
diff --git a/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h b/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h
index 13d6d3aed3..e08cd9de6d 100644
--- a/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h
+++ b/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h
@@ -49,9 +49,7 @@ static inline void icache_invalidate_line(volatile void *vaddr)
* Applies the above functions on all lines that are touched by the
* specified virtual address range.
*/
-void dcache_invalidate_range(volatile void *start, size_t len);
void dcache_clean_range(volatile void *start, size_t len);
-void dcache_flush_range(volatile void *start, size_t len);
void icache_invalidate_range(volatile void *start, size_t len);
static inline void dcache_flush_unlocked(void)
diff --git a/arch/avr32/include/asm/dma-mapping.h b/arch/avr32/include/asm/dma-mapping.h
index 95ea81ff5e..dbdd2fee38 100644
--- a/arch/avr32/include/asm/dma-mapping.h
+++ b/arch/avr32/include/asm/dma-mapping.h
@@ -23,13 +23,15 @@ static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
switch (dir) {
case DMA_BIDIRECTIONAL:
- dcache_flush_range(vaddr, len);
+ flush_dcache_range((unsigned long)vaddr,
+ (unsigned long)vaddr + len);
break;
case DMA_TO_DEVICE:
dcache_clean_range(vaddr, len);
break;
case DMA_FROM_DEVICE:
- dcache_invalidate_range(vaddr, len);
+ invalidate_dcache_range((unsigned long)vaddr,
+ (unsigned long)vaddr + len);
break;
default:
/* This will cause a linker error */
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index 7680102f52..bf0997f98d 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -65,8 +65,8 @@ static void dma_alloc_init(void)
printf("DMA: Using memory from 0x%08lx to 0x%08lx\n",
dma_alloc_start, dma_alloc_end);
- dcache_invalidate_range(cached(dma_alloc_start),
- dma_alloc_end - dma_alloc_start);
+ invalidate_dcache_range((unsigned long)cached(dma_alloc_start),
+ dma_alloc_end);
}
void *dma_alloc_coherent(size_t len, unsigned long *handle)
generated by cgit (git 2.34.1) at 2025-01-19 21:34:44 +0000