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-rw-r--r--arch/arm/cpu/arm1136/mx35/generic.c10
-rw-r--r--arch/arm/cpu/arm926ejs/mx25/generic.c8
-rw-r--r--arch/arm/cpu/armv7/vf610/generic.c10
-rw-r--r--arch/arm/cpu/armv8/s32v234/generic.c2
-rw-r--r--arch/arm/dts/at91-sama5d2_xplained.dts36
-rw-r--r--arch/arm/include/asm/arch-meson/eth.h3
-rw-r--r--arch/arm/include/asm/arch-meson/sm.h4
-rw-r--r--arch/arm/include/asm/global_data.h2
-rw-r--r--arch/arm/mach-imx/cpu.c6
-rw-r--r--arch/arm/mach-imx/mx6/litesom.c4
-rw-r--r--arch/arm/mach-imx/mx7/clock.c4
-rw-r--r--arch/arm/mach-imx/mx7ulp/clock.c2
-rw-r--r--arch/arm/mach-imx/speed.c4
-rw-r--r--arch/arm/mach-meson/board-common.c31
-rw-r--r--arch/arm/mach-meson/sm.c24
-rw-r--r--arch/m68k/cpu/mcf5445x/cpu_init.c2
16 files changed, 106 insertions, 46 deletions
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index cbc43644a9..a651b8c341 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -14,8 +14,8 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
#endif
#include <netdev.h>
#include <spl.h>
@@ -27,7 +27,7 @@
#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
@@ -446,7 +446,7 @@ int cpu_eth_init(bd_t *bis)
return rc;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
@@ -459,7 +459,7 @@ int cpu_mmc_init(bd_t *bis)
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
index 2795a5f22e..5fcf06ae1a 100644
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -16,8 +16,8 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
@@ -233,7 +233,7 @@ int cpu_eth_init(bd_t *bis)
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#else
@@ -243,7 +243,7 @@ int get_clocks(void)
return 0;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index f962903484..337f4af7a8 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -10,11 +10,11 @@
#include <asm/arch/crm_regs.h>
#include <asm/mach-imx/sys_proto.h>
#include <netdev.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
@@ -345,7 +345,7 @@ int cpu_eth_init(bd_t *bis)
return rc;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
int cpu_mmc_init(bd_t *bis)
{
return fsl_esdhc_mmc_init(bis);
@@ -354,7 +354,7 @@ int cpu_mmc_init(bd_t *bis)
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#endif
return 0;
diff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c
index 273b88e9d3..2c4ea36e07 100644
--- a/arch/arm/cpu/armv8/s32v234/generic.c
+++ b/arch/arm/cpu/armv8/s32v234/generic.c
@@ -342,7 +342,7 @@ int cpu_eth_init(bd_t * bis)
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
#endif
return 0;
diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts
index c0708feeb7..7f0d1696ba 100644
--- a/arch/arm/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/dts/at91-sama5d2_xplained.dts
@@ -79,26 +79,18 @@
};
qspi0: spi@f0020000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi0_sck_cs_default &pinctrl_qspi0_dat_default>;
status = "okay";
+ u-boot,dm-pre-reloc;
flash@0 {
- compatible = "atmel,sama5d2-qspi-flash";
+ compatible = "jedec,spi-nor";
reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi0_default>;
spi-max-frequency = <83000000>;
-
- partition@00000000 {
- label = "boot";
- reg = <0x00000000 0x00c00000>;
- };
-
- partition@00c00000 {
- label = "rootfs";
- reg = <0x00c00000 0x00000000>;
- };
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
};
};
@@ -208,14 +200,20 @@
bias-disable;
};
- pinctrl_qspi0_default: qspi0_default {
+ pinctrl_qspi0_sck_cs_default: qspi0_sck_cs_default {
pinmux = <PIN_PA22__QSPI0_SCK>,
- <PIN_PA23__QSPI0_CS>,
- <PIN_PA24__QSPI0_IO0>,
+ <PIN_PA23__QSPI0_CS>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_qspi0_dat_default: qspi0_dat_default {
+ pinmux = <PIN_PA24__QSPI0_IO0>,
<PIN_PA25__QSPI0_IO1>,
<PIN_PA26__QSPI0_IO2>,
<PIN_PA27__QSPI0_IO3>;
- bias-disable;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
};
pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h
index 08acc5cbf7..f765cd7c4c 100644
--- a/arch/arm/include/asm/arch-meson/eth.h
+++ b/arch/arm/include/asm/arch-meson/eth.h
@@ -19,4 +19,7 @@ enum {
*/
void meson_eth_init(phy_interface_t mode, unsigned int flags);
+/* Generate an unique MAC address based on the HW serial */
+int meson_generate_serial_ethaddr(void);
+
#endif /* __MESON_ETH_H__ */
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
index 83d6441803..60d04ae228 100644
--- a/arch/arm/include/asm/arch-meson/sm.h
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -8,4 +8,8 @@
ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
+#define SM_SERIAL_SIZE 12
+
+int meson_sm_get_serial(void *buffer, size_t size);
+
#endif /* __MESON_SM_H__ */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index a81b1061df..17740147ea 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -9,7 +9,7 @@
/* Architecture-specific global data */
struct arch_global_data {
-#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
u32 sdhc_clk;
#endif
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index d62ff6ef25..3a8cf30c06 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -21,8 +21,8 @@
#include <thermal.h>
#include <sata.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
#endif
static u32 reset_cause = -1;
@@ -258,7 +258,7 @@ int cpu_eth_init(bd_t *bis)
return rc;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c
index c332d6805b..4f4df7433b 100644
--- a/arch/arm/mach-imx/mx6/litesom.c
+++ b/arch/arm/mach-imx/mx6/litesom.c
@@ -16,7 +16,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <linux/sizes.h>
#include <mmc.h>
@@ -49,7 +49,7 @@ static iomux_v3_cfg_t const emmc_pads[] = {
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
#define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10)
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index e364b162d9..4f9724cadb 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -19,13 +19,13 @@ struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
ANATOP_BASE_ADDR;
struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index fac9011388..dc317fe810 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c
index ab134d06c5..f9e486c7df 100644
--- a/arch/arm/mach-imx/speed.c
+++ b/arch/arm/mach-imx/speed.c
@@ -11,13 +11,13 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_USDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c
index 8c41301674..18383f774e 100644
--- a/arch/arm/mach-meson/board-common.c
+++ b/arch/arm/mach-meson/board-common.c
@@ -7,6 +7,7 @@
#include <asm/arch/boot.h>
#include <linux/libfdt.h>
#include <linux/err.h>
+#include <environment.h>
#include <asm/arch/mem.h>
#include <asm/arch/sm.h>
#include <asm/armv8/mmu.h>
@@ -67,6 +68,36 @@ void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
}
}
+int meson_generate_serial_ethaddr(void)
+{
+ u8 mac_addr[ARP_HLEN];
+ char serial[SM_SERIAL_SIZE];
+ u32 sid;
+ u16 sid16;
+
+ if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) {
+ sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE);
+ sid16 = crc16_ccitt(0, (unsigned char *)serial, SM_SERIAL_SIZE);
+
+ /* Ensure the NIC specific bytes of the mac are not all 0 */
+ if ((sid & 0xffffff) == 0)
+ sid |= 0x800000;
+
+ /* Non OUI / registered MAC address */
+ mac_addr[0] = ((sid16 >> 8) & 0xfc) | 0x02;
+ mac_addr[1] = (sid16 >> 0) & 0xff;
+ mac_addr[2] = (sid >> 24) & 0xff;
+ mac_addr[3] = (sid >> 16) & 0xff;
+ mac_addr[4] = (sid >> 8) & 0xff;
+ mac_addr[5] = (sid >> 0) & 0xff;
+
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ } else
+ return -EINVAL;
+
+ return 0;
+}
+
static void meson_set_boot_source(void)
{
const char *source;
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index a07b46895d..05b7f0bdf2 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -6,12 +6,14 @@
*/
#include <common.h>
+#include <asm/arch/sm.h>
#include <linux/kernel.h>
#define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020
#define FN_GET_SHARE_MEM_OUTPUT_BASE 0x82000021
#define FN_EFUSE_READ 0x82000030
#define FN_EFUSE_WRITE 0x82000031
+#define FN_CHIP_ID 0x82000044
static void *shmem_input;
static void *shmem_output;
@@ -53,3 +55,25 @@ ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size)
return regs.regs[0];
}
+
+#define SM_CHIP_ID_LENGTH 119
+#define SM_CHIP_ID_OFFSET 4
+#define SM_CHIP_ID_SIZE 12
+
+int meson_sm_get_serial(void *buffer, size_t size)
+{
+ struct pt_regs regs;
+
+ meson_init_shmem();
+
+ regs.regs[0] = FN_CHIP_ID;
+ regs.regs[1] = 0;
+ regs.regs[2] = 0;
+
+ smc_call(&regs);
+
+ memcpy(buffer, shmem_output + SM_CHIP_ID_OFFSET,
+ min_t(size_t, size, SM_CHIP_ID_SIZE));
+
+ return 0;
+}
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 8f4991c1cb..134510b00f 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -200,7 +200,7 @@ void cpu_init_f(void)
/* Lowest slew rate for UART0,1,2 */
out_8(&gpio->srcr_uart, 0x00);
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/* eSDHC pin as faster speed */
out_8(&gpio->srcr_sdhc, 0x03);
generated by cgit (git 2.34.1) at 2025-01-28 17:22:42 +0000