diff options
Diffstat (limited to 'arch')
169 files changed, 11541 insertions, 707 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 9be02d1319..7f3cbe2ec8 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -160,6 +160,7 @@ config X86 select TIMER select USE_PRIVATE_LIBGCC select X86_TSC_TIMER + imply HAS_ROM if X86_RESET_VECTOR imply BLK imply CMD_DM imply CMD_FPGA_LOADMK diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cd5fb0d353..6b8a32c38d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -64,6 +64,8 @@ endif config GIC_V3_ITS bool "ARM GICV3 ITS" + select REGMAP + select SYSCON help ARM GICV3 Interrupt translation service (ITS). Basic support for programming locality specific peripheral @@ -501,23 +503,6 @@ config TPL_USE_ARCH_MEMSET Such an implementation may be faster under some conditions but may increase the binary size. -config SET_STACK_SIZE - bool "Enable an option to set max stack size that can be used" - default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ - help - This will enable an option to set max stack size that can be - used by U-Boot. - -config STACK_SIZE - hex "Define max stack size that can be used by U-Boot" - depends on SET_STACK_SIZE - default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP - default 0x1000000 if ARCH_ZYNQ - help - Define Max stack size that can be used by U-Boot so that the - initrd_high will be calculated as base stack pointer minus this - stack size. - config ARM64_SUPPORT_AARCH32 bool "ARM64 system support AArch32 execution state" depends on ARM64 @@ -732,6 +717,15 @@ config TARGET_BCMNS2 ARMv8 Cortex-A57 processors targeting a broad range of networking applications. +config TARGET_BCMNS3 + bool "Support Broadcom NS3" + select ARM64 + select BOARD_LATE_INIT + help + Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit + ARMv8 Cortex-A72 processors targeting a broad range of networking + applications. + config ARCH_EXYNOS bool "Samsung EXYNOS" select DM @@ -767,6 +761,17 @@ config ARCH_INTEGRATOR select PL01X_SERIAL imply CMD_DM +config ARCH_IPQ40XX + bool "Qualcomm IPQ40xx SoCs" + select CPU_V7A + select DM + select DM_GPIO + select DM_SERIAL + select PINCTRL + select CLK + select OF_CONTROL + imply CMD_DM + config ARCH_KEYSTONE bool "TI Keystone" select CMD_POWEROFF @@ -905,6 +910,11 @@ config ARCH_MX5 select CPU_V7A imply MXC_GPIO +config ARCH_NEXELL + bool "Nexell S5P4418/S5P6818 SoC" + select ENABLE_ARM_SOC_BOOT0_HOOK + select DM + config ARCH_OWL bool "Actions Semi OWL SoCs" select DM @@ -1793,6 +1803,8 @@ source "arch/arm/mach-highbank/Kconfig" source "arch/arm/mach-integrator/Kconfig" +source "arch/arm/mach-ipq40xx/Kconfig" + source "arch/arm/mach-k3/Kconfig" source "arch/arm/mach-keystone/Kconfig" @@ -1879,6 +1891,8 @@ source "arch/arm/cpu/armv8/Kconfig" source "arch/arm/mach-imx/Kconfig" +source "arch/arm/mach-nexell/Kconfig" + source "board/bosch/shc/Kconfig" source "board/bosch/guardian/Kconfig" source "board/CarMediaLab/flea3/Kconfig" @@ -1896,6 +1910,7 @@ source "board/broadcom/bcm968580xref/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" source "board/broadcom/bcmns2/Kconfig" +source "board/broadcom/bcmns3/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/cirrus/edb93xx/Kconfig" source "board/eets/pdu001/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 94eb50bf72..bf3890e99b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -58,6 +58,7 @@ machine-$(CONFIG_ARCH_BCMSTB) += bcmstb machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_EXYNOS) += exynos machine-$(CONFIG_ARCH_HIGHBANK) += highbank +machine-$(CONFIG_ARCH_IPQ40XX) += ipq40xx machine-$(CONFIG_ARCH_K3) += k3 machine-$(CONFIG_ARCH_KEYSTONE) += keystone machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood @@ -65,6 +66,7 @@ machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu +machine-$(CONFIG_ARCH_NEXELL) += nexell machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 machine-$(CONFIG_ARCH_ORION5X) += orion5x machine-$(CONFIG_ARCH_OWL) += owl diff --git a/arch/arm/config.mk b/arch/arm/config.mk index f25603109e..4153f7e371 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -122,7 +122,7 @@ endif ifneq ($(CONFIG_SPL_BUILD),y) # Check that only R_ARM_RELATIVE relocations are generated. -ALL-y += checkarmreloc +INPUTS-y += checkarmreloc # The movt / movw can hardcode 16 bit parts of the addresses in the # instruction. Relocation is not supported for that case, so disable # such usage by requiring word relocations. @@ -154,17 +154,17 @@ endif ifneq ($(CONFIG_IMX_CONFIG),) ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD -ALL-y += SPL +INPUTS-y += SPL endif else ifeq ($(CONFIG_OF_SEPARATE),y) -ALL-y += u-boot-dtb.imx +INPUTS-y += u-boot-dtb.imx else -ALL-y += u-boot.imx +INPUTS-y += u-boot.imx endif endif ifneq ($(CONFIG_VF610),) -ALL-y += u-boot.vyb +INPUTS-y += u-boot.vyb endif endif diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 8c955d0d52..0e83e394d5 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -42,3 +42,5 @@ obj-$(CONFIG_RMOBILE) += rmobile/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_VF610) += vf610/ +obj-$(CONFIG_ARCH_S5P4418) += s5p4418/ +obj-$(CONFIG_ARCH_NEXELL) += s5p-common/ diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index 12cf804e88..bfe02389cd 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -3,9 +3,14 @@ # Copyright (C) 2009 Samsung Electronics # Minkyu Kang <mk7.kang@samsung.com> -obj-y += cpu_info.o +ifdef CONFIG_ARCH_NEXELL +obj-$(CONFIG_PWM_NX) += pwm.o +obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o +else +obj-y += cpu_info.o ifndef CONFIG_SPL_BUILD -obj-y += timer.o -obj-y += sromc.o -obj-$(CONFIG_PWM) += pwm.o +obj-y += timer.o +obj-y += sromc.o +obj-$(CONFIG_PWM) += pwm.o +endif endif diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 6b9e865803..aef2e5574b 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -15,7 +15,11 @@ int pwm_enable(int pwm_id) { const struct s5p_timer *pwm = +#if defined(CONFIG_ARCH_NEXELL) + (struct s5p_timer *)PHY_BASEADDR_PWM; +#else (struct s5p_timer *)samsung_get_base_timer(); +#endif unsigned long tcon; tcon = readl(&pwm->tcon); @@ -29,7 +33,11 @@ int pwm_enable(int pwm_id) void pwm_disable(int pwm_id) { const struct s5p_timer *pwm = +#if defined(CONFIG_ARCH_NEXELL) + (struct s5p_timer *)PHY_BASEADDR_PWM; +#else (struct s5p_timer *)samsung_get_base_timer(); +#endif unsigned long tcon; tcon = readl(&pwm->tcon); @@ -43,14 +51,43 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) unsigned long tin_parent_rate; unsigned int div; +#if defined(CONFIG_ARCH_NEXELL) + unsigned int pre_div; + const struct s5p_timer *pwm = + (struct s5p_timer *)PHY_BASEADDR_PWM; + unsigned int val; + struct clk *clk = clk_get(CORECLK_NAME_PCLK); + + tin_parent_rate = clk_get_rate(clk); +#else tin_parent_rate = get_pwm_clk(); +#endif + +#if defined(CONFIG_ARCH_NEXELL) + writel(0, &pwm->tcfg0); + val = readl(&pwm->tcfg0); + + if (pwm_id < 2) + div = ((val >> 0) & 0xff) + 1; + else + div = ((val >> 8) & 0xff) + 1; + writel(0, &pwm->tcfg1); + val = readl(&pwm->tcfg1); + val = (val >> MUX_DIV_SHIFT(pwm_id)) & 0xF; + pre_div = (1UL << val); + + freq = tin_parent_rate / div / pre_div; + + return freq; +#else for (div = 2; div <= 16; div *= 2) { if ((tin_parent_rate / (div << 16)) < freq) return tin_parent_rate / div; } return tin_parent_rate / 16; +#endif } #define NS_IN_SEC 1000000000UL @@ -58,7 +95,11 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) int pwm_config(int pwm_id, int duty_ns, int period_ns) { const struct s5p_timer *pwm = +#if defined(CONFIG_ARCH_NEXELL) + (struct s5p_timer *)PHY_BASEADDR_PWM; +#else (struct s5p_timer *)samsung_get_base_timer(); +#endif unsigned int offset; unsigned long tin_rate; unsigned long tin_ns; @@ -84,7 +125,12 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns) tin_rate = pwm_calc_tin(pwm_id, frequency); tin_ns = NS_IN_SEC / tin_rate; - tcnt = period_ns / tin_ns; + + if (IS_ENABLED(CONFIG_ARCH_NEXELL)) + /* The counter starts at zero. */ + tcnt = (period_ns / tin_ns) - 1; + else + tcnt = period_ns / tin_ns; /* Note, counters count down */ tcmp = duty_ns / tin_ns; @@ -115,7 +161,11 @@ int pwm_init(int pwm_id, int div, int invert) { u32 val; const struct s5p_timer *pwm = +#if defined(CONFIG_ARCH_NEXELL) + (struct s5p_timer *)PHY_BASEADDR_PWM; +#else (struct s5p_timer *)samsung_get_base_timer(); +#endif unsigned long ticks_per_period; unsigned int offset, prescaler; @@ -148,7 +198,12 @@ int pwm_init(int pwm_id, int div, int invert) ticks_per_period = -1UL; } else { const unsigned long pwm_hz = 1000; +#if defined(CONFIG_ARCH_NEXELL) + struct clk *clk = clk_get(CORECLK_NAME_PCLK); + unsigned long timer_rate_hz = clk_get_rate(clk) / +#else unsigned long timer_rate_hz = get_pwm_clk() / +#endif ((prescaler + 1) * (1 << div)); ticks_per_period = timer_rate_hz / pwm_hz; diff --git a/arch/arm/cpu/armv7/s5p4418/Makefile b/arch/arm/cpu/armv7/s5p4418/Makefile new file mode 100644 index 0000000000..321b257b6d --- /dev/null +++ b/arch/arm/cpu/armv7/s5p4418/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 Nexell +# Hyunseok, Jung <hsjung@nexell.co.kr> + +obj-y += cpu.o diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c new file mode 100644 index 0000000000..8add9474ad --- /dev/null +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Nexell + * Hyunseok, Jung <hsjung@nexell.co.kr> + */ + +#include <common.h> +#include <command.h> +#include <asm/system.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <asm/io.h> +#include <asm/arch/nexell.h> +#include <asm/arch/clk.h> +#include <asm/arch/reset.h> +#include <asm/arch/tieoff.h> +#include <cpu_func.h> +#include <linux/delay.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_ARCH_CPU_INIT +#error must be define the macro "CONFIG_ARCH_CPU_INIT" +#endif + +void s_init(void) +{ +} + +static void cpu_soc_init(void) +{ + /* + * NOTE> ALIVE Power Gate must enable for Alive register access. + * must be clear wfi jump address + */ + writel(1, ALIVEPWRGATEREG); + writel(0xFFFFFFFF, SCR_ARM_SECOND_BOOT); + + /* write 0xf0 on alive scratchpad reg for boot success check */ + writel(readl(SCR_SIGNAGURE_READ) | 0xF0, (SCR_SIGNAGURE_SET)); + + /* set l2 cache tieoff */ + nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_0, 1); + nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1); +} + +#ifdef CONFIG_PL011_SERIAL +static void serial_device_init(void) +{ + char dev[10]; + int id; + + sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX); + id = RESET_ID_UART0 + CONFIG_CONS_INDEX; + + struct clk *clk = clk_get((const char *)dev); + + /* reset control: Low active ___|--- */ + nx_rstcon_setrst(id, RSTCON_ASSERT); + udelay(10); + nx_rstcon_setrst(id, RSTCON_NEGATE); + udelay(10); + + /* set clock */ + clk_disable(clk); + clk_set_rate(clk, CONFIG_PL011_CLOCK); + clk_enable(clk); +} +#endif + +int arch_cpu_init(void) +{ + flush_dcache_all(); + cpu_soc_init(); + clk_init(); + + if (IS_ENABLED(CONFIG_PL011_SERIAL)) + serial_device_init(); + + return 0; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + return 0; +} +#endif + +void reset_cpu(ulong ignored) +{ + void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR; + const u32 sw_rst_enb_bitpos = 3; + const u32 sw_rst_enb_mask = 1 << sw_rst_enb_bitpos; + const u32 sw_rst_bitpos = 12; + const u32 sw_rst_mask = 1 << sw_rst_bitpos; + int pwrcont = 0x224; + int pwrmode = 0x228; + u32 read_value; + + read_value = readl((void *)(clkpwr_reg + pwrcont)); + + read_value &= ~sw_rst_enb_mask; + read_value |= 1 << sw_rst_enb_bitpos; + + writel(read_value, (void *)(clkpwr_reg + pwrcont)); + writel(sw_rst_mask, (void *)(clkpwr_reg + pwrmode)); +} + +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + return 0; +} +#endif /* CONFIG_ARCH_MISC_INIT */ diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 2e48df0eb9..7e33a183d5 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_S32V234) += s32v234/ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o +obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ diff --git a/arch/arm/cpu/armv8/bcmns3/Makefile b/arch/arm/cpu/armv8/bcmns3/Makefile new file mode 100644 index 0000000000..a35e29d11a --- /dev/null +++ b/arch/arm/cpu/armv8/bcmns3/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 Broadcom. + +obj-y += lowlevel.o diff --git a/arch/arm/cpu/armv8/bcmns3/lowlevel.S b/arch/arm/cpu/armv8/bcmns3/lowlevel.S new file mode 100644 index 0000000000..bf1a17ab03 --- /dev/null +++ b/arch/arm/cpu/armv8/bcmns3/lowlevel.S @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Broadcom. + * + */ + +#include <asm/macro.h> +#include <linux/linkage.h> + +hnf_pstate_poll: + /* x0 has the desired status, return 0 for success, 1 for timeout + * clobber x1, x2, x3, x4, x6, x7 + */ + mov x1, x0 + mov x7, #0 /* flag for timeout */ + mrs x3, cntpct_el0 /* read timer */ + mov w0, #600 + mov w6, #1000 + mul w0, w0, w6 + add x3, x3, x0 /* timeout after 100 microseconds */ + mov x0, #0x18 + movk x0, #0x6120, lsl #16 /* HNF0_PSTATE_STATUS */ + mov w6, #4 /* HN-F node count */ +1: + ldr x2, [x0] + cmp x2, x1 /* check status */ + b.eq 2f + mrs x4, cntpct_el0 + cmp x4, x3 + b.ls 1b + mov x7, #1 /* timeout */ + b 3f +2: + add x0, x0, #0x10000 /* move to next node */ + subs w6, w6, #1 + cbnz w6, 1b +3: + mov x0, x7 + ret + +hnf_set_pstate: + /* x0 has the desired state, clobber x1, x2, x6 */ + mov x1, x0 + /* power state to SFONLY */ + mov w6, #4 /* HN-F node count */ + mov x0, #0x10 + movk x0, #0x6120, lsl #16 /* HNF0_PSTATE_REQ */ +1: /* set pstate to sfonly */ + ldr x2, [x0] + and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */ + orr x2, x2, x1 + str x2, [x0] + add x0, x0, #0x10000 /* move to next node */ + subs w6, w6, #1 + cbnz w6, 1b + + ret + +ENTRY(__asm_flush_l3_dcache) + /* + * Return status in x0 + * success 0 + * timeout 1 for setting SFONLY, 2 for FAM, 3 for both + */ + mov x29, lr + mov x8, #0 + + dsb sy + mov x0, #0x1 /* HNFPSTAT_SFONLY */ + bl hnf_set_pstate + + mov x0, #0x4 /* SFONLY status */ + bl hnf_pstate_poll + cbz x0, 1f + mov x8, #1 /* timeout */ +1: + dsb sy + mov x0, #0x3 /* HNFPSTAT_FAM */ + bl hnf_set_pstate + + mov x0, #0xc /* FAM status */ + bl hnf_pstate_poll + cbz x0, 1f + add x8, x8, #0x2 +1: + mov x0, x8 + mov lr, x29 + ret +ENDPROC(__asm_flush_l3_dcache) + +ENTRY(save_boot_params) +/* + * void set_boot_params(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3) + */ + adr x4, bl33_info + str x0, [x4] + b save_boot_params_ret +ENDPROC(save_boot_params) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 2f75b2cdd3..be51b7d856 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -23,6 +23,7 @@ config ARCH_LS1012A config ARCH_LS1028A bool select ARMV8_SET_SMPEN + select FSL_LAYERSCAPE select FSL_LSCH3 select NXP_LSCH3_2 select SYS_FSL_HAS_CCI400 @@ -67,7 +68,6 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009660 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009798 - select SYS_FSL_ERRATUM_A009929 select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 @@ -75,7 +75,7 @@ config ARCH_LS1043A select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F - select SYS_I2C_MXC if !DM_I2C + select SYS_I2C_MXC select SYS_I2C_MXC_I2C1 if !DM_I2C select SYS_I2C_MXC_I2C2 if !DM_I2C select SYS_I2C_MXC_I2C3 if !DM_I2C @@ -108,7 +108,7 @@ config ARCH_LS1046A select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F - select SYS_I2C_MXC if !DM_I2C + select SYS_I2C_MXC select SYS_I2C_MXC_I2C1 if !DM_I2C select SYS_I2C_MXC_I2C2 if !DM_I2C select SYS_I2C_MXC_I2C3 if !DM_I2C @@ -591,9 +591,6 @@ config SYS_FSL_ERRATUM_A009635 config SYS_FSL_ERRATUM_A009660 bool -config SYS_FSL_ERRATUM_A009929 - bool - config SYS_FSL_ERRATUM_A050382 bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index e398aecd12..9ecb372b4e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -6,7 +6,7 @@ obj-y += cpu.o obj-y += lowlevel.o obj-y += soc.o ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_MP) += mp.o +obj-$(CONFIG_MP) += mp.o spintable.o obj-$(CONFIG_OF_LIBFDT) += fdt.o endif obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 67764ee83d..7400b2cf29 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -54,7 +54,6 @@ void ft_fixup_cpu(void *blob) fdt32_t *reg; int addr_cells; u64 val, core_id; - size_t *boot_code_size = &(__secondary_boot_code_size); u32 mask = cpu_pos_mask(); int off_prev = -1; @@ -145,11 +144,11 @@ remove_psci_node: "cpu", 4); } - fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code, - *boot_code_size); + fdt_add_mem_rsv(blob, (uintptr_t)secondary_boot_code_start, + secondary_boot_code_size); #if CONFIG_IS_ENABLED(EFI_LOADER) - efi_add_memory_map((uintptr_t)&secondary_boot_code, *boot_code_size, - EFI_RESERVED_MEMORY_TYPE); + efi_add_memory_map((uintptr_t)secondary_boot_code_start, + secondary_boot_code_size, EFI_RESERVED_MEMORY_TYPE); #endif } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 711ab87556..a519f6ed67 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -11,14 +11,16 @@ #include <asm/gic.h> #include <asm/macro.h> #include <asm/arch-fsl-layerscape/soc.h> -#ifdef CONFIG_MP -#include <asm/arch/mp.h> -#endif #ifdef CONFIG_FSL_LSCH3 #include <asm/arch-fsl-layerscape/immap_lsch3.h> #endif #include <asm/u-boot.h> + .align 3 + .weak secondary_boot_addr +secondary_boot_addr: + .quad 0 + /* Get GIC offset * For LS1043a rev1.0, GIC base address align with 4k. * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT] @@ -208,8 +210,13 @@ ENTRY(lowlevel_init) branch_if_master x0, x1, 2f #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY) - ldr x0, =secondary_boot_func - blr x0 + /* + * Formerly, here was a jump to secondary_boot_func, but we just + * return early here and let the generic code in start.S handle + * the jump to secondary_boot_func. + */ + mov lr, x29 /* Restore LR */ + ret #endif 2: @@ -419,151 +426,3 @@ ENTRY(__asm_flush_l3_dcache) ret ENDPROC(__asm_flush_l3_dcache) #endif /* CONFIG_SYS_FSL_HAS_CCN504 */ - -#ifdef CONFIG_MP - /* Keep literals not used by the secondary boot code outside it */ - .ltorg - - /* Using 64 bit alignment since the spin table is accessed as data */ - .align 4 - .global secondary_boot_code - /* Secondary Boot Code starts here */ -secondary_boot_code: - .global __spin_table -__spin_table: - .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE - - .align 2 -ENTRY(secondary_boot_func) - /* - * MPIDR_EL1 Fields: - * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) - * MPIDR[7:2] = AFF0_RES - * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3) - * MPIDR[23:16] = AFF2_CLUSTERID - * MPIDR[24] = MT - * MPIDR[29:25] = RES0 - * MPIDR[30] = U - * MPIDR[31] = ME - * MPIDR[39:32] = AFF3 - * - * Linear Processor ID (LPID) calculation from MPIDR_EL1: - * (We only use AFF0_CPUID and AFF1_CLUSTERID for now - * until AFF2_CLUSTERID and AFF3 have non-zero values) - * - * LPID = MPIDR[15:8] | MPIDR[1:0] - */ - mrs x0, mpidr_el1 - ubfm x1, x0, #8, #15 - ubfm x2, x0, #0, #1 - orr x10, x2, x1, lsl #2 /* x10 has LPID */ - ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */ - /* - * offset of the spin table element for this core from start of spin - * table (each elem is padded to 64 bytes) - */ - lsl x1, x10, #6 - ldr x0, =__spin_table - /* physical address of this cpus spin table element */ - add x11, x1, x0 - - ldr x0, =__real_cntfrq - ldr x0, [x0] - msr cntfrq_el0, x0 /* set with real frequency */ - str x9, [x11, #16] /* LPID */ - mov x4, #1 - str x4, [x11, #8] /* STATUS */ - dsb sy -#if defined(CONFIG_GICV3) - gic_wait_for_interrupt_m x0 -#elif defined(CONFIG_GICV2) - bl get_gic_offset - mov x0, x1 - gic_wait_for_interrupt_m x0, w1 -#endif - -slave_cpu: - wfe - ldr x0, [x11] - cbz x0, slave_cpu -#ifndef CONFIG_ARMV8_SWITCH_TO_EL1 - mrs x1, sctlr_el2 -#else - mrs x1, sctlr_el1 -#endif - tbz x1, #25, cpu_is_le - rev x0, x0 /* BE to LE conversion */ -cpu_is_le: - ldr x5, [x11, #24] - cbz x5, 1f - -#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x4, secondary_switch_to_el1 - ldr x5, =ES_TO_AARCH64 -#else - ldr x4, [x11] - ldr x5, =ES_TO_AARCH32 -#endif - bl secondary_switch_to_el2 - -1: -#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x4, secondary_switch_to_el1 -#else - ldr x4, [x11] -#endif - ldr x5, =ES_TO_AARCH64 - bl secondary_switch_to_el2 - -ENDPROC(secondary_boot_func) - -ENTRY(secondary_switch_to_el2) - switch_el x6, 1f, 0f, 0f -0: ret -1: armv8_switch_to_el2_m x4, x5, x6 -ENDPROC(secondary_switch_to_el2) - -ENTRY(secondary_switch_to_el1) - mrs x0, mpidr_el1 - ubfm x1, x0, #8, #15 - ubfm x2, x0, #0, #1 - orr x10, x2, x1, lsl #2 /* x10 has LPID */ - - lsl x1, x10, #6 - ldr x0, =__spin_table - /* physical address of this cpus spin table element */ - add x11, x1, x0 - - ldr x4, [x11] - - ldr x5, [x11, #24] - cbz x5, 2f - - ldr x5, =ES_TO_AARCH32 - bl switch_to_el1 - -2: ldr x5, =ES_TO_AARCH64 - -switch_to_el1: - switch_el x6, 0f, 1f, 0f -0: ret -1: armv8_switch_to_el1_m x4, x5, x6 -ENDPROC(secondary_switch_to_el1) - - /* Ensure that the literals used by the secondary boot code are - * assembled within it (this is required so that we can protect - * this area with a single memreserve region - */ - .ltorg - - /* 64 bit alignment for elements accessed as data */ - .align 4 - .global __real_cntfrq -__real_cntfrq: - .quad COUNTER_FREQUENCY - .globl __secondary_boot_code_size - .type __secondary_boot_code_size, %object - /* Secondary Boot Code ends here */ -__secondary_boot_code_size: - .quad .-secondary_boot_code -#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 1ea887b331..bd85351705 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -6,6 +6,7 @@ #include <common.h> #include <cpu_func.h> #include <image.h> +#include <log.h> #include <asm/cache.h> #include <asm/io.h> #include <asm/system.h> @@ -14,17 +15,14 @@ #include <linux/delay.h> #include "cpu.h" #include <asm/arch-fsl-layerscape/soc.h> +#include <efi_loader.h> DECLARE_GLOBAL_DATA_PTR; void *get_spin_tbl_addr(void) { - return &__spin_table; -} - -phys_addr_t determine_mp_bootpg(void) -{ - return (phys_addr_t)&secondary_boot_code; + /* the spin table is at the beginning */ + return secondary_boot_code_start; } void update_os_arch_secondary_cores(uint8_t os_arch) @@ -43,7 +41,7 @@ void update_os_arch_secondary_cores(uint8_t os_arch) } #ifdef CONFIG_FSL_LSCH3 -void wake_secondary_core_n(int cluster, int core, int cluster_cores) +static void wake_secondary_core_n(int cluster, int core, int cluster_cores) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); @@ -80,7 +78,11 @@ int fsl_layerscape_wake_seconday_cores(void) #endif u32 cores, cpu_up_mask = 1; int i, timeout = 10; - u64 *table = get_spin_tbl_addr(); + u64 *table; +#ifdef CONFIG_EFI_LOADER + u64 reloc_addr = U32_MAX; + efi_status_t ret; +#endif #ifdef COUNTER_FREQUENCY_REAL /* update for secondary cores */ @@ -89,16 +91,49 @@ int fsl_layerscape_wake_seconday_cores(void) (unsigned long)&__real_cntfrq + 8); #endif +#ifdef CONFIG_EFI_LOADER + /* + * EFI will reserve 64kb for its runtime services. This will probably + * overlap with our spin table code, which is why we have to relocate + * it. + * Keep this after the __real_cntfrq update, so we have it when we + * copy the complete section here. + */ + ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, + EFI_RESERVED_MEMORY_TYPE, + efi_size_in_pages(secondary_boot_code_size), + &reloc_addr); + if (ret == EFI_SUCCESS) { + debug("Relocating spin table from %llx to %llx (size %lx)\n", + (u64)secondary_boot_code_start, reloc_addr, + secondary_boot_code_size); + memcpy((void *)reloc_addr, secondary_boot_code_start, + secondary_boot_code_size); + flush_dcache_range(reloc_addr, + reloc_addr + secondary_boot_code_size); + + /* set new entry point for secondary cores */ + secondary_boot_addr += (void *)reloc_addr - + secondary_boot_code_start; + flush_dcache_range((unsigned long)&secondary_boot_addr, + (unsigned long)&secondary_boot_addr + 8); + + /* this will be used to reserve the memory */ + secondary_boot_code_start = (void *)reloc_addr; + } +#endif + cores = cpu_mask(); /* Clear spin table so that secondary processors * observe the correct value after waking up from wfe. */ + table = get_spin_tbl_addr(); memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); flush_dcache_range((unsigned long)table, (unsigned long)table + (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); - printf("Waking secondary cores to start from %lx\n", gd->relocaddr); + debug("Waking secondary cores to start from %lx\n", gd->relocaddr); #ifdef CONFIG_FSL_LSCH3 gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); @@ -168,11 +203,11 @@ int fsl_layerscape_wake_seconday_cores(void) udelay(10); } if (timeout <= 0) { - printf("Not all cores (0x%x) are up (0x%x)\n", - cores, cpu_up_mask); + printf("CPU: Failed to bring up some cores (mask 0x%x)\n", + cores ^ cpu_up_mask); return 1; } - printf("All (%d) cores are up.\n", hweight32(cores)); + printf("CPU: %d cores online\n", hweight32(cores)); return 0; } @@ -189,9 +224,9 @@ static int is_pos_valid(unsigned int pos) int is_core_online(u64 cpu_id) { - u64 *table; + u64 *table = get_spin_tbl_addr(); int pos = id_to_core(cpu_id); - table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY; + table += pos * WORDS_PER_SPIN_TABLE_ENTRY; return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1; } @@ -237,18 +272,16 @@ static int core_to_pos(int nr) int cpu_status(u32 nr) { - u64 *table; + u64 *table = get_spin_tbl_addr(); int pos; if (nr == 0) { - table = (u64 *)get_spin_tbl_addr(); printf("table base @ 0x%p\n", table); } else { pos = core_to_pos(nr); if (pos < 0) return -1; - table = (u64 *)get_spin_tbl_addr() + pos * - WORDS_PER_SPIN_TABLE_ENTRY; + table += pos * WORDS_PER_SPIN_TABLE_ENTRY; printf("table @ 0x%p\n", table); printf(" addr - 0x%016llx\n", table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]); @@ -264,7 +297,7 @@ int cpu_status(u32 nr) int cpu_release(u32 nr, int argc, char *const argv[]) { u64 boot_addr; - u64 *table = (u64 *)get_spin_tbl_addr(); + u64 *table = get_spin_tbl_addr(); int pos; pos = core_to_pos(nr); @@ -277,11 +310,12 @@ int cpu_release(u32 nr, int argc, char *const argv[]) flush_dcache_range((unsigned long)table, (unsigned long)table + SPIN_TABLE_ELEM_SIZE); asm volatile("dsb st"); - smp_kick_all_cpus(); /* only those with entry addr set will run */ + /* - * When the first release command runs, all cores are set to go. Those - * without a valid entry address will be trapped by "wfe". "sev" kicks - * them off to check the address again. When set, they continue to run. + * The secondary CPUs polling the spin-table above for a non-zero + * value. To save power "wfe" is called. Thus call "sev" here to + * wake the CPUs and let them check the spin-table again (see + * slave_cpu loop in lowlevel.S) */ asm volatile("sev"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index ad7ea05935..fde893e8c9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -41,37 +41,11 @@ DECLARE_GLOBAL_DATA_PTR; #endif #ifdef CONFIG_GIC_V3_ITS -#define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K) -#define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K) -#define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \ - PROPTABLE_MAX_SZ, SZ_1M) -static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size) -{ - u32 phandle; - int err; - struct fdt_memory gic_rd_tables; - - gic_rd_tables.start = base; - gic_rd_tables.end = base + size - 1; - err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables, - &phandle); - if (err < 0) - debug("%s: failed to add reserved memory: %d\n", __func__, err); - - return err; -} - int ls_gic_rd_tables_init(void *blob) { - u64 gic_lpi_base; int ret; - gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K); - ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE); - if (ret) - return ret; - - ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores()); + ret = gic_lpi_tables_init(); if (ret) debug("%s: failed to init gic-lpi-tables\n", __func__); @@ -445,20 +419,6 @@ int get_core_volt_from_fuse(void) } #elif defined(CONFIG_FSL_LSCH2) - -static void erratum_a009929(void) -{ -#ifdef CONFIG_SYS_FSL_ERRATUM_A009929 - struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; - u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; - u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); - - rstrqmr1 |= 0x00000400; - gur_out32(&gur->rstrqmr1, rstrqmr1); - writel(0x01000000, dcsr_cop_ccp); -#endif -} - /* * This erratum requires setting a value to eddrtqcr1 to optimal * the DDR performance. The eddrtqcr1 register is in SCFG space @@ -724,7 +684,6 @@ void fsl_lsch2_early_init_f(void) #endif /* Erratum */ erratum_a008850_early(); /* part 1 of 2 */ - erratum_a009929(); erratum_a009660(); erratum_a010539(); erratum_a009008(); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S new file mode 100644 index 0000000000..363ded03e6 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2014-2015 Freescale Semiconductor + * Copyright 2019 NXP + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> +#include <asm/system.h> +#include <asm/arch/mp.h> + +.align 3 +.global secondary_boot_addr +secondary_boot_addr: + .quad __secondary_boot_func + +.global secondary_boot_code_start +secondary_boot_code_start: + .quad __secondary_boot_code_start + +.global secondary_boot_code_size +secondary_boot_code_size: + .quad __secondary_boot_code_end - __secondary_boot_code_start + + /* Using 64 bit alignment since the spin table is accessed as data */ + .align 3 + /* Secondary Boot Code starts here */ +__secondary_boot_code_start: +__spin_table: + .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE + + .align 2 +__secondary_boot_func: + /* + * MPIDR_EL1 Fields: + * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) + * MPIDR[7:2] = AFF0_RES + * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3) + * MPIDR[23:16] = AFF2_CLUSTERID + * MPIDR[24] = MT + * MPIDR[29:25] = RES0 + * MPIDR[30] = U + * MPIDR[31] = ME + * MPIDR[39:32] = AFF3 + * + * Linear Processor ID (LPID) calculation from MPIDR_EL1: + * (We only use AFF0_CPUID and AFF1_CLUSTERID for now + * until AFF2_CLUSTERID and AFF3 have non-zero values) + * + * LPID = MPIDR[15:8] | MPIDR[1:0] + */ + mrs x0, mpidr_el1 + ubfm x1, x0, #8, #15 + ubfm x2, x0, #0, #1 + orr x10, x2, x1, lsl #2 /* x10 has LPID */ + ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */ + /* + * offset of the spin table element for this core from start of spin + * table (each elem is padded to 64 bytes) + */ + lsl x1, x10, #6 + adr x0, __spin_table + /* physical address of this cpus spin table element */ + add x11, x1, x0 + + adr x0, __real_cntfrq + ldr x0, [x0] + msr cntfrq_el0, x0 /* set with real frequency */ + str x9, [x11, #16] /* LPID */ + mov x4, #1 + str x4, [x11, #8] /* STATUS */ + dsb sy + +1: + wfe + ldr x4, [x11] + cbz x4, 1b + mrs x1, sctlr_el2 + tbz x1, #25, 2f + rev x4, x4 /* BE to LE conversion */ +2: + ldr x6, =ES_TO_AARCH64 +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + adr x5, 3f + switch_el x7, 0f, _dead_loop, _dead_loop +0: armv8_switch_to_el2_m x5, x6, x7 +#endif +3: + ldr x7, [x11, #24] /* ARCH_COMP */ + cbz x7, 4f + ldr x6, =ES_TO_AARCH32 +4: +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + switch_el x7, _dead_loop, 0f, _dead_loop +0: armv8_switch_to_el1_m x4, x6, x7 +#else + switch_el x7, 0f, _dead_loop, _dead_loop +0: armv8_switch_to_el2_m x4, x6, x7 +#endif + +_dead_loop: + wfe + b _dead_loop + + /* Ensure that the literals used by the secondary boot code are + * assembled within it (this is required so that we can protect + * this area with a single memreserve region + */ + .ltorg + + /* 64 bit alignment for elements accessed as data */ + .align 3 + .global __real_cntfrq +__real_cntfrq: + .quad COUNTER_FREQUENCY + /* Secondary Boot Code ends here */ +__secondary_boot_code_end: diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 93a848eac5..43a2ee1213 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -147,6 +147,9 @@ dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb +dtb-$(CONFIG_ARCH_S5P4418) += \ + s5p4418-nanopi2.dtb + dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ meson-gxbb-odroidc2.dtb \ @@ -775,6 +778,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \ r8a7794-silk-u-boot.dtb dtb-$(CONFIG_RCAR_GEN3) += \ + r8a774a1-beacon-rzg2m-kit.dtb \ r8a77950-ulcb-u-boot.dtb \ r8a77950-salvator-x-u-boot.dtb \ r8a77960-ulcb-u-boot.dtb \ @@ -927,6 +931,8 @@ dtb-$(CONFIG_ARCH_BCM68360) += \ dtb-$(CONFIG_ARCH_BCM6858) += \ bcm968580xref.dtb +dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb + dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb @@ -937,6 +943,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \ + stm32mp157c-odyssey.dtb \ + stm32mp15xx-dhcom-drc02.dtb \ stm32mp15xx-dhcom-pdk2.dtb \ stm32mp15xx-dhcor-avenger96.dtb @@ -946,6 +954,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ + mt7623a-unielec-u7623-02-emmc.dtb \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ mt8512-bm1-emmc.dtb \ diff --git a/arch/arm/dts/beacon-renesom-baseboard.dtsi b/arch/arm/dts/beacon-renesom-baseboard.dtsi new file mode 100644 index 0000000000..8a472c057a --- /dev/null +++ b/arch/arm/dts/beacon-renesom-baseboard.dtsi @@ -0,0 +1,597 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020, Compass Electronics Group, LLC + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + aliases { + serial0 = &scif2; + serial1 = &hscif0; + serial2 = &hscif1; + serial3 = &scif0; + serial4 = &hscif2; + serial5 = &scif5; + spi0 = &msiof0; + spi1 = &msiof1; + spi2 = &msiof2; + spi3 = &msiof3; + ethernet0 = &avb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <®_lcd>; + enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>; + pwms = <&pwm0 0 50000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + hdmi0-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con: endpoint { + remote-endpoint = <&rcar_dw_hdmi0_out>; + }; + }; + }; + + keys { + compatible = "gpio-keys"; + + key-1 { + gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_1>; + label = "Switch-1"; + wakeup-source; + debounce-interval = <20>; + }; + key-2 { + gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; + linux,code = <KEY_2>; + label = "Switch-2"; + wakeup-source; + debounce-interval = <20>; + }; + key-3 { + gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + linux,code = <KEY_3>; + label = "Switch-3"; + wakeup-source; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + linux,code = <KEY_4>; + label = "Switch-4"; + wakeup-source; + debounce-interval = <20>; + }; + key-5 { + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + linux,code = <KEY_5>; + label = "Switch-4"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led0 { + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + label = "LED0"; + linux,default-trigger = "heartbeat"; + }; + led1 { + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + label = "LED1"; + linux,default-trigger = "heartbeat"; + }; + led2 { + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + label = "LED2"; + linux,default-trigger = "heartbeat"; + }; + led3 { + gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; + label = "LED3"; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_audio: regulator_audio { + compatible = "regulator-fixed"; + regulator-name = "audio-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio_exp2 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "lcd_panel_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_exp1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd_reset: regulator-lcd-reset { + compatible = "regulator-fixed"; + regulator-name = "nLCD_RESET"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_lcd>; + }; + + reg_cam0: regulator_camera { + compatible = "regulator-fixed"; + regulator-name = "reg_cam0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio_exp2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_cam1: regulator_camera { + compatible = "regulator-fixed"; + regulator-name = "reg_cam1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio_exp2 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; + }; + + sound_card { + compatible = "audio-graph-card"; + label = "rcar-sound"; + dais = <&rsnd_port0>, <&rsnd_port1>; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + regulator-always-on; + }; + + /* External DU dot clocks */ + x302_clk: x302-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33000000>; + }; + + x304_clk: x304-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&audio_clk_b { + clock-frequency = <22579200>; +}; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + renesas,can-clock-select = <0x0>; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + renesas,can-clock-select = <0x0>; + status = "okay"; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", + "dclkin.0", "dclkin.1", "dclkin.2"; +}; + +&ehci0 { + dr_mode = "otg"; + status = "okay"; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>, <&versaclock6_bb 4>; +}; + +&ehci1 { + status = "okay"; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 4>; +}; + +&hdmi0 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; + }; + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + port@2 { + /* HDMI sound */ + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint1>; + }; + }; + }; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + gpio_exp2: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_exp3: gpio@22 { + compatible = "onnn,pca9654"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + versaclock6_bb: versaclock6_bb@6a { + compatible = "idt,5p49v6965"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x304_clk>; + clock-names = "xin"; + /* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */ + assigned-clocks = <&versaclock6_bb 1>, + <&versaclock6_bb 2>, + <&versaclock6_bb 3>, + <&versaclock6_bb 4>; + assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24000000>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:Default */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:Default */ + 0x0000 /* 5:Default */ + >; + port { + wm8962_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint0>; + }; + }; + }; + + /* 0 - lcd_reset */ + /* 1 - lcd_pwr */ + /* 2 - lcd_select */ + /* 3 - backlight-enable */ + /* 4 - Touch_shdwn */ + /* 5 - LCD_H_pol */ + /* 6 - lcd_V_pol */ + gpio_exp1: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + touchscreen@26 { + compatible = "ilitek,ili2117"; + reg = <0x26>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + wakeup-source; + }; +}; + +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pciec0 { + status = "okay"; +}; + +&pciec1 { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pfc { + can0_pins: can0 { + groups = "can0_data_a"; + function = "can0"; + }; + + can1_pins: can1 { + groups = "can1_data"; + function = "can1"; + }; + + du_pins: du { + groups = "du_rgb888", "du_sync", "du_clk_out_1", "du_disp"; + function = "du"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + i2c5_pins: i2c5 { + groups = "i2c5"; + function = "i2c5"; + }; + + led_pins: leds { + /* GP_0_4 , AVS1, AVS2, GP_7_3 */ + pins = "GP_0_4", "GP_7_0", "GP_7_1", "GP_7_3"; + bias-pull-down; + }; + + msiof1_pins: msiof1 { + groups = "msiof1_clk_g", "msiof1_rxd_g", "msiof1_txd_g"; + function = "msiof1"; + }; + + pwm0_pins: pwm0 { + groups = "pwm0"; + function = "pwm0"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a_a"; + function = "audio_clk"; + }; + + usb0_pins: usb0 { + mux { + groups = "usb0"; + function = "usb0"; + }; + }; + + usb1_pins: usb1 { + mux { + groups = "usb1"; + function = "usb1"; + }; + }; + + usb30_pins: usb30 { + mux { + groups = "usb30"; + function = "usb30"; + }; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <11289600>; + + status = "okay"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A774A1_CLK_S0D4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + rsnd_port0: port@0 { + reg = <0>; + rsnd_endpoint0: endpoint { + remote-endpoint = <&wm8962_endpoint>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint0>; + frame-master = <&rsnd_endpoint0>; + + playback = <&ssi1 &dvc1 &src1>; + capture = <&ssi0>; + }; + }; + rsnd_port1: port@1 { + reg = <0x01>; + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint1>; + frame-master = <&rsnd_endpoint1>; + + playback = <&ssi2>; + }; + }; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scif5 { + pinctrl-0 = <&scif5_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/dts/beacon-renesom-som.dtsi b/arch/arm/dts/beacon-renesom-som.dtsi new file mode 100644 index 0000000000..6c16a2732a --- /dev/null +++ b/arch/arm/dts/beacon-renesom-som.dtsi @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020, Compass Electronics Group, LLC + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; + + osc_32k: osc_32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + wlan_pwrseq: wlan_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>; + clocks = <&osc_32k>; + clock-names = "ext_clock"; + post-power-on-delay-ms = <80>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&gpio6 { + usb_hub_reset { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + max-speed = <4000000>; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>; + clocks = <&osc_32k>; + clock-names = "extclk"; + }; +}; + +&hscif2 { + status = "okay"; + pinctrl-0 = <&hscif2_pins>; + pinctrl-names = "default"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + pca9654: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "i2c4_20_0", + "wl_reg_on", + "bt_reg_on", + "i2c4_20_3", + "i2c4_20_4", + "bt_dev_wake", + "i2c4_20_6", + "i2c4_20_7"; + }; + + pca9654_lte: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + interrupt-parent = <&gpio5>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "i2c4_21_0", + "zoe_pwr_on", + "zoe_extint", + "zoe_reset_n", + "sara_reset", + "i2c4_21_5", + "sara_pwr_off", + "sara_networking_status"; + }; + + eeprom@50 { + compatible = "microchip, at24c64", "atmel,24c64"; + pagesize = <32>; + read-only; /* Manufacturing EEPROM programmed at factory */ + reg = <0x50>; + }; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; + + versaclock5: versaclock_som@6a { + compatible = "idt,5p49v6965"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x304_clk>; + clock-names = "xin"; + /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */ + assigned-clocks = <&versaclock5 1>, + <&versaclock5 2>, + <&versaclock5 3>, + <&versaclock5 4>; + assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>; + }; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_mdio", "avb_mii"; + function = "avb"; + }; + + pins_mdio { + groups = "avb_mdio"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", + "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + + hscif2_pins: hscif2 { + groups = "hscif2_data_a"; + function = "hscif2"; + }; + + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif5_pins: scif5 { + groups = "scif5_data_a"; + function = "scif5"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; + function = "sdhi3"; + power-source = <1800>; + }; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhi2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhi2_pins>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + cap-power-off-card; + pm-ignore-notify; + keep-power-in-suspend; + mmc-pwrseq = <&wlan_pwrseq>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio1>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&sdhi3 { + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; + +&usb_extal_clk { + clock-frequency = <50000000>; +}; + +&usb3s0_clk { + clock-frequency = <100000000>; +}; + +&vspb { + status = "okay"; +}; + +&vspi0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index 4f56f40bd3..6cdcce1b92 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -15,20 +15,94 @@ compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; aliases { spi0 = &fspi; + spi1 = &dspi0; + spi2 = &dspi1; + spi3 = &dspi2; }; }; &dspi0 { + bus-num = <0>; status = "okay"; + + dflash0: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + + dflash1: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; }; &dspi1 { + bus-num = <0>; status = "okay"; + + dflash3: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + + dflash4: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash5: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; }; &dspi2 { + bus-num = <0>; status = "okay"; + + dflash8: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; }; &esdhc0 { diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 8673a5db2a..3f11d6cd18 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -257,6 +257,17 @@ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + pcie_ep@3400000 { + compatible = "fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x80000 + 0x00 0x034c0000 0x0 0x40000 + 0x40 0x00000000 0x8 0x00000000>; + reg-names = "regs", "ctrl", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <8>; + big-endian; + }; + pcie@3500000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ @@ -274,6 +285,17 @@ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + pcie_ep@3500000 { + compatible = "fsl,ls-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x80000 + 0x00 0x035c0000 0x0 0x40000 + 0x48 0x00000000 0x8 0x00000000>; + reg-names = "regs", "ctrl", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <8>; + big-endian; + }; + pcie@3600000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ @@ -290,6 +312,17 @@ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + pcie_ep@3600000 { + compatible = "fsl,ls-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x80000 + 0x00 0x036c0000 0x0 0x40000 + 0x50 0x00000000 0x8 0x00000000>; + reg-names = "regs", "ctrl", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <8>; + big-endian; + }; + sata: sata@3200000 { compatible = "fsl,ls1046a-ahci"; reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi index 129cf82a8f..96c980004b 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dtsi +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -20,6 +20,105 @@ phy-connection-type = "rgmii-id"; }; +&dspi0 { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + + dflash3: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash4: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash5: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&dspi2 { + bus-num = <0>; + status = "okay"; + + dflash6: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash7: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash8: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + &emdio1 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 1789da8638..dee1e2f215 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -204,6 +204,13 @@ #interrupt-cells = <2>; }; + watchdog@23a0000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x23a0000 0 0x1000>, + <0x0 0x2390000 0 0x1000>; + timeout-sec = <30>; + }; + usb0: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; @@ -284,7 +291,7 @@ reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */ 0x00 0x03480000 0x0 0x40000 /* LUT registers */ 0x00 0x034c0000 0x0 0x40000 /* PF control registers */ - 0x80 0x00000000 0x0 0x1000>; /* configuration space */ + 0x80 0x00000000 0x0 0x2000>; /* configuration space */ reg-names = "ccsr", "lut", "pf_ctrl", "config"; #address-cells = <3>; #size-cells = <2>; @@ -298,7 +305,7 @@ reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */ 0x00 0x03580000 0x0 0x40000 /* LUT registers */ 0x00 0x035c0000 0x0 0x40000 /* PF control registers */ - 0x88 0x00000000 0x0 0x1000>; /* configuration space */ + 0x88 0x00000000 0x0 0x2000>; /* configuration space */ reg-names = "ccsr", "lut", "pf_ctrl", "config"; #address-cells = <3>; #size-cells = <2>; @@ -313,7 +320,7 @@ reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */ 0x00 0x03680000 0x0 0x40000 /* LUT registers */ 0x00 0x036c0000 0x0 0x40000 /* PF control registers */ - 0x90 0x00000000 0x0 0x1000>; /* configuration space */ + 0x90 0x00000000 0x0 0x2000>; /* configuration space */ reg-names = "ccsr", "lut", "pf_ctrl", "config"; #address-cells = <3>; #size-cells = <2>; @@ -327,7 +334,7 @@ reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */ 0x00 0x03780000 0x0 0x40000 /* LUT registers */ 0x00 0x037c0000 0x0 0x40000 /* PF control registers */ - 0x98 0x00000000 0x0 0x1000>; /* configuration space */ + 0x98 0x00000000 0x0 0x2000>; /* configuration space */ reg-names = "ccsr", "lut", "pf_ctrl", "config"; #address-cells = <3>; #size-cells = <2>; @@ -341,7 +348,7 @@ reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */ 0x00 0x03880000 0x0 0x40000 /* LUT registers */ 0x00 0x038c0000 0x0 0x40000 /* PF control registers */ - 0xa0 0x00000000 0x0 0x1000>; /* configuration space */ + 0xa0 0x00000000 0x0 0x2000>; /* configuration space */ reg-names = "ccsr", "lut", "pf_ctrl", "config"; #address-cells = <3>; #size-cells = <2>; @@ -355,7 +362,7 @@ reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */ 0x00 0x03980000 0x0 0x40000 /* LUT registers */ 0x00 0x039c0000 0x0 0x40000 /* PF control registers */ - 0xa8 0x00000000 0x0 0x1000>; /* configuration space */ + 0xa8 0x00000000 0x0 0x2000>; /* configuration space */ reg-names = "ccsr", "lut", "pf_ctrl", "config"; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/dts/k3-am65-wakeup.dtsi b/arch/arm/dts/k3-am65-wakeup.dtsi index 2676d6035b..666c30d019 100644 --- a/arch/arm/dts/k3-am65-wakeup.dtsi +++ b/arch/arm/dts/k3-am65-wakeup.dtsi @@ -62,4 +62,9 @@ clocks = <&k3_clks 115 1>; power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; }; + + chipid: chipid@43000014 { + compatible = "ti,am654-chipid"; + reg = <0x43000014 0x4>; + }; }; diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index d9ff3ed47b..a30680d3e0 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -246,3 +246,7 @@ u-boot,dm-spl; }; }; + +&chipid { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 6e748bfebb..cfb39325e9 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -211,3 +211,7 @@ &mcu_fss0_ospi1_pins_default { u-boot,dm-spl; }; + +&chipid { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index e6c99ab698..60695f5eb9 100644 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -316,4 +316,9 @@ ti,cpts-periodic-outputs = <2>; }; }; + + chipid: chipid@43000014 { + compatible = "ti,am654-chipid"; + reg = <0x0 0x43000014 0x0 0x4>; + }; }; diff --git a/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts b/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts new file mode 100644 index 0000000000..fdeec75b05 --- /dev/null +++ b/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include "mt7623.dtsi" +#include "mt7623-u-boot.dtsi" + +/ { + model = "UniElec U7623-02 eMMC"; + compatible = "unielec,u7623-02-emmc", "mediatek,mt7623"; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x20000000>; + }; + + chosen { + stdout-path = &uart2; + tick-timer = &timer0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + led3 { + label = "u7623-01:green:led3"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led4 { + label = "u7623-01:green:led4"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +ð { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "rgmii"; + mediatek,switch = "mt7530"; + mediatek,mcm; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; +}; + +&pinctrl { + ephy_default: ephy_default { + mux { + function = "eth"; + groups = "mdc_mdio", "ephy"; + }; + + conf { + pins = "G2_TXEN", "G2_TXD0", "G2_TXD1", "G2_TXD2", + "G2_TXD3", "G2_TXC", "G2_RXC", "G2_RXD0", + "G2_RXD1", "G2_RXD2", "G2_RXD3", "G2_RXDV", + "MDC", "MDIO"; + drive-strength = <12>; + mediatek,tdsel = <5>; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "msdc"; + groups = "msdc0"; + }; + + conf-cmd-data { + pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1", + "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4", + "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "MSDC0_CLK"; + bias-pull-down; + }; + + conf-rst { + pins = "MSDC0_RSTB"; + bias-pull-up; + }; + }; + + pcie_default: pcie-default { + mux { + function = "pcie"; + groups = "pcie0_0_perst", "pcie1_0_perst"; + }; + }; + + uart0_pins_a: uart0-default { + mux { + function = "uart"; + groups = "uart0_0_txd_rxd"; + }; + }; + + uart1_pins_a: uart1-default { + mux { + function = "uart"; + groups = "uart1_0_txd_rxd"; + }; + }; + + uart2_pins_a: uart2-default { + mux { + function = "uart"; + groups = "uart2_0_txd_rxd"; + }; + }; + + uart2_pins_b: uart2-alt { + mux { + function = "uart"; + groups = "uart2_1_txd_rxd"; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; + + pcie@1,0 { + status = "okay"; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_b>; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts index bf84f76344..5cc7294de6 100644 --- a/arch/arm/dts/mt7629-rfb.dts +++ b/arch/arm/dts/mt7629-rfb.dts @@ -24,12 +24,14 @@ ð { status = "okay"; - mediatek,gmac-id = <1>; - phy-mode = "gmii"; - phy-handle = <&phy0>; - - phy0: ethernet-phy@0 { - reg = <0>; + mediatek,gmac-id = <0>; + phy-mode = "sgmii"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <1000>; + full-duplex; }; }; diff --git a/arch/arm/dts/ns3-board.dts b/arch/arm/dts/ns3-board.dts new file mode 100644 index 0000000000..4e0966a132 --- /dev/null +++ b/arch/arm/dts/ns3-board.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Broadcom + */ + +/dts-v1/; + +#include <dt-bindings/memory/bcm-ns3-mc.h> + +/* + * Single mem reserve region which includes the following: + * Components name Start Addr Size + * ------------------------------------------------ + * GIC LPI tables 0x8ad7_0000 0x0009_0000 + * Nitro FW 0x8ae0_0000 0x0020_0000 + * Nitro Crash dump 0x8b00_0000 0x0200_0000 + * OPTEE OS 0x8d00_0000 0x0200_0000 + * BL31 services 0x8f00_0000 0x0010_0000 + * Tmon 0x8f10_0000 0x0000_1000 + * LPM/reserved 0x8f10_1000 0x0000_1000 + * ATF to Bl33 info 0x8f10_2000 0x0000_1000 + * ATF error logs 0x8f10_3000 0x0001_0000 + * Error log parser 0x8f11_3000 0x0010_0000 + */ + +/memreserve/ BCM_NS3_MEM_RSVE_START BCM_NS3_MEM_RSVE_END; + +/* CRMU page tables */ +/memreserve/ BCM_NS3_CRMU_PGT_START BCM_NS3_CRMU_PGT_SIZE; + +#include "ns3.dtsi" + +/ { + model = "NS3 model"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/ns3.dtsi b/arch/arm/dts/ns3.dtsi new file mode 100644 index 0000000000..09098aac3a --- /dev/null +++ b/arch/arm/dts/ns3.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Broadcom + */ + +#include "skeleton64.dtsi" + +/ { + compatible = "brcm,ns3"; + #address-cells = <2>; + #size-cells = <2>; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>, + <0x8 0x80000000 0x1 0x80000000>; + }; + + hsls { + compatible = "simple-bus"; + dma-ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x68900000 0x17700000>; + + uart1: uart@110000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00110000 0x1000>; + reg-shift = <2>; + clock-frequency = <25000000>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi new file mode 100644 index 0000000000..5f78bc5ab9 --- /dev/null +++ b/arch/arm/dts/qcom-ipq4019.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Sartura Ltd. + * + * Author: Robert Marko <robert.marko@sartura.hr> + */ + + /dts-v1/; + +#include "skeleton.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/pinctrl-snapdragon.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + model = "Qualcomm Technologies, Inc. IPQ4019"; + compatible = "qcom,ipq4019"; + + aliases { + serial0 = &blsp1_uart1; + }; + + reserved-memory { + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; + + smem_mem: smem_region: smem@87e00000 { + reg = <0x87e00000 0x080000>; + no-map; + }; + + tz@87e80000 { + reg = <0x87e80000 0x180000>; + no-map; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-ipq4019"; + reg = <0x1800000 0x60000>; + #clock-cells = <1>; + #reset-cells = <1>; + u-boot,dm-pre-reloc; + }; + + pinctrl: qcom,tlmm@1000000 { + compatible = "qcom,tlmm-ipq4019"; + reg = <0x1000000 0x300000>; + u-boot,dm-pre-reloc; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; + clock = <&gcc 26>; + bit-rate = <0xFF>; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + soc_gpios: pinctrl@1000000 { + compatible = "qcom,ipq4019-pinctrl"; + reg = <0x1000000 0x300000>; + gpio-controller; + gpio-count = <100>; + gpio-bank-name="soc"; + #gpio-cells = <2>; + }; + }; +}; diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi new file mode 100644 index 0000000000..a0c0a7f35c --- /dev/null +++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/ { + soc { + u-boot,dm-pre-reloc; + }; +}; + +&cpg { + u-boot,dm-pre-reloc; +}; + +&extal_clk { + u-boot,dm-pre-reloc; +}; + +&prr { + u-boot,dm-pre-reloc; +}; + +&extalr_clk { + u-boot,dm-pre-reloc; +}; + +&sdhi0 { + /delete-property/ cd-gpios; +}; + +&sdhi2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts new file mode 100644 index 0000000000..e7ed5d4806 --- /dev/null +++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020, Compass Electronics Group, LLC + */ + +/dts-v1/; + +#include "r8a774a1.dtsi" +#include "beacon-renesom-som.dtsi" +#include "beacon-renesom-baseboard.dtsi" + +/ { + model = "Beacon Embedded Works RZ/G2M Development Kit"; + compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1"; +}; diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi new file mode 100644 index 0000000000..a603d94797 --- /dev/null +++ b/arch/arm/dts/r8a774a1.dtsi @@ -0,0 +1,2787 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a774a1 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> +#include <dt-bindings/power/r8a774a1-sysc.h> + +/ { + compatible = "renesas,r8a774a1"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c_dvfs; + }; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&a57_0>; + }; + core1 { + cpu = <&a57_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&a53_0>; + }; + core1 { + cpu = <&a53_1>; + }; + core2 { + cpu = <&a53_2>; + }; + core3 { + cpu = <&a53_3>; + }; + }; + }; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + dynamic-power-coefficient = <854>; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a53_0: cpu@100 { + compatible = "arm,cortex-a53"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + #cooling-cells = <2>; + dynamic-power-coefficient = <277>; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A774A1_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A774A1_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, <&a57_1>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a774a1-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a774a1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a774a1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a774a1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a774a1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a774a1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a774a1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a774a1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a774a1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a774a1"; + reg = <0 0xe6060000 0 0x50c>; + }; + + cmt0: timer@e60f0000 { + compatible = "renesas,r8a774a1-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a774a1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a774a1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a774a1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a774a1-cpg-mssr"; + reg = <0 0xe6150000 0 0x0bb0>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a774a1-rst"; + reg = <0 0xe6160000 0 0x018c>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a774a1-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a774a1-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774a1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774a1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774a1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774a1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774a1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774a1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774a1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a774a1", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a774a1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a774a1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a774a1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a774a1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a774a1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a774a1", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x200>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a774a1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a774a1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a774a1-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a774a1", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a774a1", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a774a1", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; + }; + + ipmmu_ds0: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a774a1"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: iommu@e7740000 { + compatible = "renesas,ipmmu-r8a774a1"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@e6570000 { + compatible = "renesas,ipmmu-r8a774a1"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@e67b0000 { + compatible = "renesas,ipmmu-r8a774a1"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp: iommu@ec670000 { + compatible = "renesas,ipmmu-r8a774a1"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: iommu@fd800000 { + compatible = "renesas,ipmmu-r8a774a1"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 5>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv1: iommu@fd950000 { + compatible = "renesas,ipmmu-r8a774a1"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: iommu@fe6b0000 { + compatible = "renesas,ipmmu-r8a774a1"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 8>; + power-domains = <&sysc R8A774A1_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: iommu@febd0000 { + compatible = "renesas,ipmmu-r8a774a1"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a774a1", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a774a1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A774A1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a774a1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A774A1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a774a1-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A774A1_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a774a1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a774a1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a774a1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 0x40>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a774a1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a774a1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a774a1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 0x40>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a774a1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a774a1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a774a1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a774a1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin4>; + }; + vin4csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin5>; + }; + vin5csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin6>; + }; + vin6csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin7>; + }; + vin7csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin7>; + }; + }; + }; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774A1_CLK_S0D4>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + status = "disabled"; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a774a1", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, + <&ipmmu_mp 2>, <&ipmmu_mp 3>, + <&ipmmu_mp 4>, <&ipmmu_mp 5>, + <&ipmmu_mp 6>, <&ipmmu_mp 7>, + <&ipmmu_mp 8>, <&ipmmu_mp 9>, + <&ipmmu_mp 10>, <&ipmmu_mp 11>, + <&ipmmu_mp 12>, <&ipmmu_mp 13>, + <&ipmmu_mp 14>, <&ipmmu_mp 15>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a774a1", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, + <&ipmmu_mp 18>, <&ipmmu_mp 19>, + <&ipmmu_mp 20>, <&ipmmu_mp 21>, + <&ipmmu_mp 22>, <&ipmmu_mp 23>, + <&ipmmu_mp 24>, <&ipmmu_mp 25>, + <&ipmmu_mp 26>, <&ipmmu_mp 27>, + <&ipmmu_mp 28>, <&ipmmu_mp 29>, + <&ipmmu_mp 30>, <&ipmmu_mp 31>; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a774a1", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a774a1-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; + }; + + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a774a1", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + #phy-cells = <1>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a774a1", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <1>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a774a1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a774a1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a774a1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a774a1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a774a1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a774a1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, + <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, + <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A774A1_PD_A3VC>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A774A1_PD_A3VC>; + resets = <&cpg 615>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A774A1_PD_A3VC>; + resets = <&cpg 607>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 601>; + iommus = <&ipmmu_vi0 10>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A774A1_PD_A3VC>; + resets = <&cpg 611>; + iommus = <&ipmmu_vc0 19>; + }; + + vspb: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A774A1_PD_A3VC>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + vspd2: vsp@fea30000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea30000 0 0x5000>; + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 621>; + + renesas,fcp = <&fcpvd2>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A774A1_PD_A3VC>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + csi20: csi2@fea80000 { + compatible = "renesas,r8a774a1-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a774a1-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + csi40vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi40>; + }; + csi40vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi40>; + }; + csi40vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi40>; + }; + csi40vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi40>; + }; + }; + + }; + }; + + hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a774a1-hdmi", + "renesas,rcar-gen3-hdmi"; + reg = <0 0xfead0000 0 0x10000>; + interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 729>, + <&cpg CPG_CORE R8A774A1_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 729>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; + }; + port@1 { + reg = <1>; + }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; + }; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a774a1"; + reg = <0 0xfeb00000 0 0x70000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>; + clock-names = "du.0", "du.1", "du.2"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.2"; + status = "disabled"; + + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; + }; + }; + port@2 { + reg = <2>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a774a1-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + sustainable-power = <3874>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + sustainable-power = <3874>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + sustainable-power = <3874>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a57_0 0 2>; + contribution = <1024>; + }; + map1 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; + }; + }; + trips { + target: trip-point1 { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; +}; diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 51b6e018bd..e3c6c10f13 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include "rockchip-u-boot.dtsi" +#include "rockchip-optee.dtsi" / { chosen { @@ -12,6 +13,30 @@ }; }; +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { + rom { + filename = "u-boot.rom"; + size = <0x400000>; + pad-byte = <0xff>; + + mkimage { + args = "-n rk3288 -T rkspi"; + u-boot-spl { + }; + }; + u-boot-img { + offset = <0x20000>; + }; + u-boot { + offset = <0x300000>; + }; + fdtmap { + }; + }; +}; +#endif + &dmc { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 7bddc3acdb..390ac2bb5a 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -4,3 +4,7 @@ */ #include "rk3399-u-boot.dtsi" + +&spi_flash { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index 7ac88392f2..f9c5bb607b 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -537,7 +537,7 @@ ap_i2c_audio: &i2c8 { pinctrl-names = "default", "sleep"; pinctrl-1 = <&spi1_sleep>; - spiflash@0 { + spi_flash: spiflash@0 { compatible = "jedec,spi-nor"; reg = <0>; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 8237782408..ecd230c720 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -4,11 +4,14 @@ */ #define USB_CLASS_HUB 9 +#include "rockchip-u-boot.dtsi" + / { aliases { mmc0 = &sdhci; mmc1 = &sdmmc; pci0 = &pcie0; + spi1 = &spi1; }; cic: syscon@ff620000 { @@ -57,6 +60,30 @@ }; +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { + rom { + filename = "u-boot.rom"; + size = <0x400000>; + pad-byte = <0xff>; + + mkimage { + args = "-n rk3399 -T rkspi"; + u-boot-spl { + }; + }; + u-boot-img { + offset = <0x40000>; + }; + u-boot { + offset = <0x300000>; + }; + fdtmap { + }; + }; +}; +#endif + &cru { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi new file mode 100644 index 0000000000..cde9b81b26 --- /dev/null +++ b/arch/arm/dts/rockchip-optee.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Google LLC + */ + +#include <config.h> + +#if defined(CONFIG_HAS_ROM) && defined(CONFIG_FIT) +&binman { + itb { + filename = "u-boot.itb"; + fit { + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + description = "FIT image with OP-TEE support"; + #address-cells = <1>; + + images { + uboot { + description = "U-Boot"; + type = "standalone"; + os = "U-Boot"; + arch = "arm"; + compression = "none"; + load = <CONFIG_SYS_TEXT_BASE>; + + u-boot-nodtb { + }; + }; + optee { + description = "OP-TEE"; + type = "firmware"; + arch = "arm"; + os = "tee"; + compression = "none"; + load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; + entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; + + blob-ext { + filename = "tee.bin"; + }; + }; + fdt { + description = CONFIG_SYS_BOARD; + type = "flat_dt"; + compression = "none"; + + u-boot-dtb { + }; + }; + }; + + configurations { + default = "conf"; + conf { + description = CONFIG_SYS_BOARD; + firmware = "optee"; + loadables = "uboot"; + fdt = "fdt"; + }; + }; + }; + }; +}; +#endif diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index a2559e2db0..eae3ee715d 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -6,7 +6,14 @@ #include <config.h> / { - binman { + binman: binman { + multiple-images; + }; +}; + +#ifdef CONFIG_SPL +&binman { + simple-bin { filename = "u-boot-rockchip.bin"; pad-byte = <0xff>; @@ -19,3 +26,4 @@ }; }; }; +#endif diff --git a/arch/arm/dts/s5p4418-nanopi2.dts b/arch/arm/dts/s5p4418-nanopi2.dts new file mode 100644 index 0000000000..4deaf10a1c --- /dev/null +++ b/arch/arm/dts/s5p4418-nanopi2.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net> + * + * (C) Copyright 2017 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * (C) Copyright 2016 Nexell + * Youngbok, Park <park@nexell.co.kr> + */ + +/dts-v1/; +#include "s5p4418.dtsi" + +/ { + model = "FriendlyElec boards based on Nexell s5p4418"; + cpu-model = "S5p4418"; + + compatible = "friendlyelec,nanopi2", + "nexell,s5p4418"; + + aliases { + mmc0 = "/mmc@c0069000"; + mmc1 = "/mmc@c0062000"; + i2c0 = "/i2c@c00a4000"; + i2c1 = "/i2c@c00a5000"; + i2c2 = "/i2c@c00a6000"; + }; + + mmc0:mmc@c0062000 { + frequency = <50000000>; + drive_dly = <0x0>; + drive_shift = <0x03>; + sample_dly = <0x00>; + sample_shift = <0x02>; + mmcboost = <0>; + status = "okay"; + }; + + mmc2:mmc@c0069000 { + frequency = <50000000>; + drive_dly = <0x0>; + drive_shift = <0x03>; + sample_dly = <0x00>; + sample_shift = <0x02>; + mmcboost = <0>; + status = "okay"; + }; + + /* NanoPi2: Header "CON2", NanoPC-T2: EEPROM (MAC-Addr.) and Audio */ + i2c0:i2c@c00a4000 { + status ="okay"; + }; + + /* NanoPi2: Header "CON2" and HDMI, NanoPC-T2: HDMI */ + i2c1:i2c@c00a5000 { + status ="okay"; + }; + + /* NanoPi2: LCD interface, NanoPC-T2: LCD, LVDS and MIPI interfaces */ + i2c2:i2c@c00a6000 { + status ="okay"; + }; + + dp0:dp@c0102800 { + status = "okay"; + module = <0>; + lcd-type = "lvds"; + + dp-device { + format = <0>; /* 0:VESA, 1:JEIDA */ + }; + + dp-sync { + h_active_len = <1024>; + h_front_porch = <84>; + h_back_porch = <84>; + h_sync_width = <88>; + h_sync_invert = <0>; + v_active_len = <600>; + v_front_porch = <10>; + v_back_porch = <10>; + v_sync_width = <20>; + v_sync_invert = <0>; + }; + + dp-ctrl { + clk_src_lv0 = <3>; + clk_div_lv0 = <16>; + clk_src_lv1 = <7>; + clk_div_lv1 = <1>; + out_format = <2>; + }; + + dp-planes { + layer_top { + screen_width = <1024>; + screen_height = <600>; + back_color = <0x0>; + }; + + layer_1 { /* RGB 1 */ + width = <1024>; + height = <600>; + format = <0x06530000>; + pixel_byte = <4>; + }; + }; + }; +}; diff --git a/arch/arm/dts/s5p4418-pinctrl.dtsi b/arch/arm/dts/s5p4418-pinctrl.dtsi new file mode 100644 index 0000000000..a7e1c2c381 --- /dev/null +++ b/arch/arm/dts/s5p4418-pinctrl.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nexell's s5p6818 SoC pin-mux and pin-config device tree source + * + * (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net> + * + * Copyright (C) 2016 Nexell Co., Ltd. + * http://www.nexell.co.kr + * + * Nexell's s5p6818 SoC pin-mux and pin-config options are listed as + * device tree nodes in this file. + */ + +pinctrl@C0010000 { + /* + * values for "pin-pull": + * pulldown resistor = 0 + * pullup = 1 + * no pullup/down = 2 + */ + + /* MMC */ + mmc0_clk: mmc0-clk { + pins = "gpioa-29"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <2>; + }; + + mmc0_cmd: mmc0-cmd { + pins = "gpioa-31"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <1>; + }; + + mmc0_bus4: mmc0-bus-width4 { + pins = "gpiob-1, gpiob-3, gpiob-5, gpiob-7"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <1>; + }; + + mmc1_clk: mmc1-clk { + pins = "gpiod-22"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <2>; + }; + + mmc1_cmd: mmc1-cmd { + pins = "gpiod-23"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <1>; + }; + + mmc1_bus4: mmc1-bus-width4 { + pins = "gpiod-24, gpiod-25, gpiod-26, gpiod-27"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <1>; + }; + + mmc2_clk: mmc2-clk { + pins = "gpioc-18"; + pin-function = <2>; + pin-pull = <2>; + pin-strength = <2>; + }; + + mmc2_cmd: mmc2-cmd { + pins = "gpioc-19"; + pin-function = <2>; + pin-pull = <2>; + pin-strength = <1>; + }; + + mmc2_bus4: mmc2-bus-width4 { + pins = "gpioc-20, gpioc-21, gpioc-22, gpioc-23"; + pin-function = <2>; + pin-pull = <2>; + pin-strength = <1>; + }; + + mmc2_bus8: mmc2-bus-width8 { + nexell,pins = "gpioe-21", "gpioe-22", "gpioe-23", "gpioe-24"; + pin-function = <2>; + pin-pull = <2>; + pin-strength = <1>; + }; + + /* I2C */ + i2c0_sda:i2c0-sda { + pins = "gpiod-3"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + i2c0_scl:i2c0-scl { + pins = "gpiod-2"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + i2c1_sda:i2c1-sda { + pins = "gpiod-5"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + i2c1_scl:i2c1-scl { + pins = "gpiod-4"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + i2c2_sda:i2c2-sda { + pins = "gpiod-7"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + i2c2_scl:i2c2-scl { + pins = "gpiod-6"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; +}; diff --git a/arch/arm/dts/s5p4418.dtsi b/arch/arm/dts/s5p4418.dtsi new file mode 100644 index 0000000000..a4d1a1bd03 --- /dev/null +++ b/arch/arm/dts/s5p4418.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net> + * + * (C) Copyright 2016 Nexell + * Youngbok, Park <park@nexell.co.kr> + * + */ + +#include "skeleton.dtsi" + +/ { + #include "s5p4418-pinctrl.dtsi" + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &mmc2; + gmac = "/ethernet@c0060000"; + }; + + mmc2:mmc@c0069000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nexell,nexell-dwmmc"; + reg = <0xc0069000 0x1000>; + bus-width = <4>; + index = <2>; + max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_clk>, <&mmc2_cmd>, <&mmc2_bus4>; + status = "disabled"; + }; + + mmc1:mmc@c0068000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nexell,nexell-dwmmc"; + reg = <0xc0068000 0x1000>; + bus-width = <4>; + index = <1>; + max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_clk>, <&mmc1_cmd>, <&mmc1_bus4>; + status = "disabled"; + }; + + mmc0:mmc@c0062000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nexell,nexell-dwmmc"; + reg = <0xc0062000 0x1000>; + bus-width = <4>; + index = <0>; + max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_clk>, <&mmc0_cmd>, <&mmc0_bus4>; + status = "disabled"; + }; + + i2c0:i2c@c00a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nexell,s5pxx18-i2c"; + reg = <0xc00a4000 0x100>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_sda>, <&i2c0_scl>; + status ="disabled"; + }; + + i2c1:i2c@c00a5000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nexell,s5pxx18-i2c"; + reg = <0xc00a5000 0x100>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_sda>, <&i2c1_scl>; + status ="disabled"; + }; + + i2c2:i2c@c00a6000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nexell,s5pxx18-i2c"; + reg = <0xc00a6000 0x100>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_sda>, <&i2c2_scl>; + status ="disabled"; + }; + + dp0:dp@c0102800 { + compatible = "nexell,nexell-display"; + reg = <0xc0102800 0x100>; + index = <0>; + u-boot,dm-pre-reloc; + status = "disabled"; + }; + + dp1:dp@c0102c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nexell,nexell-display"; + reg = <0xc0102c00 0x100>; + index = <1>; + status = "disabled"; + }; + + gpio_a:gpio@c001a000 { + compatible = "nexell,nexell-gpio"; + reg = <0xc001a000 0x00000010>; + altr,gpio-bank-width = <32>; + gpio-bank-name = "gpio_a"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_b:gpio@c001b000 { + compatible = "nexell,nexell-gpio"; + reg = <0xc001b000 0x00000010>; + altr,gpio-bank-width = <32>; + gpio-bank-name = "gpio_b"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_c:gpio@c001c000 { + compatible = "nexell,nexell-gpio"; + reg = <0xc001c000 0x00000010>; + nexell,gpio-bank-width = <32>; + gpio-bank-name = "gpio_c"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_d:gpio@c001d000 { + compatible = "nexell,nexell-gpio"; + reg = <0xc001d000 0x00000010>; + nexell,gpio-bank-width = <32>; + gpio-bank-name = "gpio_d"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_e:gpio@c001e000 { + compatible = "nexell,nexell-gpio"; + reg = <0xc001e000 0x00000010>; + nexell,gpio-bank-width = <32>; + gpio-bank-name = "gpio_e"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_alv:gpio@c0010800 { + compatible = "nexell,nexell-gpio"; + reg = <0xc0010800 0x00000010>; + nexell,gpio-bank-width = <32>; + gpio-bank-name = "gpio_alv"; + gpio-controller; + #gpio-cells = <2>; + }; + + pinctrl@C0010000 { + compatible = "nexell,s5pxx18-pinctrl"; + reg = <0xc0010000 0xf000>; + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index c385896ebc..e9525b5d06 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -6,7 +6,7 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { - adc1_in6_pins_a: adc1-in6 { + adc1_in6_pins_a: adc1-in6-0 { pins { pinmux = <STM32_PINMUX('F', 12, ANALOG)>; }; @@ -21,6 +21,13 @@ }; }; + adc12_ain_pins_b: adc12-ain-1 { + pins { + pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ + <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */ + }; + }; + adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { pins { pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ @@ -37,7 +44,7 @@ }; }; - cec_pins_sleep_a: cec-sleep-0 { + cec_sleep_pins_a: cec-sleep-0 { pins { pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ }; @@ -52,19 +59,19 @@ }; }; - cec_pins_sleep_b: cec-sleep-1 { + cec_sleep_pins_b: cec-sleep-1 { pins { pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ }; }; - dac_ch1_pins_a: dac-ch1 { + dac_ch1_pins_a: dac-ch1-0 { pins { pinmux = <STM32_PINMUX('A', 4, ANALOG)>; }; }; - dac_ch2_pins_a: dac-ch2 { + dac_ch2_pins_a: dac-ch2-0 { pins { pinmux = <STM32_PINMUX('A', 5, ANALOG)>; }; @@ -142,7 +149,7 @@ }; }; - ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { + ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ @@ -166,6 +173,57 @@ pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ + }; + }; + + ethernet0_rgmii_pins_c: rgmii-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ @@ -193,7 +251,7 @@ }; }; - ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 { + ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { pins1 { pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ @@ -233,7 +291,7 @@ }; }; - ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { + ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { pins1 { pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ @@ -301,14 +359,14 @@ }; }; - i2c1_pins_sleep_a: i2c1-1 { + i2c1_sleep_pins_a: i2c1-sleep-0 { pins { pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ }; }; - i2c1_pins_b: i2c1-2 { + i2c1_pins_b: i2c1-1 { pins { pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ @@ -318,7 +376,7 @@ }; }; - i2c1_pins_sleep_b: i2c1-3 { + i2c1_sleep_pins_b: i2c1-sleep-1 { pins { pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ @@ -335,14 +393,14 @@ }; }; - i2c2_pins_sleep_a: i2c2-1 { + i2c2_sleep_pins_a: i2c2-sleep-0 { pins { pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ }; }; - i2c2_pins_b1: i2c2-2 { + i2c2_pins_b1: i2c2-1 { pins { pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ bias-disable; @@ -351,13 +409,13 @@ }; }; - i2c2_pins_sleep_b1: i2c2-3 { + i2c2_sleep_pins_b1: i2c2-sleep-1 { pins { pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ }; }; - i2c2_pins_c: i2c2-4 { + i2c2_pins_c: i2c2-2 { pins { pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ @@ -367,7 +425,7 @@ }; }; - i2c2_pins_sleep_c: i2c2-5 { + i2c2_pins_sleep_c: i2c2-sleep-2 { pins { pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ @@ -384,7 +442,7 @@ }; }; - i2c5_pins_sleep_a: i2c5-1 { + i2c5_sleep_pins_a: i2c5-sleep-0 { pins { pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ @@ -392,6 +450,23 @@ }; }; + i2c5_pins_b: i2c5-1 { + pins { + pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ + <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_b: i2c5-sleep-1 { + pins { + pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */ + <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */ + }; + }; + i2s2_pins_a: i2s2-0 { pins { pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ @@ -403,7 +478,7 @@ }; }; - i2s2_pins_sleep_a: i2s2-1 { + i2s2_sleep_pins_a: i2s2-sleep-0 { pins { pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ @@ -411,7 +486,7 @@ }; }; - ltdc_pins_a: ltdc-a-0 { + ltdc_pins_a: ltdc-0 { pins { pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ @@ -447,7 +522,7 @@ }; }; - ltdc_pins_sleep_a: ltdc-a-1 { + ltdc_sleep_pins_a: ltdc-sleep-0 { pins { pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ @@ -480,7 +555,7 @@ }; }; - ltdc_pins_b: ltdc-b-0 { + ltdc_pins_b: ltdc-1 { pins { pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ @@ -516,7 +591,7 @@ }; }; - ltdc_pins_sleep_b: ltdc-b-1 { + ltdc_sleep_pins_b: ltdc-sleep-1 { pins { pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ @@ -549,6 +624,142 @@ }; }; + ltdc_pins_c: ltdc-2 { + pins1 { + pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */ + <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */ + <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */ + <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */ + <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */ + <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ + <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */ + <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */ + <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ + <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ + <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */ + <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ + <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ + <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ + <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ + <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ + <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ + <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ + <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */ + <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ + <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_sleep_pins_c: ltdc-sleep-2 { + pins1 { + pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */ + <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */ + <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */ + <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */ + <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */ + <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */ + <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */ + <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */ + <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */ + <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */ + <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */ + <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */ + <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */ + <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */ + <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */ + <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */ + <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */ + <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */ + <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */ + <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */ + }; + }; + + ltdc_pins_d: ltdc-3 { + pins1 { + pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ + <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */ + <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */ + <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ + <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ + <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ + <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */ + <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */ + <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ + <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ + <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ + <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */ + <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ + <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */ + <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ + <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */ + <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */ + <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */ + <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ + <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ + <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ + <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ + <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */ + <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ + <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ + <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + ltdc_sleep_pins_d: ltdc-sleep-3 { + pins { + pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ + <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ + <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */ + <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */ + <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ + <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ + <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ + <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */ + <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ + <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ + <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ + <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */ + <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ + <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */ + <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */ + <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */ + <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ + <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ + <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ + <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */ + <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ + <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ + <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ @@ -569,6 +780,46 @@ }; }; + m_can1_pins_b: m-can1-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_b: m_can1-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */ + }; + }; + + m_can2_pins_a: m-can2-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ + bias-disable; + }; + }; + + m_can2_sleep_pins_a: m_can2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */ + <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */ + }; + }; + pwm1_pins_a: pwm1-0 { pins { pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ @@ -618,6 +869,21 @@ }; }; + pwm3_pins_b: pwm3-1 { + pins { + pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_b: pwm3-sleep-1 { + pins { + pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */ + }; + }; + pwm4_pins_a: pwm4-0 { pins { pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ @@ -665,6 +931,25 @@ }; }; + pwm5_pins_b: pwm5-1 { + pins { + pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */ + <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */ + <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_sleep_pins_b: pwm5-sleep-1 { + pins { + pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */ + <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */ + }; + }; + pwm8_pins_a: pwm8-0 { pins { pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ @@ -778,7 +1063,7 @@ }; }; - sai2a_sleep_pins_a: sai2a-1 { + sai2a_sleep_pins_a: sai2a-sleep-0 { pins { pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ @@ -787,7 +1072,7 @@ }; }; - sai2a_pins_b: sai2a-2 { + sai2a_pins_b: sai2a-1 { pins1 { pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ @@ -798,7 +1083,7 @@ }; }; - sai2a_sleep_pins_b: sai2a-sleep-3 { + sai2a_sleep_pins_b: sai2a-sleep-1 { pins { pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ @@ -806,6 +1091,25 @@ }; }; + sai2a_pins_c: sai2a-4 { + pins { + pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */ + <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */ + <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_sleep_pins_c: sai2a-5 { + pins { + pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */ + <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */ + <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */ + }; + }; + sai2b_pins_a: sai2b-0 { pins1 { pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ @@ -821,7 +1125,7 @@ }; }; - sai2b_sleep_pins_a: sai2b-1 { + sai2b_sleep_pins_a: sai2b-sleep-0 { pins { pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ @@ -830,14 +1134,27 @@ }; }; - sai2b_pins_b: sai2b-2 { + sai2b_pins_b: sai2b-1 { pins { pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ bias-disable; }; }; - sai2b_sleep_pins_b: sai2b-3 { + sai2b_sleep_pins_b: sai2b-sleep-1 { + pins { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ + }; + }; + + sai2b_pins_c: sai2a-4 { + pins1 { + pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_c: sai2a-sleep-5 { pins { pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ }; @@ -852,7 +1169,7 @@ }; }; - sai4a_sleep_pins_a: sai4a-1 { + sai4a_sleep_pins_a: sai4a-sleep-0 { pins { pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ }; @@ -939,7 +1256,7 @@ sdmmc1_dir_pins_b: sdmmc1-dir-1 { pins1 { pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('E', 14, AF8)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ slew-rate = <1>; drive-push-pull; @@ -954,9 +1271,9 @@ sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { pins { pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ - <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ - <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ + <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ + <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ }; }; @@ -1080,6 +1397,27 @@ sdmmc2_d47_pins_b: sdmmc2-d47-1 { pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_pins_c: sdmmc2-d47-2 { + pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ @@ -1090,7 +1428,7 @@ }; }; - sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { + sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { pins { pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */ @@ -1153,6 +1491,60 @@ }; }; + sdmmc3_b4_pins_b: sdmmc3-b4-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ + <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { + pins { + pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ + <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ + <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ + }; + }; + spdifrx_pins_a: spdifrx-0 { pins { pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ @@ -1160,7 +1552,7 @@ }; }; - spdifrx_sleep_pins_a: spdifrx-1 { + spdifrx_sleep_pins_a: spdifrx-sleep-0 { pins { pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ }; @@ -1168,15 +1560,15 @@ spi2_pins_a: spi2-0 { pins1 { - pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ - <STM32_PINMUX('I', 0, AF5)>, /* SPI2_NSS */ - <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ + pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */ + <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <1>; }; + pins2 { - pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ + pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */ bias-disable; }; }; @@ -1188,6 +1580,54 @@ }; }; + usart2_pins_a: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; + + usart2_pins_b: usart2-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; + usart3_pins_a: usart3-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ @@ -1227,6 +1667,19 @@ }; }; + uart4_pins_c: uart4-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + uart7_pins_a: uart7-0 { pins1 { pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */ @@ -1242,6 +1695,19 @@ }; }; + uart7_pins_b: uart7-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + uart8_pins_a: uart8-0 { pins1 { pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ @@ -1279,7 +1745,7 @@ }; }; - i2c2_pins_sleep_b2: i2c2-1 { + i2c2_sleep_pins_b2: i2c2-sleep-0 { pins { pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ }; @@ -1295,7 +1761,7 @@ }; }; - i2c4_pins_sleep_a: i2c4-1 { + i2c4_sleep_pins_a: i2c4-sleep-0 { pins { pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ @@ -1316,4 +1782,18 @@ bias-disable; }; }; + + spi4_pins_a: spi4-0 { + pins { + pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ + <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ + bias-disable; + }; + }; }; diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index 66be7df9ae..7ec90fe4a3 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -32,6 +32,10 @@ reboot { u-boot,dm-pre-reloc; + compatible = "syscon-reboot"; + regmap = <&rcc>; + offset = <0x404>; + mask = <0x1>; }; soc { @@ -185,6 +189,38 @@ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; }; +&usart1 { + resets = <&rcc USART1_R>; +}; + +&usart2 { + resets = <&rcc USART2_R>; +}; + +&usart3 { + resets = <&rcc USART3_R>; +}; + +&uart4 { + resets = <&rcc UART4_R>; +}; + +&uart5 { + resets = <&rcc UART5_R>; +}; + +&usart6 { + resets = <&rcc USART6_R>; +}; + +&uart7 { + resets = <&rcc UART7_R>; +}; + +&uart8{ + resets = <&rcc UART8_R>; +}; + &usbotg_hs { compatible = "st,stm32mp1-hsotg", "snps,dwc2"; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index d5216a1831..0d97f56fca 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -44,8 +44,6 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; }; intc: interrupt-controller@a0021000 { @@ -128,13 +126,6 @@ status = "disabled"; }; - reboot { - compatible = "syscon-reboot"; - regmap = <&rcc>; - offset = <0x404>; - mask = <0x1>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; @@ -500,7 +491,7 @@ }; i2c1: i2c@40012000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40012000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, @@ -509,12 +500,13 @@ resets = <&rcc I2C1_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x1>; wakeup-source; status = "disabled"; }; i2c2: i2c@40013000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40013000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, @@ -523,12 +515,13 @@ resets = <&rcc I2C2_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x2>; wakeup-source; status = "disabled"; }; i2c3: i2c@40014000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40014000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, @@ -537,12 +530,13 @@ resets = <&rcc I2C3_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x4>; wakeup-source; status = "disabled"; }; i2c5: i2c@40015000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40015000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, @@ -551,6 +545,7 @@ resets = <&rcc I2C5_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x10>; wakeup-source; status = "disabled"; }; @@ -575,14 +570,14 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; @@ -1157,6 +1152,11 @@ }; }; + pwr_mcu: pwr_mcu@50001014 { + compatible = "syscon"; + reg = <0x50001014 0x4>; + }; + exti: interrupt-controller@5000d000 { compatible = "st,stm32mp1-exti", "syscon"; interrupt-controller; @@ -1413,14 +1413,12 @@ "mac-clk-tx", "mac-clk-rx", "eth-ck", - "ethstp", - "syscfg-clk"; + "ethstp"; clocks = <&rcc ETHMAC>, <&rcc ETHTX>, <&rcc ETHRX>, <&rcc ETHCK_K>, - <&rcc ETHSTP>, - <&rcc SYSCFG>; + <&rcc ETHSTP>; st,syscon = <&syscfg 0x4>; snps,mixed-burst; snps,pbl = <2>; @@ -1458,6 +1456,11 @@ clock-names = "lcd"; resets = <&rcc LTDC_R>; status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + }; }; iwdg2: watchdog@5a002000 { @@ -1513,7 +1516,7 @@ }; i2c4: i2c@5c002000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x5c002000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, @@ -1522,6 +1525,7 @@ resets = <&rcc I2C4_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x8>; wakeup-source; status = "disabled"; }; @@ -1552,7 +1556,7 @@ }; i2c6: i2c@5c009000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x5c009000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, @@ -1561,6 +1565,7 @@ resets = <&rcc I2C6_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x20>; wakeup-source; status = "disabled"; }; @@ -1742,6 +1747,7 @@ resets = <&rcc MCU_R>; st,syscfg-holdboot = <&rcc 0x10C 0x1>; st,syscfg-tz = <&rcc 0x000 0x1>; + st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; status = "disabled"; }; }; diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi index 3f0a4a91cc..54e73ccea4 100644 --- a/arch/arm/dts/stm32mp157.dtsi +++ b/arch/arm/dts/stm32mp157.dtsi @@ -15,7 +15,6 @@ clocks = <&rcc GPU>, <&rcc GPU_K>; clock-names = "bus" ,"core"; resets = <&rcc GPU_R>; - status = "disabled"; }; dsi: dsi@5a000000 { @@ -25,7 +24,14 @@ clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index 7b8c1c1cc7..6787619290 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -16,6 +16,7 @@ config { u-boot,boot-led = "heartbeat"; u-boot,error-led = "error"; + u-boot,mmc-env-partition = "ssbl"; st,adc_usb_pd = <&adc1 18>, <&adc1 19>; st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; @@ -162,8 +163,6 @@ &sdmmc1 { u-boot,dm-spl; - broken-cd; - /delete-property/ cd-gpios; }; &sdmmc1_b4_pins_a { @@ -194,5 +193,4 @@ &usbotg_hs { u-boot,force-b-session-valid; - hnp-srp-disable; }; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 7985b80967..9a8a26710a 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -27,15 +27,10 @@ }; &dsi { - #address-cells = <1>; - #size-cells = <0>; status = "okay"; phy-dsi-supply = <®18>; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; dsi_in: endpoint { @@ -83,9 +78,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep1_out: endpoint@1 { reg = <1>; remote-endpoint = <&dsi_in>; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index ef3e7f45a3..f3002e995b 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -17,6 +17,7 @@ config { u-boot,boot-led = "heartbeat"; u-boot,error-led = "error"; + u-boot,mmc-env-partition = "ssbl"; st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; }; @@ -158,8 +159,6 @@ &sdmmc1 { u-boot,dm-spl; - broken-cd; - /delete-property/ cd-gpios; }; &sdmmc1_b4_pins_a { diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index c4c1202789..072d646379 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -134,13 +134,12 @@ &gpu { contiguous-area = <&gpu_reserved>; - status = "okay"; }; &i2c4 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_pins_sleep_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; clock-frequency = <400000>; @@ -328,6 +327,10 @@ bus-width = <4>; vmmc-supply = <&vdd_sd>; vqmmc-supply = <&sd_switch>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 8a4c7ff31a..b19056557e 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -98,15 +98,10 @@ }; &dsi { - #address-cells = <1>; - #size-cells = <0>; phy-dsi-supply = <®18>; status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; dsi_in: endpoint { @@ -141,7 +136,7 @@ ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii-id"; max-speed = <1000>; @@ -176,7 +171,7 @@ &i2c2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_pins_a>; - pinctrl-1 = <&i2c2_pins_sleep_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; @@ -230,7 +225,7 @@ &i2c5 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c5_pins_a>; - pinctrl-1 = <&i2c5_pins_sleep_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; @@ -240,9 +235,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep0_out: endpoint@0 { reg = <0>; remote-endpoint = <&dsi_in>; diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi new file mode 100644 index 0000000000..6be728846e --- /dev/null +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com> + */ + +#include <dt-bindings/clock/stm32mp1-clksrc.h> +#include "stm32mp15-u-boot.dtsi" +#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" + +/ { + config { + u-boot,boot-led = "heartbeat"; + }; +}; + +&clk_hse { + st,digbypass; +}; + +&i2c2 { + u-boot,dm-pre-reloc; +}; + +&i2c2_pins_a { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + }; +}; + +&pmic { + u-boot,dm-pre-reloc; +}; + +&rcc { + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MCU_PLL3P + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + >; + + st,clkdiv = < + 1 /*MPU*/ + 0 /*AXI*/ + 0 /*MCU*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 23 /*RTC*/ + 0 /*MCO1*/ + 0 /*MCO2*/ + >; + + st,pkcs = < + CLK_CKPER_HSE + CLK_FMC_ACLK + CLK_QSPI_ACLK + CLK_ETH_DISABLED + CLK_SDMMC12_PLL4P + CLK_DSI_DSIPLL + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_SPI2S1_PLL3Q + CLK_SPI2S23_PLL3Q + CLK_SPI45_HSI + CLK_SPI6_HSI + CLK_I2C46_HSI + CLK_SDMMC3_PLL4P + CLK_USBO_USBPHY + CLK_ADC_CKPER + CLK_CEC_LSE + CLK_I2C12_HSI + CLK_I2C35_HSI + CLK_UART1_HSI + CLK_UART24_HSI + CLK_UART35_HSI + CLK_UART6_HSI + CLK_UART78_HSI + CLK_SPDIF_PLL4P + CLK_FDCAN_PLL4R + CLK_SAI1_PLL3Q + CLK_SAI2_PLL3Q + CLK_SAI3_PLL3Q + CLK_SAI4_PLL3Q + CLK_RNG1_LSI + CLK_RNG2_LSI + CLK_LPTIM1_PCLK1 + CLK_LPTIM23_PCLK3 + CLK_LPTIM45_LSE + >; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ + pll2: st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = < 2 65 1 0 0 PQR(1,1,1) >; + frac = < 0x1400 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ + pll3: st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = < 1 33 1 16 36 PQR(1,1,1) >; + frac = < 0x1a04 >; + u-boot,dm-pre-reloc; + }; + + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ + pll4: st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = < 3 98 5 7 7 PQR(1,1,1) >; + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi new file mode 100644 index 0000000000..83ff2e7ce1 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com> + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/st,stpmic1.h> + +/ { + + model = "Seeed Studio Odyssey-STM32MP157C SOM"; + compatible = "seeed,odyssey-stm32mp157c-som", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + gpu_reserved: gpu@d4000000 { + reg = <0xd4000000 0x4000000>; + no-map; + }; + + optee@de000000 { + reg = <0xde000000 0x02000000>; + no-map; + }; + }; + + led { + compatible = "gpio-leds"; + blue { + label = "heartbeat"; + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + +}; + +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO1 0>; + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO2 0>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO5 0>; + regulator-boot-on; + }; + + v1v2_hdmi: ldo6 { + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO6 0>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + broken-cd; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm1_pins_a>; + pinctrl-1 = <&pwm1_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@0 { + status = "okay"; + }; +}; + +&timers3 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm3_pins_a>; + pinctrl-1 = <&pwm3_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>; + pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@3 { + status = "okay"; + }; +}; + +&timers5 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@4 { + status = "okay"; + }; +}; + +&timers6 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + timer@5 { + status = "okay"; + }; +}; + +&timers12 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm12_pins_a>; + pinctrl-1 = <&pwm12_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@11 { + status = "okay"; + }; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp157c-odyssey-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-u-boot.dtsi new file mode 100644 index 0000000000..abceba5cbd --- /dev/null +++ b/arch/arm/dts/stm32mp157c-odyssey-u-boot.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com> + */ + + #include "stm32mp157c-odyssey-som-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc1; + usb0 = &usbotg_hs; + }; + config { + u-boot,boot-led = "heartbeat"; + u-boot,error-led = "error"; + }; + led { + red { + label = "error"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + status = "okay"; + }; + }; +}; + +&adc { + status = "okay"; +}; + +&sdmmc1 { + u-boot,dm-spl; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; +}; + diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts new file mode 100644 index 0000000000..0e725498dd --- /dev/null +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com> + */ + +/dts-v1/; + +#include "stm32mp157c-odyssey-som.dtsi" + +/ { + + model = "Seeed Studio Odyssey-STM32MP157C Board"; + compatible = "seeed,odyssey-stm32mp157c", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + blue { + label = "heartbeat"; + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>; + vdd-supply = <&vdd>; + vdda-supply = <&vdd>; + vref-supply = <&vrefbuf>; + status = "disabled"; + adc1: adc@0 { + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (56 + 47kOhms) * 5pF => 2.5us. + * Use arbitrary margin here (e.g. 5us). + */ + st,min-sample-time-nsecs = <5000>; + /* AIN connector, USB Type-C CC1 & CC2 */ + st,adc-channels = <0 1 6 13 18 19>; + status = "okay"; + }; + adc2: adc@100 { + /* AIN connector, USB Type-C CC1 & CC2 */ + st,adc-channels = <0 1 2 6 18 19>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +&cec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cec_pins_b>; + pinctrl-1 = <&cec_sleep_pins_b>; + status = "okay"; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2s2 { + clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "i2sclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s2_pins_a>; + pinctrl-1 = <&i2s2_sleep_pins_a>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi new file mode 100644 index 0000000000..f83cfe90b8 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + */ + +#include "stm32mp15xx-dhcom-u-boot.dtsi" diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts new file mode 100644 index 0000000000..5a237a3b7b --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + */ + +#include "stm32mp15xx-dhcom.dtsi" + +/ { + model = "DH Electronics STM32MP15xx DHCOM DRC02"; + compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx"; + + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&gpiob { + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the STM32 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + usb-hub { + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485-rx-en"; + }; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "Out1", + "Out2", "", "", ""; +}; + +&gpioi { + gpio-line-names = "In1", "", "", "", + "", "", "", "", + "In2", "", "", "", + "", "", "", ""; + + /* + * NOTE: The USB Hub on the DRC02 needs a reset signal to be + * pulled high in order to be detected by the USB Controller. + * This signal should be handled by USB power sequencing in + * order to reset the Hub when USB bus is powered down, but + * so far there is no such functionality. + */ + usb-hub { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c5 { /* TP7/TP8 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&sdmmc3 { + /* + * On DRC02, the SoM does not have SDIO WiFi. The pins + * are used for on-board microSD slot instead. + */ + /delete-property/broken-cd; + cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + cs-gpios = <&gpioz 3 0>; + /* Use PIO for the display */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; /* Enable once there is display driver */ + /* + * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are + * also connected to the display board connector. + */ +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +/* + * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), + * however the STM32MP1 pinmux cannot map them to UART4 . + */ + +&uart8 { /* RS485 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts index dd98c7abee..52a77c4123 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts @@ -11,78 +11,9 @@ aliases { serial0 = &uart4; - ethernet0 = ðernet0; }; chosen { stdout-path = "serial0:115200n8"; }; - - ethernet_vio: vioregulator { - compatible = "regulator-fixed"; - regulator-name = "vio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rmii"; - max-speed = <100>; - phy-handle = <&phy0>; - st,eth_ref_clk_sel; - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&pinctrl { - ethernet0_rmii_pins_a: rmii-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ - <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ - <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ - <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ - <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ - <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ - <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ - <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ - bias-disable; - }; - }; - - ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ - <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ - <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ - <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ - <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ - <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ - <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ - <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ - <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ - }; - }; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 69c5af4241..f96de9e7a3 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -264,9 +264,6 @@ &sdmmc1 { u-boot,dm-spl; - broken-cd; - /delete-property/ cd-gpios; - /delete-property/ disable-wp; }; &sdmmc1_b4_pins_a { diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index b3f4cb4515..643aec94ce 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -14,12 +14,23 @@ / { aliases { eeprom0 = &eeprom0; + ethernet0 = ðernet0; }; memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x40000000>; }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + }; }; &cec { @@ -39,6 +50,28 @@ status = "okay"; }; +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth_ref_clk_sel; + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; @@ -228,6 +261,42 @@ vdd_3v3_usbfs-supply = <&vdd_usb>; }; +&pinctrl { + ethernet0_rmii_pins_a: rmii-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; +}; + &qspi { pinctrl-names = "default", "sleep"; pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts index c1cc80bcf5..88f25d89b2 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts @@ -89,8 +89,8 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_b>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii"; max-speed = <1000>; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index e7a46e7b5f..d660dfb74e 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -112,7 +112,11 @@ &cec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cec_pins_b>; - pinctrl-1 = <&cec_pins_sleep_b>; + pinctrl-1 = <&cec_sleep_pins_b>; + status = "okay"; +}; + +&dts { status = "okay"; }; @@ -127,7 +131,7 @@ ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii-id"; max-speed = <1000>; @@ -145,13 +149,12 @@ &gpu { contiguous-area = <&gpu_reserved>; - status = "okay"; }; &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_pins_sleep_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; i2c-scl-rising-time-ns = <100>; i2c-scl-falling-time-ns = <7>; status = "okay"; @@ -226,7 +229,7 @@ &i2c4 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_pins_sleep_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; clock-frequency = <400000>; @@ -393,7 +396,7 @@ clock-names = "pclk", "i2sclk", "x8k", "x11k"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2s2_pins_a>; - pinctrl-1 = <&i2s2_pins_sleep_a>; + pinctrl-1 = <&i2s2_sleep_pins_a>; status = "okay"; i2s2_port: port { @@ -417,13 +420,10 @@ <dc { pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_a>; - pinctrl-1 = <<dc_pins_sleep_a>; + pinctrl-1 = <<dc_sleep_pins_a>; status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep0_out: endpoint@0 { reg = <0>; remote-endpoint = <&sii9022_in>; diff --git a/arch/arm/include/asm/arch-bcmns3/bl33_info.h b/arch/arm/include/asm/arch-bcmns3/bl33_info.h new file mode 100644 index 0000000000..bbc95b0186 --- /dev/null +++ b/arch/arm/include/asm/arch-bcmns3/bl33_info.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Broadcom. + * + */ + +#ifndef BL33_INFO_H +#define BL33_INFO_H +#include <asm/io.h> + +/* Increase version number each time this file is modified */ +#define BL33_INFO_VERSION 1 + +struct chip_info { + unsigned int chip_id; + unsigned int rev_id; +}; + +struct bl33_info { + unsigned int version; + struct chip_info chip; +}; + +extern struct bl33_info *bl33_info; + +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/gpio.h b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h new file mode 100644 index 0000000000..7ae5eee8b6 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/gpio.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +/* + * Dummy header file to enable CONFIG_OF_CONTROL. + * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. + * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable + * OF_CONTROL must have arch/gpio.h. + */ + +#ifndef __ASM_ARCH_MX85XX_GPIO_H +#define __ASM_ARCH_MX85XX_GPIO_H + +struct mpc8xxx_gpio_plat { + ulong addr; + ulong size; + uint ngpios; +}; + +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index 00aa91b0a2..faac8f1128 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -32,18 +32,16 @@ #define id_to_core(x) ((x & 3) | (x >> 6)) #ifndef __ASSEMBLY__ -extern u64 __spin_table[]; extern u64 __real_cntfrq; -extern u64 *secondary_boot_code; -extern size_t __secondary_boot_code_size; +extern void *secondary_boot_addr; +extern void *secondary_boot_code_start; +extern size_t secondary_boot_code_size; #ifdef CONFIG_MP int fsl_layerscape_wake_seconday_cores(void); #else static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } #endif void *get_spin_tbl_addr(void); -phys_addr_t determine_mp_bootpg(void); -void secondary_boot_func(void); int is_core_online(u64 cpu_id); u32 cpu_pos_mask(void); #endif diff --git a/arch/arm/include/asm/arch-mediatek/reset.h b/arch/arm/include/asm/arch-mediatek/reset.h index 9704666d24..4ba0bad94e 100644 --- a/arch/arm/include/asm/arch-mediatek/reset.h +++ b/arch/arm/include/asm/arch-mediatek/reset.h @@ -6,7 +6,7 @@ #ifndef __MEDIATEK_RESET_H #define __MEDIATEK_RESET_H -#include <dm.h> +struct udevice; int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs); diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h index 5131fabec4..35efec78c3 100644 --- a/arch/arm/include/asm/gic-v3.h +++ b/arch/arm/include/asm/gic-v3.h @@ -127,9 +127,9 @@ #define GIC_REDISTRIBUTOR_OFFSET 0x20000 #ifdef CONFIG_GIC_V3_ITS -int gic_lpi_tables_init(u64 base, u32 max_redist); +int gic_lpi_tables_init(void); #else -int gic_lpi_tables_init(u64 base, u32 max_redist) +int gic_lpi_tables_init(void) { return 0; } diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 333e407b66..7dc87afb83 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,12 +1,9 @@ #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \ !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ - !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \ - !defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \ - !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ - !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \ - !defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \ - !defined(CONFIG_CORTINA_PLATFORM) + !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \ + !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \ + !defined(CONFIG_TARGET_BCMNS3) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 37c1bfd726..ce552944b7 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -445,10 +445,16 @@ static inline void set_dacr(unsigned int val) #define TTBCR_EPD0 (0 << 7) /* - * Memory types + * VMSAv8-32 Long-descriptor format memory region attributes + * (ARM Architecture Reference Manual section G5.7.4 [DDI0487E.a]) + * + * MAIR0[ 7: 0] 0x00 Device-nGnRnE (aka Strongly-Ordered) + * MAIR0[15: 8] 0xaa Outer/Inner Write-Through, Read-Allocate No Write-Allocate + * MAIR0[23:16] 0xee Outer/Inner Write-Back, Read-Allocate No Write-Allocate + * MAIR0[31:24] 0xff Outer/Inner Write-Back, Read-Allocate Write-Allocate */ -#define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \ - (0xcc << (2 * 8)) | (0xff << (3 * 8))) +#define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0xaa << (1 * 8)) | \ + (0xee << (2 * 8)) | (0xff << (3 * 8))) /* options available for data cache on each page */ enum dcache_option { @@ -471,7 +477,16 @@ enum dcache_option { #define TTB_SECT_B_MASK (1 << 2) #define TTB_SECT (2 << 0) -/* options available for data cache on each page */ +/* + * Short-descriptor format memory region attributes, without TEX remap + * (ARM Architecture Reference Manual section G5.7.2 [DDI0487E.a]) + * + * TEX[0] C B + * 0 0 0 Device-nGnRnE (aka Strongly-Ordered) + * 0 1 0 Outer/Inner Write-Through, Read-Allocate No Write-Allocate + * 0 1 1 Outer/Inner Write-Back, Read-Allocate No Write-Allocate + * 1 1 1 Outer/Inner Write-Back, Read-Allocate Write-Allocate + */ enum dcache_option { DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index 90f37a123c..a1657e3853 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -3,6 +3,9 @@ * Copyright 2019 Broadcom. */ #include <common.h> +#include <dm.h> +#include <regmap.h> +#include <syscon.h> #include <asm/gic.h> #include <asm/gic-v3.h> #include <asm/io.h> @@ -15,23 +18,104 @@ static u32 lpi_id_bits; #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) +/* Number of GIC re-distributors */ +#define MAX_GIC_REDISTRIBUTORS 8 + +/* + * gic_v3_its_priv - gic details + * + * @gicd_base: gicd base address + * @gicr_base: gicr base address + * @lpi_base: gic lpi base address + * @num_redist: number of gic re-distributors + */ +struct gic_v3_its_priv { + ulong gicd_base; + ulong gicr_base; + ulong lpi_base; + u32 num_redist; +}; + +static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv) +{ + struct udevice *dev; + fdt_addr_t addr; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_IRQ, + DM_GET_DRIVER(arm_gic_v3_its), &dev); + if (ret) { + pr_err("%s: failed to get %s irq device\n", __func__, + DM_GET_DRIVER(arm_gic_v3_its)->name); + return ret; + } + + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) { + pr_err("%s: failed to get GICD address\n", __func__); + return -EINVAL; + } + priv->gicd_base = addr; + + addr = dev_read_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) { + pr_err("%s: failed to get GICR address\n", __func__); + return -EINVAL; + } + priv->gicr_base = addr; + + return 0; +} + +static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv) +{ + struct regmap *regmap; + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_SYSCON, + DM_GET_DRIVER(gic_lpi_syscon), &dev); + if (ret) { + pr_err("%s: failed to get %s syscon device\n", __func__, + DM_GET_DRIVER(gic_lpi_syscon)->name); + return ret; + } + + regmap = syscon_get_regmap(dev); + if (!regmap) { + pr_err("%s: failed to regmap for %s syscon device\n", __func__, + DM_GET_DRIVER(gic_lpi_syscon)->name); + return -ENODEV; + } + priv->lpi_base = regmap->ranges[0].start; + + priv->num_redist = dev_read_u32_default(dev, "max-gic-redistributors", + MAX_GIC_REDISTRIBUTORS); + + return 0; +} + /* * Program the GIC LPI configuration tables for all * the re-distributors and enable the LPI table - * base: Configuration table address - * num_redist: number of redistributors */ -int gic_lpi_tables_init(u64 base, u32 num_redist) +int gic_lpi_tables_init(void) { + struct gic_v3_its_priv priv; u32 gicd_typer; u64 val; u64 tmp; int i; u64 redist_lpi_base; - u64 pend_base = GICR_BASE + GICR_PENDBASER; + u64 pend_base; - gicd_typer = readl(GICD_BASE + GICD_TYPER); + if (gic_v3_its_get_gic_addr(&priv)) + return -EINVAL; + + if (gic_v3_its_get_gic_lpi_addr(&priv)) + return -EINVAL; + gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER)); /* GIC support for Locality specific peripheral interrupts (LPI's) */ if (!(gicd_typer & GICD_TYPER_LPIS)) { pr_err("GIC implementation does not support LPI's\n"); @@ -43,10 +127,10 @@ int gic_lpi_tables_init(u64 base, u32 num_redist) * Once the LPI table is enabled, can not program the * LPI configuration tables again, unless the GIC is reset. */ - for (i = 0; i < num_redist; i++) { + for (i = 0; i < priv.num_redist; i++) { u32 offset = i * GIC_REDISTRIBUTOR_OFFSET; - if ((readl((uintptr_t)(GICR_BASE + offset))) & + if ((readl((uintptr_t)(priv.gicr_base + offset))) & GICR_CTLR_ENABLE_LPIS) { pr_err("Re-Distributor %d LPI is already enabled\n", i); @@ -59,25 +143,27 @@ int gic_lpi_tables_init(u64 base, u32 num_redist) ITS_MAX_LPI_NRBITS); /* Set PropBase */ - val = (base | + val = (priv.lpi_base | GICR_PROPBASER_INNERSHAREABLE | GICR_PROPBASER_RAWAWB | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); - writeq(val, (GICR_BASE + GICR_PROPBASER)); - tmp = readl(GICR_BASE + GICR_PROPBASER); + writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER)); + tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER)); if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | GICR_PROPBASER_CACHEABILITY_MASK); val |= GICR_PROPBASER_NC; - writeq(val, (GICR_BASE + GICR_PROPBASER)); + writeq(val, + (uintptr_t)(priv.gicr_base + GICR_PROPBASER)); } } - redist_lpi_base = base + LPI_PROPBASE_SZ; + redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ; - for (i = 0; i < num_redist; i++) { + pend_base = priv.gicr_base + GICR_PENDBASER; + for (i = 0; i < priv.num_redist; i++) { u32 offset = i * GIC_REDISTRIBUTOR_OFFSET; val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) | @@ -94,9 +180,31 @@ int gic_lpi_tables_init(u64 base, u32 num_redist) } /* Enable LPI for the redistributor */ - writel(GICR_CTLR_ENABLE_LPIS, (uintptr_t)(GICR_BASE + offset)); + writel(GICR_CTLR_ENABLE_LPIS, + (uintptr_t)(priv.gicr_base + offset)); } return 0; } +static const struct udevice_id gic_v3_its_ids[] = { + { .compatible = "arm,gic-v3" }, + {} +}; + +U_BOOT_DRIVER(arm_gic_v3_its) = { + .name = "gic-v3", + .id = UCLASS_IRQ, + .of_match = gic_v3_its_ids, +}; + +static const struct udevice_id gic_lpi_syscon_ids[] = { + { .compatible = "gic-lpi-base" }, + {} +}; + +U_BOOT_DRIVER(gic_lpi_syscon) = { + .name = "gic-lpi-base", + .id = UCLASS_SYSCON, + .of_match = gic_lpi_syscon_ids, +}; diff --git a/arch/arm/mach-at91/config.mk b/arch/arm/mach-at91/config.mk index 9a023efb19..5426394651 100644 --- a/arch/arm/mach-at91/config.mk +++ b/arch/arm/mach-at91/config.mk @@ -4,6 +4,6 @@ endif ifeq ($(CONFIG_CPU_V7A),y) ifndef CONFIG_SPL_BUILD -ALL-y += u-boot.img +INPUTS-y += u-boot.img endif endif diff --git a/arch/arm/mach-davinci/config.mk b/arch/arm/mach-davinci/config.mk index 5a33982e2d..4674cae43b 100644 --- a/arch/arm/mach-davinci/config.mk +++ b/arch/arm/mach-davinci/config.mk @@ -2,5 +2,5 @@ # # Copyright (C) 2012, Texas Instruments, Incorporated - http://www.ti.com/ ifndef CONFIG_SPL_BUILD -ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais +INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais endif diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 694c26d35f..fe8d5947cc 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -8,6 +8,7 @@ #include <bootm.h> #include <common.h> +#include <dm.h> #include <init.h> #include <log.h> #include <net.h> diff --git a/arch/arm/mach-ipq40xx/Kconfig b/arch/arm/mach-ipq40xx/Kconfig new file mode 100644 index 0000000000..4eef80e935 --- /dev/null +++ b/arch/arm/mach-ipq40xx/Kconfig @@ -0,0 +1,15 @@ +if ARCH_IPQ40XX + +config SYS_SOC + default "ipq40xx" + +config SYS_MALLOC_F_LEN + default 0x2000 + +config SYS_TEXT_BASE + default 0x87300000 + +config NR_DRAM_BANKS + default 1 + +endif diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile new file mode 100644 index 0000000000..08a65b8854 --- /dev/null +++ b/arch/arm/mach-ipq40xx/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2019 Sartura Ltd. +# +# Author: Robert Marko <robert.marko@sartura.hr> + +obj-y += clock-ipq4019.o +obj-y += pinctrl-snapdragon.o +obj-y += pinctrl-ipq4019.o diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c new file mode 100644 index 0000000000..7cf98a203c --- /dev/null +++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Clock drivers for Qualcomm IPQ40xx + * + * Copyright (c) 2019 Sartura Ltd. + * + * Author: Robert Marko <robert.marko@sartura.hr> + * + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> + +struct msm_clk_priv { + phys_addr_t base; +}; + +ulong msm_set_rate(struct clk *clk, ulong rate) +{ + switch (clk->id) { + case 26: /*UART1*/ + /* This clock is already initialized by SBL1 */ + return 0; + break; + default: + return 0; + } +} + +static int msm_clk_probe(struct udevice *dev) +{ + struct msm_clk_priv *priv = dev_get_priv(dev); + + priv->base = devfdt_get_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static ulong msm_clk_set_rate(struct clk *clk, ulong rate) +{ + return msm_set_rate(clk, rate); +} + +static struct clk_ops msm_clk_ops = { + .set_rate = msm_clk_set_rate, +}; + +static const struct udevice_id msm_clk_ids[] = { + { .compatible = "qcom,gcc-ipq4019" }, + { } +}; + +U_BOOT_DRIVER(clk_msm) = { + .name = "clk_msm", + .id = UCLASS_CLK, + .of_match = msm_clk_ids, + .ops = &msm_clk_ops, + .priv_auto_alloc_size = sizeof(struct msm_clk_priv), + .probe = msm_clk_probe, +}; diff --git a/arch/arm/mach-ipq40xx/include/mach/gpio.h b/arch/arm/mach-ipq40xx/include/mach/gpio.h new file mode 100644 index 0000000000..a45747c0fe --- /dev/null +++ b/arch/arm/mach-ipq40xx/include/mach/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Empty gpio.h + * + * This file must stay as arch/arm/include/asm/gpio.h requires it. + * + * Copyright (c) 2019 Sartura Ltd. + * + * Author: Robert Marko <robert.marko@sartura.hr> + */ diff --git a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c b/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c new file mode 100644 index 0000000000..06a57f2e5e --- /dev/null +++ b/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm IPQ40xx pinctrl + * + * Copyright (c) 2019 Sartura Ltd. + * + * Author: Robert Marko <robert.marko@sartura.hr> + */ + +#include "pinctrl-snapdragon.h" +#include <common.h> + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN]; + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"gpio", 0}, + {"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */ + {"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */ + {"blsp_uart1", 1}, +}; + +static const char *ipq4019_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *ipq4019_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; +} + +static unsigned int ipq4019_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data ipq4019_data = { + .pin_count = 100, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = ipq4019_get_function_name, + .get_function_mux = ipq4019_get_function_mux, + .get_pin_name = ipq4019_get_pin_name, +}; diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c new file mode 100644 index 0000000000..64b8b049fa --- /dev/null +++ b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TLMM driver for Qualcomm IPQ40xx + * + * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com> + * + * Copyright (c) 2020 Sartura Ltd. + * + * Author: Robert Marko <robert.marko@sartura.hr> + * + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <dm/pinctrl.h> +#include <linux/bitops.h> +#include "pinctrl-snapdragon.h" + +struct msm_pinctrl_priv { + phys_addr_t base; + struct msm_pinctrl_data *data; +}; + +#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) +#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) +#define TLMM_GPIO_DISABLE BIT(9) + +static const struct pinconf_param msm_conf_params[] = { + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 2 }, +}; + +static int msm_get_functions_count(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->functions_count; +} + +static int msm_get_pins_count(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->pin_count; +} + +static const char *msm_get_function_name(struct udevice *dev, + unsigned int selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->get_function_name(dev, selector); +} + +static int msm_pinctrl_probe(struct udevice *dev) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + priv->base = devfdt_get_addr(dev); + priv->data = (struct msm_pinctrl_data *)dev->driver_data; + + return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; +} + +static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + return priv->data->get_pin_name(dev, selector); +} + +static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, + unsigned int func_selector) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, + priv->data->get_function_mux(func_selector) << 2); + return 0; +} + +static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, + unsigned int param, unsigned int argument) +{ + struct msm_pinctrl_priv *priv = dev_get_priv(dev); + + switch (param) { + case PIN_CONFIG_DRIVE_STRENGTH: + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_DRV_STRENGTH_MASK, argument << 6); + break; + case PIN_CONFIG_BIAS_DISABLE: + clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_GPIO_PULL_MASK); + break; + case PIN_CONFIG_BIAS_PULL_UP: + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_GPIO_PULL_MASK, argument); + break; + default: + return 0; + } + + return 0; +} + +static struct pinctrl_ops msm_pinctrl_ops = { + .get_pins_count = msm_get_pins_count, + .get_pin_name = msm_get_pin_name, + .set_state = pinctrl_generic_set_state, + .pinmux_set = msm_pinmux_set, + .pinconf_num_params = ARRAY_SIZE(msm_conf_params), + .pinconf_params = msm_conf_params, + .pinconf_set = msm_pinconf_set, + .get_functions_count = msm_get_functions_count, + .get_function_name = msm_get_function_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,tlmm-ipq4019", .data = (ulong)&ipq4019_data }, + { } +}; + +U_BOOT_DRIVER(pinctrl_snapdraon) = { + .name = "pinctrl_msm", + .id = UCLASS_PINCTRL, + .of_match = msm_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv), + .ops = &msm_pinctrl_ops, + .probe = msm_pinctrl_probe, +}; diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h new file mode 100644 index 0000000000..2341a71349 --- /dev/null +++ b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm Pin control + * + * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com> + * + */ +#ifndef _PINCTRL_SNAPDRAGON_H +#define _PINCTRL_SNAPDRAGON_H + +#include <common.h> + +struct msm_pinctrl_data { + int pin_count; + int functions_count; + const char *(*get_function_name)(struct udevice *dev, + unsigned int selector); + unsigned int (*get_function_mux)(unsigned int selector); + const char *(*get_pin_name)(struct udevice *dev, + unsigned int selector); +}; + +struct pinctrl_function { + const char *name; + int val; +}; + +extern struct msm_pinctrl_data ipq4019_data; + +#endif diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 63bf060616..4335f2877b 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -25,6 +25,7 @@ #include <fs.h> #include <env.h> #include <elf.h> +#include <soc.h> struct ti_sci_handle *get_ti_sci_handle(void) { @@ -308,38 +309,27 @@ void reset_cpu(ulong ignored) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - u32 soc, rev; - char *name; - - soc = (readl(CTRLMMR_WKUP_JTAG_ID) & - JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; - rev = (readl(CTRLMMR_WKUP_JTAG_ID) & - JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT; + struct udevice *soc; + char name[64]; + int ret; printf("SoC: "); - switch (soc) { - case AM65X: - name = "AM65x"; - break; - case J721E: - name = "J721E"; - break; - default: - name = "Unknown Silicon"; - }; - printf("%s SR ", name); - switch (rev) { - case REV_PG1_0: - name = "1.0"; - break; - case REV_PG2_0: - name = "2.0"; - break; - default: - name = "Unknown Revision"; - }; - printf("%s\n", name); + ret = soc_get(&soc); + if (ret) { + printf("UNKNOWN\n"); + return 0; + } + + ret = soc_get_family(soc, name, 64); + if (!ret) { + printf("%s ", name); + } + + ret = soc_get_revision(soc, name, 64); + if (!ret) { + printf("%s\n", name); + } return 0; } diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 94cdcb56ad..ba344c5bc9 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -8,12 +8,6 @@ #include <asm/armv7_mpu.h> -#define AM65X 0xbb5a -#define J721E 0xbb64 - -#define REV_PG1_0 0 -#define REV_PG2_0 1 - struct fwl_data { const char *name; u16 fwl_id; diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk index f7afef610c..c9538718e7 100644 --- a/arch/arm/mach-k3/config.mk +++ b/arch/arm/mach-k3/config.mk @@ -44,7 +44,7 @@ tiboot3.bin: image_check FORCE $(srctree)/tools/k3_gen_x509_cert.sh -c 16 -b $(obj)/u-boot-spl.bin \ -o $@ -l $(CONFIG_SPL_TEXT_BASE) -k $(KEY) -ALL-y += tiboot3.bin +INPUTS-y += tiboot3.bin endif ifdef CONFIG_ARM64 @@ -52,10 +52,10 @@ ifdef CONFIG_ARM64 ifeq ($(CONFIG_TI_SECURE_DEVICE),y) SPL_ITS := u-boot-spl-k3_HS.its $(SPL_ITS): export IS_HS=1 -ALL-y += tispl.bin_HS +INPUTS-y += tispl.bin_HS else SPL_ITS := u-boot-spl-k3.its -ALL-y += tispl.bin +INPUTS-y += tispl.bin endif quiet_cmd_k3_mkits = MKITS $@ @@ -70,9 +70,9 @@ endif else ifeq ($(CONFIG_TI_SECURE_DEVICE),y) -ALL-y += u-boot.img_HS +INPUTS-y += u-boot.img_HS else -ALL-y += u-boot.img +INPUTS-y += u-boot.img endif endif diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 0ad761418b..f2ca80af1a 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -15,7 +15,6 @@ #endif /* Assuming these addresses and definitions stay common across K3 devices */ -#define CTRLMMR_WKUP_JTAG_ID 0x43000014 #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) #define JTAG_ID_PARTNO_SHIFT 12 diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index 513be09c68..96be069ee8 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <dm.h> #include <image.h> #include <log.h> #include <spl.h> diff --git a/arch/arm/mach-keystone/config.mk b/arch/arm/mach-keystone/config.mk index 5806f8f5d1..5a16891f23 100644 --- a/arch/arm/mach-keystone/config.mk +++ b/arch/arm/mach-keystone/config.mk @@ -9,9 +9,9 @@ include $(srctree)/arch/arm/mach-omap2/config_secure.mk ifndef CONFIG_SPL_BUILD ifeq ($(CONFIG_TI_SECURE_DEVICE),y) -ALL-y += u-boot_HS_MLO +INPUTS-y += u-boot_HS_MLO else -ALL-y += MLO +INPUTS-y += MLO endif endif diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index b6cf629c4f..beedc125b6 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -60,7 +60,6 @@ #ifdef CONFIG_CMD_NET #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ #endif /* CONFIG_CMD_NET */ diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index bbcfcfd141..02a5b88015 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -52,7 +52,6 @@ * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ #define CONFIG_ARP_TIMEOUT 200 #define CONFIG_NET_RETRY_COUNT 50 #endif /* CONFIG_CMD_NET */ diff --git a/arch/arm/mach-nexell/Kconfig b/arch/arm/mach-nexell/Kconfig new file mode 100644 index 0000000000..ffa4d4865a --- /dev/null +++ b/arch/arm/mach-nexell/Kconfig @@ -0,0 +1,58 @@ +if ARCH_NEXELL + +config ARCH_S5P4418 + bool "Nexell S5P4418 SoC" + select CPU_V7A + select OF_CONTROL + select OF_SEPARATE + select NX_GPIO + select PL011_SERIAL + select PL011_SERIAL_FLUSH_ON_INIT + help + Enable support for Nexell S5P4418 SoC. + +config ARCH_S5P6818 + bool "Nexell S5P6818 SoC" + select ARM64 + select ARMV8_MULTIENTRY + help + Enable support for Nexell S5P6818 SoC. + +menu "Nexell S5P4418/S5P6818" + depends on ARCH_NEXELL + +choice + prompt "Nexell S5P4418/S5P6818 board select" + optional + +config TARGET_NANOPI2 + bool "FriendlyARM NanoPi2 / NanoPC-T2 Board" + select ARCH_S5P4418 + help + Enable support for FriendlyARM NanoPi2 and NanoPC-T2 Boards. + +endchoice + +config SYS_BOARD + default "nanopi2" + +config SYS_VENDOR + default "friendlyarm" + +config SYS_SOC + default "nexell" + +config SYS_CONFIG_NAME + default "s5p4418_nanopi2" + +endmenu + +config SYS_PLLFIN + int + +config TIMER_SYS_TICK_CH + int + +source "board/friendlyarm/Kconfig" + +endif diff --git a/arch/arm/mach-nexell/Makefile b/arch/arm/mach-nexell/Makefile new file mode 100644 index 0000000000..10b3963ed1 --- /dev/null +++ b/arch/arm/mach-nexell/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 Nexell +# Hyunseok, Jung <hsjung@nexell.co.kr> + +obj-y += clock.o +obj-y += timer.o +obj-y += reset.o +obj-y += nx_gpio.o +obj-y += tieoff.o +obj-$(CONFIG_ARCH_S5P4418) += reg-call.o +obj-$(CONFIG_ARCH_S5P4418) += nx_sec_reg.o +obj-$(CONFIG_CMD_BOOTL) += cmd_boot_linux.o diff --git a/arch/arm/mach-nexell/clock.c b/arch/arm/mach-nexell/clock.c new file mode 100644 index 0000000000..a0ba2d8e0c --- /dev/null +++ b/arch/arm/mach-nexell/clock.c @@ -0,0 +1,869 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Nexell + * Hyunseok, Jung <hsjung@nexell.co.kr> + */ + +#include <common.h> +#include <command.h> +#include <linux/err.h> +#include <asm/io.h> +#include <asm/arch/nexell.h> +#include <asm/arch/clk.h> + +/* + * clock generator macros + */ +#define I_PLL0_BIT (0) +#define I_PLL1_BIT (1) +#define I_PLL2_BIT (2) +#define I_PLL3_BIT (3) +#define I_EXT1_BIT (4) +#define I_EXT2_BIT (5) +#define I_CLKn_BIT (7) +#define I_EXT1_BIT_FORCE (8) +#define I_EXT2_BIT_FORCE (9) + +#define I_CLOCK_NUM 6 /* PLL0, PLL1, PLL2, PLL3, EXT1, EXT2 */ + +#define I_EXECEPT_CLK (0) +#define I_CLOCK_MASK (((1 << I_CLOCK_NUM) - 1) & ~I_EXECEPT_CLK) + +#define I_PLL0 (1 << I_PLL0_BIT) +#define I_PLL1 (1 << I_PLL1_BIT) +#define I_PLL2 (1 << I_PLL2_BIT) +#define I_PLL3 (1 << I_PLL3_BIT) +#define I_EXTCLK1 (1 << I_EXT1_BIT) +#define I_EXTCLK2 (1 << I_EXT2_BIT) +#define I_EXTCLK1_FORCE (1 << I_EXT1_BIT_FORCE) +#define I_EXTCLK2_FORCE (1 << I_EXT2_BIT_FORCE) + +#define I_PLL_0_1 (I_PLL0 | I_PLL1) +#define I_PLL_0_2 (I_PLL_0_1 | I_PLL2) +#define I_PLL_0_3 (I_PLL_0_2 | I_PLL3) +#define I_CLKnOUT (0) + +#define I_PCLK (1 << 16) +#define I_BCLK (1 << 17) +#define I_GATE_PCLK (1 << 20) +#define I_GATE_BCLK (1 << 21) +#define I_PCLK_MASK (I_GATE_PCLK | I_PCLK) +#define I_BCLK_MASK (I_GATE_BCLK | I_BCLK) + +struct clk_dev_peri { + const char *dev_name; + void __iomem *base; + int dev_id; + int periph_id; + int clk_step; + u32 in_mask; + u32 in_mask1; + int div_src_0; + int div_val_0; + int invert_0; + int div_src_1; + int div_val_1; + int invert_1; + int in_extclk_1; + int in_extclk_2; +}; + +struct clk_dev { + struct clk clk; + struct clk *link; + const char *name; + struct clk_dev_peri *peri; +}; + +struct clk_dev_map { + unsigned int con_enb; + unsigned int con_gen[4]; +}; + +#define CLK_PERI_1S(name, devid, id, addr, mk)[id] = \ + { .dev_name = name, .dev_id = devid, .periph_id = id, .clk_step = 1, \ + .base = (void *)addr, .in_mask = mk, } + +#define CLK_PERI_2S(name, devid, id, addr, mk, mk2)[id] = \ + { .dev_name = name, .dev_id = devid, .periph_id = id, .clk_step = 2, \ + .base = (void *)addr, .in_mask = mk, .in_mask1 = mk2, } + +static const char * const clk_core[] = { + CORECLK_NAME_PLL0, CORECLK_NAME_PLL1, CORECLK_NAME_PLL2, + CORECLK_NAME_PLL3, CORECLK_NAME_FCLK, CORECLK_NAME_MCLK, + CORECLK_NAME_BCLK, CORECLK_NAME_PCLK, CORECLK_NAME_HCLK, +}; + +/* + * Section ".data" must be used because BSS is not available before relocation, + * in board_init_f(), respectively! I.e. global variables can not be used! + */ +static struct clk_dev_peri clk_periphs[] + __attribute__((section(".data"))) = { + CLK_PERI_1S(DEV_NAME_TIMER, 0, CLK_ID_TIMER_0, + PHY_BASEADDR_CLKGEN14, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_TIMER, 1, CLK_ID_TIMER_1, + PHY_BASEADDR_CLKGEN0, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_TIMER, 2, CLK_ID_TIMER_2, + PHY_BASEADDR_CLKGEN1, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_TIMER, 3, CLK_ID_TIMER_3, + PHY_BASEADDR_CLKGEN2, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_UART, 0, CLK_ID_UART_0, + PHY_BASEADDR_CLKGEN22, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_UART, 1, CLK_ID_UART_1, + PHY_BASEADDR_CLKGEN24, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_UART, 2, CLK_ID_UART_2, + PHY_BASEADDR_CLKGEN23, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_UART, 3, CLK_ID_UART_3, + PHY_BASEADDR_CLKGEN25, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_UART, 4, CLK_ID_UART_4, + PHY_BASEADDR_CLKGEN26, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_UART, 5, CLK_ID_UART_5, + PHY_BASEADDR_CLKGEN27, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_PWM, 0, CLK_ID_PWM_0, + PHY_BASEADDR_CLKGEN13, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_PWM, 1, CLK_ID_PWM_1, + PHY_BASEADDR_CLKGEN3, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_PWM, 2, CLK_ID_PWM_2, + PHY_BASEADDR_CLKGEN4, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_PWM, 3, CLK_ID_PWM_3, + PHY_BASEADDR_CLKGEN5, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_I2C, 0, CLK_ID_I2C_0, + PHY_BASEADDR_CLKGEN6, (I_GATE_PCLK)), + CLK_PERI_1S(DEV_NAME_I2C, 1, CLK_ID_I2C_1, + PHY_BASEADDR_CLKGEN7, (I_GATE_PCLK)), + CLK_PERI_1S(DEV_NAME_I2C, 2, CLK_ID_I2C_2, + PHY_BASEADDR_CLKGEN8, (I_GATE_PCLK)), + CLK_PERI_2S(DEV_NAME_GMAC, 0, CLK_ID_GMAC, + PHY_BASEADDR_CLKGEN10, + (I_PLL_0_3 | I_EXTCLK1 | I_EXTCLK1_FORCE), + (I_CLKnOUT)), + CLK_PERI_2S(DEV_NAME_I2S, 0, CLK_ID_I2S_0, + PHY_BASEADDR_CLKGEN15, (I_PLL_0_3 | I_EXTCLK1), + (I_CLKnOUT)), + CLK_PERI_2S(DEV_NAME_I2S, 1, CLK_ID_I2S_1, + PHY_BASEADDR_CLKGEN16, (I_PLL_0_3 | I_EXTCLK1), + (I_CLKnOUT)), + CLK_PERI_2S(DEV_NAME_I2S, 2, CLK_ID_I2S_2, + PHY_BASEADDR_CLKGEN17, (I_PLL_0_3 | I_EXTCLK1), + (I_CLKnOUT)), + CLK_PERI_1S(DEV_NAME_SDHC, 0, CLK_ID_SDHC_0, + PHY_BASEADDR_CLKGEN18, (I_PLL_0_2 | I_GATE_PCLK)), + CLK_PERI_1S(DEV_NAME_SDHC, 1, CLK_ID_SDHC_1, + PHY_BASEADDR_CLKGEN19, (I_PLL_0_2 | I_GATE_PCLK)), + CLK_PERI_1S(DEV_NAME_SDHC, 2, CLK_ID_SDHC_2, + PHY_BASEADDR_CLKGEN20, (I_PLL_0_2 | I_GATE_PCLK)), + CLK_PERI_1S(DEV_NAME_SPI, 0, CLK_ID_SPI_0, + PHY_BASEADDR_CLKGEN37, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_SPI, 1, CLK_ID_SPI_1, + PHY_BASEADDR_CLKGEN38, (I_PLL_0_2)), + CLK_PERI_1S(DEV_NAME_SPI, 2, CLK_ID_SPI_2, + PHY_BASEADDR_CLKGEN39, (I_PLL_0_2)), +}; + +#define CLK_PERI_NUM ((int)ARRAY_SIZE(clk_periphs)) +#define CLK_CORE_NUM ((int)ARRAY_SIZE(clk_core)) +#define CLK_DEVS_NUM (CLK_CORE_NUM + CLK_PERI_NUM) +#define MAX_DIVIDER ((1 << 8) - 1) /* 256, align 2 */ + +static struct clk_dev st_clk_devs[CLK_DEVS_NUM] + __attribute__((section(".data"))); +#define clk_dev_get(n) ((struct clk_dev *)&st_clk_devs[n]) +#define clk_container(p) (container_of(p, struct clk_dev, clk)) + +/* + * Core frequencys + */ +struct _core_hz_ { + unsigned long pll[4]; /* PLL */ + unsigned long cpu_fclk, cpu_bclk; /* cpu */ + unsigned long mem_fclk, mem_dclk, mem_bclk, mem_pclk; /* ddr */ + unsigned long bus_bclk, bus_pclk; /* bus */ +#if defined(CONFIG_ARCH_S5P6818) + unsigned long cci4_bclk, cci4_pclk; /* cci */ +#endif + /* ip */ + unsigned long g3d_bclk; + unsigned long coda_bclk, coda_pclk; +#if defined(CONFIG_ARCH_S5P6818) + unsigned long disp_bclk, disp_pclk; + unsigned long hdmi_pclk; +#endif +}; + +/* + * Section ".data" must be used because BSS is not available before relocation, + * in board_init_f(), respectively! I.e. global variables can not be used! + */ +/* core clock */ +static struct _core_hz_ core_hz __attribute__((section(".data"))); + +#define CORE_HZ_SIZE (sizeof(core_hz) / 4) + +/* + * CLKGEN HW + */ +static inline void clk_dev_bclk(void *base, int on) +{ + struct clk_dev_map *reg = base; + unsigned int val = readl(®->con_enb) & ~(0x3); + + val |= (on ? 3 : 0) & 0x3; /* always BCLK */ + writel(val, ®->con_enb); +} + +static inline void clk_dev_pclk(void *base, int on) +{ + struct clk_dev_map *reg = base; + unsigned int val = 0; + + if (!on) + return; + + val = readl(®->con_enb) & ~(1 << 3); + val |= (1 << 3); + writel(val, ®->con_enb); +} + +static inline void clk_dev_rate(void *base, int step, int src, int div) +{ + struct clk_dev_map *reg = base; + unsigned int val = 0; + + val = readl(®->con_gen[step << 1]); + val &= ~(0x07 << 2); + val |= (src << 2); /* source */ + val &= ~(0xFF << 5); + val |= (div - 1) << 5; /* divider */ + writel(val, ®->con_gen[step << 1]); +} + +static inline void clk_dev_inv(void *base, int step, int inv) +{ + struct clk_dev_map *reg = base; + unsigned int val = readl(®->con_gen[step << 1]) & ~(1 << 1); + + val |= (inv << 1); + writel(val, ®->con_gen[step << 1]); +} + +static inline void clk_dev_enb(void *base, int on) +{ + struct clk_dev_map *reg = base; + unsigned int val = readl(®->con_enb) & ~(1 << 2); + + val |= ((on ? 1 : 0) << 2); + writel(val, ®->con_enb); +} + +/* + * CORE FREQUENCY + * + * PLL0 [P,M,S] ------- | | ----- [DIV0] --- CPU-G0 + * |M| ----- [DIV1] --- BCLK/PCLK + * PLL1 [P,M,S] ------- | | ----- [DIV2] --- DDR + * |U| ----- [DIV3] --- 3D + * PLL2 [P,M,S,K]-------| | ----- [DIV4] --- CODA + * |X| ----- [DIV5] --- DISPLAY + * PLL3 [P,M,S,K]-------| | ----- [DIV6] --- HDMI + * | | ----- [DIV7] --- CPU-G1 + * | | ----- [DIV8] --- CCI-400(FASTBUS) + * + */ + +struct nx_clkpwr_registerset { + u32 clkmodereg0; /* 0x000 : Clock Mode Register0 */ + u32 __reserved0; /* 0x004 */ + u32 pllsetreg[4]; /* 0x008 ~ 0x014 : PLL Setting Register */ + u32 __reserved1[2]; /* 0x018 ~ 0x01C */ + u32 dvoreg[9]; /* 0x020 ~ 0x040 : Divider Setting Register */ + u32 __Reserved2; /* 0x044 */ + u32 pllsetreg_sscg[6]; /* 0x048 ~ 0x05C */ + u32 __reserved3[8]; /* 0x060 ~ 0x07C */ + u8 __reserved4[0x200 - 0x80]; /* padding (0x80 ~ 0x1FF) */ + u32 gpiowakeupriseenb; /* 0x200 : GPIO Rising Edge Detect En. Reg. */ + u32 gpiowakeupfallenb; /* 0x204 : GPIO Falling Edge Detect En. Reg. */ + u32 gpiorstenb; /* 0x208 : GPIO Reset Enable Register */ + u32 gpiowakeupenb; /* 0x20C : GPIO Wakeup Source Enable */ + u32 gpiointenb; /* 0x210 : Interrupt Enable Register */ + u32 gpiointpend; /* 0x214 : Interrupt Pend Register */ + u32 resetstatus; /* 0x218 : Reset Status Register */ + u32 intenable; /* 0x21C : Interrupt Enable Register */ + u32 intpend; /* 0x220 : Interrupt Pend Register */ + u32 pwrcont; /* 0x224 : Power Control Register */ + u32 pwrmode; /* 0x228 : Power Mode Register */ + u32 __reserved5; /* 0x22C : Reserved Region */ + u32 scratch[3]; /* 0x230 ~ 0x238 : Scratch Register */ + u32 sysrstconfig; /* 0x23C : System Reset Configuration Reg. */ + u8 __reserved6[0x2A0 - 0x240]; /* padding (0x240 ~ 0x29F) */ + u32 cpupowerdownreq; /* 0x2A0 : CPU Power Down Request Register */ + u32 cpupoweronreq; /* 0x2A4 : CPU Power On Request Register */ + u32 cpuresetmode; /* 0x2A8 : CPU Reset Mode Register */ + u32 cpuwarmresetreq; /* 0x2AC : CPU Warm Reset Request Register */ + u32 __reserved7; /* 0x2B0 */ + u32 cpustatus; /* 0x2B4 : CPU Status Register */ + u8 __reserved8[0x400 - 0x2B8]; /* padding (0x2B8 ~ 0x33F) */ +}; + +static struct nx_clkpwr_registerset * const clkpwr = + (struct nx_clkpwr_registerset *)PHY_BASEADDR_CLKPWR; + +#define getquotient(v, d) ((v) / (d)) + +#define DIV_CPUG0 0 +#define DIV_BUS 1 +#define DIV_MEM 2 +#define DIV_G3D 3 +#define DIV_CODA 4 +#if defined(CONFIG_ARCH_S5P6818) +#define DIV_DISP 5 +#define DIV_HDMI 6 +#define DIV_CPUG1 7 +#define DIV_CCI4 8 +#endif + +#define DVO0 3 +#define DVO1 9 +#define DVO2 15 +#define DVO3 21 + +static unsigned int pll_rate(unsigned int plln, unsigned int xtal) +{ + unsigned int val, val1, nP, nM, nS, nK; + unsigned int temp = 0; + + val = clkpwr->pllsetreg[plln]; + val1 = clkpwr->pllsetreg_sscg[plln]; + xtal /= 1000; /* Unit Khz */ + + nP = (val >> 18) & 0x03F; + nM = (val >> 8) & 0x3FF; + nS = (val >> 0) & 0x0FF; + nK = (val1 >> 16) & 0xFFFF; + + if (plln > 1 && nK) { + temp = (unsigned int)(getquotient((getquotient((nK * 1000), + 65536) * xtal), nP) >> nS); + } + + temp = (unsigned int)((getquotient((nM * xtal), nP) >> nS) * 1000) + + temp; + return temp; +} + +static unsigned int pll_dvo(int dvo) +{ + unsigned int val; + + val = (clkpwr->dvoreg[dvo] & 0x7); + return val; +} + +static unsigned int pll_div(int dvo) +{ + unsigned int val = clkpwr->dvoreg[dvo]; + + return ((((val >> DVO3) & 0x3F) + 1) << 24) | + ((((val >> DVO2) & 0x3F) + 1) << 16) | + ((((val >> DVO1) & 0x3F) + 1) << 8) | + ((((val >> DVO0) & 0x3F) + 1) << 0); +} + +#define PLLN_RATE(n) (pll_rate(n, CONFIG_SYS_PLLFIN)) /* 0~ 3 */ +#define CPU_FCLK_RATE(n) (pll_rate(pll_dvo(n), CONFIG_SYS_PLLFIN) / \ + ((pll_div(n) >> 0) & 0x3F)) +#define CPU_BCLK_RATE(n) (pll_rate(pll_dvo(n), CONFIG_SYS_PLLFIN) / \ + ((pll_div(n) >> 0) & 0x3F) / \ + ((pll_div(n) >> 8) & 0x3F)) + +#define MEM_FCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_MEM) >> 0) & 0x3F) / \ + ((pll_div(DIV_MEM) >> 8) & 0x3F)) + +#define MEM_DCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_MEM) >> 0) & 0x3F)) + +#define MEM_BCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_MEM) >> 0) & 0x3F) / \ + ((pll_div(DIV_MEM) >> 8) & 0x3F) / \ + ((pll_div(DIV_MEM) >> 16) & 0x3F)) +#define MEM_PCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_MEM) >> 0) & 0x3F) / \ + ((pll_div(DIV_MEM) >> 8) & 0x3F) / \ + ((pll_div(DIV_MEM) >> 16) & 0x3F) / \ + ((pll_div(DIV_MEM) >> 24) & 0x3F)) + +#define BUS_BCLK_RATE() (pll_rate(pll_dvo(DIV_BUS), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_BUS) >> 0) & 0x3F)) +#define BUS_PCLK_RATE() (pll_rate(pll_dvo(DIV_BUS), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_BUS) >> 0) & 0x3F) / \ + ((pll_div(DIV_BUS) >> 8) & 0x3F)) + +#define G3D_BCLK_RATE() (pll_rate(pll_dvo(DIV_G3D), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_G3D) >> 0) & 0x3F)) + +#define MPG_BCLK_RATE() (pll_rate(pll_dvo(DIV_CODA), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_CODA) >> 0) & 0x3F)) +#define MPG_PCLK_RATE() (pll_rate(pll_dvo(DIV_CODA), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_CODA) >> 0) & 0x3F) / \ + ((pll_div(DIV_CODA) >> 8) & 0x3F)) + +#if defined(CONFIG_ARCH_S5P6818) +#define DISP_BCLK_RATE() (pll_rate(pll_dvo(DIV_DISP), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_DISP) >> 0) & 0x3F)) +#define DISP_PCLK_RATE() (pll_rate(pll_dvo(DIV_DISP), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_DISP) >> 0) & 0x3F) / \ + ((pll_div(DIV_DISP) >> 8) & 0x3F)) + +#define HDMI_PCLK_RATE() (pll_rate(pll_dvo(DIV_HDMI), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_HDMI) >> 0) & 0x3F)) + +#define CCI4_BCLK_RATE() (pll_rate(pll_dvo(DIV_CCI4), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_CCI4) >> 0) & 0x3F)) +#define CCI4_PCLK_RATE() (pll_rate(pll_dvo(DIV_CCI4), CONFIG_SYS_PLLFIN) / \ + ((pll_div(DIV_CCI4) >> 0) & 0x3F) / \ + ((pll_div(DIV_CCI4) >> 8) & 0x3F)) +#endif + +static void core_update_rate(int type) +{ + switch (type) { + case 0: + core_hz.pll[0] = PLLN_RATE(0); break; + case 1: + core_hz.pll[1] = PLLN_RATE(1); break; + case 2: + core_hz.pll[2] = PLLN_RATE(2); break; + case 3: + core_hz.pll[3] = PLLN_RATE(3); break; + case 4: + core_hz.cpu_fclk = CPU_FCLK_RATE(DIV_CPUG0); break; + case 5: + core_hz.mem_fclk = MEM_FCLK_RATE(); break; + case 6: + core_hz.bus_bclk = BUS_BCLK_RATE(); break; + case 7: + core_hz.bus_pclk = BUS_PCLK_RATE(); break; + case 8: + core_hz.cpu_bclk = CPU_BCLK_RATE(DIV_CPUG0); break; + case 9: + core_hz.mem_dclk = MEM_DCLK_RATE(); break; + case 10: + core_hz.mem_bclk = MEM_BCLK_RATE(); break; + case 11: + core_hz.mem_pclk = MEM_PCLK_RATE(); break; + case 12: + core_hz.g3d_bclk = G3D_BCLK_RATE(); break; + case 13: + core_hz.coda_bclk = MPG_BCLK_RATE(); break; + case 14: + core_hz.coda_pclk = MPG_PCLK_RATE(); break; +#if defined(CONFIG_ARCH_S5P6818) + case 15: + core_hz.disp_bclk = DISP_BCLK_RATE(); break; + case 16: + core_hz.disp_pclk = DISP_PCLK_RATE(); break; + case 17: + core_hz.hdmi_pclk = HDMI_PCLK_RATE(); break; + case 18: + core_hz.cci4_bclk = CCI4_BCLK_RATE(); break; + case 19: + core_hz.cci4_pclk = CCI4_PCLK_RATE(); break; +#endif + }; +} + +static unsigned long core_get_rate(int type) +{ + unsigned long rate = 0; + + switch (type) { + case 0: + rate = core_hz.pll[0]; break; + case 1: + rate = core_hz.pll[1]; break; + case 2: + rate = core_hz.pll[2]; break; + case 3: + rate = core_hz.pll[3]; break; + case 4: + rate = core_hz.cpu_fclk; break; + case 5: + rate = core_hz.mem_fclk; break; + case 6: + rate = core_hz.bus_bclk; break; + case 7: + rate = core_hz.bus_pclk; break; + case 8: + rate = core_hz.cpu_bclk; break; + case 9: + rate = core_hz.mem_dclk; break; + case 10: + rate = core_hz.mem_bclk; break; + case 11: + rate = core_hz.mem_pclk; break; + case 12: + rate = core_hz.g3d_bclk; break; + case 13: + rate = core_hz.coda_bclk; break; + case 14: + rate = core_hz.coda_pclk; break; +#if defined(CONFIG_ARCH_S5P6818) + case 15: + rate = core_hz.disp_bclk; break; + case 16: + rate = core_hz.disp_pclk; break; + case 17: + rate = core_hz.hdmi_pclk; break; + case 18: + rate = core_hz.cci4_bclk; break; + case 19: + rate = core_hz.cci4_pclk; break; +#endif + default: + printf("unknown core clock type %d ...\n", type); + break; + }; + return rate; +} + +static long core_set_rate(struct clk *clk, long rate) +{ + return clk->rate; +} + +static void core_rate_init(void) +{ + int i; + + for (i = 0; i < CORE_HZ_SIZE; i++) + core_update_rate(i); +} + +/* + * Clock Interfaces + */ +static inline long clk_divide(long rate, long request, + int align, int *divide) +{ + int div = (rate / request); + int max = MAX_DIVIDER & ~(align - 1); + int adv = (div & ~(align - 1)) + align; + long ret; + + if (!div) { + if (divide) + *divide = 1; + return rate; + } + + if (div != 1) + div &= ~(align - 1); + + if (div != adv && abs(request - rate / div) > abs(request - rate / adv)) + div = adv; + + div = (div > max ? max : div); + if (divide) + *divide = div; + + ret = rate / div; + return ret; +} + +void clk_put(struct clk *clk) +{ +} + +struct clk *clk_get(const char *id) +{ + struct clk_dev *cdev = clk_dev_get(0); + struct clk *clk = NULL; + const char *str = NULL, *c = NULL; + int i, devid; + + if (id) + str = id; + + for (i = 0; i < CLK_DEVS_NUM; i++, cdev++) { + if (!cdev->name) + continue; + if (!strncmp(cdev->name, str, strlen(cdev->name))) { + c = strrchr((const char *)str, (int)'.'); + if (!c || !cdev->peri) + break; + devid = simple_strtoul(++c, NULL, 10); + if (cdev->peri->dev_id == devid) + break; + } + } + if (i < CLK_DEVS_NUM) + clk = &cdev->clk; + else + clk = &(clk_dev_get(7))->clk; /* pclk */ + + return clk ? clk : ERR_PTR(-ENOENT); +} + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + struct clk_dev *pll = NULL, *cdev = clk_container(clk); + struct clk_dev_peri *peri = cdev->peri; + unsigned long request = rate, rate_hz = 0; + unsigned int mask; + int step, div[2] = { 0, }; + int i, n, clk2 = 0; + int start_src = 0, max_src = I_CLOCK_NUM; + short s1 = 0, s2 = 0, d1 = 0, d2 = 0; + + if (!peri) + return core_set_rate(clk, rate); + + step = peri->clk_step; + mask = peri->in_mask; + debug("clk: %s.%d request = %ld [input=0x%x]\n", peri->dev_name, + peri->dev_id, rate, mask); + + if (!(I_CLOCK_MASK & mask)) { + if (I_PCLK_MASK & mask) + return core_get_rate(CORECLK_ID_PCLK); + else if (I_BCLK_MASK & mask) + return core_get_rate(CORECLK_ID_BCLK); + else + return clk->rate; + } + +next: + if (peri->in_mask & I_EXTCLK1_FORCE) { + start_src = 4; max_src = 5; + } + for (n = start_src ; max_src > n; n++) { + if (!(((mask & I_CLOCK_MASK) >> n) & 0x1)) + continue; + + if (n == I_EXT1_BIT) { + rate = peri->in_extclk_1; + } else if (n == I_EXT2_BIT) { + rate = peri->in_extclk_2; + } else { + pll = clk_dev_get(n); + rate = pll->clk.rate; + } + + if (!rate) + continue; + + for (i = 0; step > i ; i++) + rate = clk_divide(rate, request, 2, &div[i]); + + if (rate_hz && (abs(rate - request) > abs(rate_hz - request))) + continue; + + debug("clk: %s.%d, pll.%d[%lu] request[%ld] calc[%ld]\n", + peri->dev_name, peri->dev_id, n, pll->clk.rate, + request, rate); + + if (clk2) { + s1 = -1, d1 = -1; /* not use */ + s2 = n, d2 = div[0]; + } else { + s1 = n, d1 = div[0]; + s2 = I_CLKn_BIT, d2 = div[1]; + } + rate_hz = rate; + } + + /* search 2th clock from input */ + if (!clk2 && abs(rate_hz - request) && + peri->in_mask1 & ((1 << I_CLOCK_NUM) - 1)) { + clk2 = 1; + mask = peri->in_mask1; + step = 1; + goto next; + } + if (peri->in_mask & I_EXTCLK1_FORCE) { + if (s1 == 0) { + s1 = 4; s2 = 7; + d1 = 1; d2 = 1; + } + } + + peri->div_src_0 = s1, peri->div_val_0 = d1; + peri->div_src_1 = s2, peri->div_val_1 = d2; + clk->rate = rate_hz; + + debug("clk: %s.%d, step[%d] src[%d,%d] %ld", peri->dev_name, + peri->dev_id, peri->clk_step, peri->div_src_0, peri->div_src_1, + rate); + debug("/(div0: %d * div1: %d) = %ld, %ld diff (%ld)\n", + peri->div_val_0, peri->div_val_1, rate_hz, request, + abs(rate_hz - request)); + + return clk->rate; +} + +unsigned long clk_get_rate(struct clk *clk) +{ + struct clk_dev *cdev = clk_container(clk); + + if (cdev->link) + clk = cdev->link; + return clk->rate; +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk_dev *cdev = clk_container(clk); + struct clk_dev_peri *peri = cdev->peri; + int i; + + if (!peri) + return core_set_rate(clk, rate); + + clk_round_rate(clk, rate); + + for (i = 0; peri->clk_step > i ; i++) { + int s = (i == 0 ? peri->div_src_0 : peri->div_src_1); + int d = (i == 0 ? peri->div_val_0 : peri->div_val_1); + + if (-1 == s) + continue; + + clk_dev_rate(peri->base, i, s, d); + + debug("clk: %s.%d (%p) set_rate [%d] src[%d] div[%d]\n", + peri->dev_name, peri->dev_id, peri->base, i, s, d); + } + + return clk->rate; +} + +int clk_enable(struct clk *clk) +{ + struct clk_dev *cdev = clk_container(clk); + struct clk_dev_peri *peri = cdev->peri; + int i = 0, inv = 0; + + if (!peri) + return 0; + + debug("clk: %s.%d enable (BCLK=%s, PCLK=%s)\n", peri->dev_name, + peri->dev_id, I_GATE_BCLK & peri->in_mask ? "ON" : "PASS", + I_GATE_PCLK & peri->in_mask ? "ON" : "PASS"); + + if (!(I_CLOCK_MASK & peri->in_mask)) { + /* Gated BCLK/PCLK enable */ + if (I_GATE_BCLK & peri->in_mask) + clk_dev_bclk(peri->base, 1); + + if (I_GATE_PCLK & peri->in_mask) + clk_dev_pclk(peri->base, 1); + + return 0; + } + + /* invert */ + inv = peri->invert_0; + for (; peri->clk_step > i; i++, inv = peri->invert_1) + clk_dev_inv(peri->base, i, inv); + + /* Gated BCLK/PCLK enable */ + if (I_GATE_BCLK & peri->in_mask) + clk_dev_bclk(peri->base, 1); + + if (I_GATE_PCLK & peri->in_mask) + clk_dev_pclk(peri->base, 1); + + /* restore clock rate */ + for (i = 0; peri->clk_step > i ; i++) { + int s = (i == 0 ? peri->div_src_0 : peri->div_src_1); + int d = (i == 0 ? peri->div_val_0 : peri->div_val_1); + + if (s == -1) + continue; + clk_dev_rate(peri->base, i, s, d); + } + + clk_dev_enb(peri->base, 1); + + return 0; +} + +void clk_disable(struct clk *clk) +{ + struct clk_dev *cdev = clk_container(clk); + struct clk_dev_peri *peri = cdev->peri; + + if (!peri) + return; + + debug("clk: %s.%d disable\n", peri->dev_name, peri->dev_id); + + if (!(I_CLOCK_MASK & peri->in_mask)) { + /* Gated BCLK/PCLK disable */ + if (I_GATE_BCLK & peri->in_mask) + clk_dev_bclk(peri->base, 0); + + if (I_GATE_PCLK & peri->in_mask) + clk_dev_pclk(peri->base, 0); + + return; + } + + clk_dev_rate(peri->base, 0, 7, 256); /* for power save */ + clk_dev_enb(peri->base, 0); + + /* Gated BCLK/PCLK disable */ + if (I_GATE_BCLK & peri->in_mask) + clk_dev_bclk(peri->base, 0); + + if (I_GATE_PCLK & peri->in_mask) + clk_dev_pclk(peri->base, 0); +} + +/* + * Core clocks APIs + */ +void __init clk_init(void) +{ + struct clk_dev *cdev = st_clk_devs; + struct clk_dev_peri *peri = clk_periphs; + struct clk *clk = NULL; + int i = 0; + + memset(cdev, 0, sizeof(st_clk_devs)); + core_rate_init(); + + for (i = 0; (CLK_CORE_NUM + CLK_PERI_NUM) > i; i++, cdev++) { + if (i < CLK_CORE_NUM) { + cdev->name = clk_core[i]; + clk = &cdev->clk; + clk->rate = core_get_rate(i); + continue; + } + + peri = &clk_periphs[i - CLK_CORE_NUM]; + peri->base = (void *)peri->base; + + cdev->peri = peri; + cdev->name = peri->dev_name; + + if (!(I_CLOCK_MASK & peri->in_mask)) { + if (I_BCLK_MASK & peri->in_mask) + cdev->clk.rate = core_get_rate(CORECLK_ID_BCLK); + if (I_PCLK_MASK & peri->in_mask) + cdev->clk.rate = core_get_rate(CORECLK_ID_PCLK); + } + + /* prevent uart clock disable for low step debug message */ + #ifndef CONFIG_DEBUG_NX_UART + if (peri->dev_name) { + #ifdef CONFIG_BACKLIGHT_PWM + if (!strcmp(peri->dev_name, DEV_NAME_PWM)) + continue; + #endif + } + #endif + } + debug("CPU : Clock Generator= %d EA, ", CLK_DEVS_NUM); +} diff --git a/arch/arm/mach-nexell/cmd_boot_linux.c b/arch/arm/mach-nexell/cmd_boot_linux.c new file mode 100644 index 0000000000..f2dedfe162 --- /dev/null +++ b/arch/arm/mach-nexell/cmd_boot_linux.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 nexell + * jhkim <jhkim@nexell.co.kr> + */ + +#include <common.h> +#include <bootm.h> +#include <command.h> +#include <environment.h> +#include <errno.h> +#include <image.h> +#include <fdt_support.h> + +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_CLI_FRAMEWORK) + +DECLARE_GLOBAL_DATA_PTR; + +static bootm_headers_t linux_images; + +static void boot_go_set_os(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[], + bootm_headers_t *images) +{ + char * const img_addr = argv[0]; + + images->os.type = IH_TYPE_KERNEL; + images->os.comp = IH_COMP_NONE; + images->os.os = IH_OS_LINUX; + images->os.load = simple_strtoul(img_addr, NULL, 16); + images->ep = images->os.load; +#if defined(CONFIG_ARM) + images->os.arch = IH_ARCH_ARM; +#elif defined(CONFIG_ARM64) + images->os.arch = IH_ARCH_ARM64; +#else + #error "Not support architecture ..." +#endif + if (!IS_ENABLED(CONFIG_OF_LIBFDT) && !IS_ENABLED(CONFIG_SPL_BUILD)) { + /* set DTB address for linux kernel */ + if (argc > 2) { + unsigned long ft_addr; + + ft_addr = simple_strtol(argv[2], NULL, 16); + images->ft_addr = (char *)ft_addr; + + /* + * if not defined IMAGE_ENABLE_OF_LIBFDT, + * must be set to fdt address + */ + if (!IMAGE_ENABLE_OF_LIBFDT) + gd->bd->bi_boot_params = ft_addr; + + debug("## set ft:%08lx and boot params:%08lx [control of:%s]" + "...\n", ft_addr, gd->bd->bi_boot_params, + IMAGE_ENABLE_OF_LIBFDT ? "on" : "off"); + } + } +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_LMB) +static void boot_start_lmb(bootm_headers_t *images) +{ + ulong mem_start; + phys_size_t mem_size; + + lmb_init(&images->lmb); + + mem_start = getenv_bootm_low(); + mem_size = getenv_bootm_size(); + + lmb_add(&images->lmb, (phys_addr_t)mem_start, mem_size); + + arch_lmb_reserve(&images->lmb); + board_lmb_reserve(&images->lmb); +} +#else +#define lmb_reserve(lmb, base, size) +static inline void boot_start_lmb(bootm_headers_t *images) { } +#endif + +int do_boot_linux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + boot_os_fn *boot_fn; + bootm_headers_t *images = &linux_images; + int flags; + int ret; + + boot_start_lmb(images); + + flags = BOOTM_STATE_START; + + argc--; argv++; + boot_go_set_os(cmdtp, flag, argc, argv, images); + + if (IS_ENABLED(CONFIG_OF_LIBFDT)) { + /* find flattened device tree */ + ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, images, + &images->ft_addr, &images->ft_len); + if (ret) { + puts("Could not find a valid device tree\n"); + return 1; + } + set_working_fdt_addr((ulong)images->ft_addr); + } + + if (!IS_ENABLED(CONFIG_OF_LIBFDT)) + flags |= BOOTM_STATE_OS_GO; + + boot_fn = do_bootm_linux; + ret = boot_fn(flags, argc, argv, images); + + if (ret == BOOTM_ERR_UNIMPLEMENTED) + show_boot_progress(BOOTSTAGE_ID_DECOMP_UNIMPL); + else if (ret == BOOTM_ERR_RESET) + do_reset(cmdtp, flag, argc, argv); + + return ret; +} + +U_BOOT_CMD(bootl, CONFIG_SYS_MAXARGS, 1, do_boot_linux, + "boot linux image from memory", + "[addr [arg ...]]\n - boot linux image stored in memory\n" + "\tuse a '-' for the DTB address\n" +); +#endif + +#if defined(CONFIG_CMD_BOOTD) && !defined(CONFIG_CMD_BOOTM) +int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return run_command(env_get("bootcmd"), flag); +} + +U_BOOT_CMD(boot, 1, 1, do_bootd, + "boot default, i.e., run 'bootcmd'", + "" +); + +/* keep old command name "bootd" for backward compatibility */ +U_BOOT_CMD(bootd, 1, 1, do_bootd, + "boot default, i.e., run 'bootcmd'", + "" +); +#endif diff --git a/arch/arm/mach-nexell/config.mk b/arch/arm/mach-nexell/config.mk new file mode 100644 index 0000000000..7b0662699c --- /dev/null +++ b/arch/arm/mach-nexell/config.mk @@ -0,0 +1,11 @@ +# +# (C) Copyright 2016 Nexell +# junghyun kim<jhkim@nexell.co.kr> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +SOCDIR=CPUDIR/$(VENDOR) +MACHDIR=$(patsubst %,arch/arm/mach-%,$(machine-y)) + +LDPPFLAGS += -DMACHDIR=$(MACHDIR) -DSOCDIR=$(SOCDIR) diff --git a/arch/arm/mach-nexell/include/mach/boot0.h b/arch/arm/mach-nexell/include/mach/boot0.h new file mode 100644 index 0000000000..e05c07ece6 --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/boot0.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * NSIH (Nexell System Information Header) for FriendlyArm nanopi2 board + * + * The NSIH (first 512 Bytes of u-boot.bin) is necessary for the + * 2nd-Bootloader to get information like load address of U-Boot. + * + * 0x400 must be added to CONFIG_SYS_TEXT_BASE to have the actual load and + * start address because 2nd-Bootloader loads with an offset of 0x400 + * (NSIH + 0x200 bytes are not loaded into RAM). + * + * It has been tested / is working with the following 2nd-Bootloader: + * "BL1 by Nexell V1.0.0-gd551e13 [Built on 2018-01-25 16:58:29]" + * + * (C) Copyright 2020 Stefan Bosch <stefan_b@posteo.net> + */ + +#ifndef __BOOT0_H +#define __BOOT0_H + + ARM_VECTORS + .space 0x30 + .word (_end - _start) + 20 * 1024 /* 0x50: load size + * (bin + 20k for DTB) */ + .space 0x4 + .word CONFIG_SYS_TEXT_BASE + 0x400 /* 0x58: load address */ + .word 0x00000000 + .word CONFIG_SYS_TEXT_BASE + 0x400 /* 0x60: start address */ + .space 0x198 + .byte 'N' /* 0x1FC: "NSIH" signature */ + .byte 'S' + .byte 'I' + .byte 'H' + + /* The NSIH + 0x200 bytes are omitted by the 2nd-Bootloader */ + .space 0x200 +_start: + ARM_VECTORS + +#endif /* __BOOT0_H */ diff --git a/arch/arm/mach-nexell/include/mach/clk.h b/arch/arm/mach-nexell/include/mach/clk.h new file mode 100644 index 0000000000..cc5589adea --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/clk.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * (C) Copyright 2016 Nexell + * Hyunseok, Jung <hsjung@nexell.co.kr> + */ + +#ifndef __ASM_ARM_ARCH_CLK_H_ +#define __ASM_ARM_ARCH_CLK_H_ + +struct clk { + unsigned long rate; +}; + +void clk_init(void); + +struct clk *clk_get(const char *id); +void clk_put(struct clk *clk); +unsigned long clk_get_rate(struct clk *clk); +long clk_round_rate(struct clk *clk, unsigned long rate); +int clk_set_rate(struct clk *clk, unsigned long rate); +int clk_enable(struct clk *clk); +void clk_disable(struct clk *clk); + +#endif diff --git a/arch/arm/mach-nexell/include/mach/display.h b/arch/arm/mach-nexell/include/mach/display.h new file mode 100644 index 0000000000..b167e63a5a --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/display.h @@ -0,0 +1,273 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2016 Nexell Co., Ltd. + * + * Author: junghyun, kim <jhkim@nexell.co.kr> + */ + +#ifndef _NX__DISPLAY_H_ +#define _NX__DISPLAY_H_ + +#define DP_PLANS_NUM 3 + +/* the display output format. */ +#define DPC_FORMAT_RGB555 0 /* RGB555 Format */ +#define DPC_FORMAT_RGB565 1 /* RGB565 Format */ +#define DPC_FORMAT_RGB666 2 /* RGB666 Format */ +#define DPC_FORMAT_RGB888 3 /* RGB888 Format */ +#define DPC_FORMAT_MRGB555A 4 /* MRGB555A Format */ +#define DPC_FORMAT_MRGB555B 5 /* MRGB555B Format */ +#define DPC_FORMAT_MRGB565 6 /* MRGB565 Format */ +#define DPC_FORMAT_MRGB666 7 /* MRGB666 Format */ +#define DPC_FORMAT_MRGB888A 8 /* MRGB888A Format */ +#define DPC_FORMAT_MRGB888B 9 /* MRGB888B Format */ +#define DPC_FORMAT_CCIR656 10 /* ITU-R BT.656 / 601(8-bit) */ +#define DPC_FORMAT_CCIR601A 12 /* ITU-R BT.601A */ +#define DPC_FORMAT_CCIR601B 13 /* ITU-R BT.601B */ +#define DPC_FORMAT_4096COLOR 1 /* 4096 Color Format */ +#define DPC_FORMAT_16GRAY 3 /* 16 Level Gray Format */ + +/* layer pixel format. */ +#define MLC_RGBFMT_R5G6B5 0x44320000 /* {R5,G6,B5 }. */ +#define MLC_RGBFMT_B5G6R5 0xC4320000 /* {B5,G6,R5 }. */ +#define MLC_RGBFMT_X1R5G5B5 0x43420000 /* {X1,R5,G5,B5}. */ +#define MLC_RGBFMT_X1B5G5R5 0xC3420000 /* {X1,B5,G5,R5}. */ +#define MLC_RGBFMT_X4R4G4B4 0x42110000 /* {X4,R4,G4,B4}. */ +#define MLC_RGBFMT_X4B4G4R4 0xC2110000 /* {X4,B4,G4,R4}. */ +#define MLC_RGBFMT_X8R3G3B2 0x41200000 /* {X8,R3,G3,B2}. */ +#define MLC_RGBFMT_X8B3G3R2 0xC1200000 /* {X8,B3,G3,R2}. */ +#define MLC_RGBFMT_A1R5G5B5 0x33420000 /* {A1,R5,G5,B5}. */ +#define MLC_RGBFMT_A1B5G5R5 0xB3420000 /* {A1,B5,G5,R5}. */ +#define MLC_RGBFMT_A4R4G4B4 0x22110000 /* {A4,R4,G4,B4}. */ +#define MLC_RGBFMT_A4B4G4R4 0xA2110000 /* {A4,B4,G4,R4}. */ +#define MLC_RGBFMT_A8R3G3B2 0x11200000 /* {A8,R3,G3,B2}. */ +#define MLC_RGBFMT_A8B3G3R2 0x91200000 /* {A8,B3,G3,R2}. */ +#define MLC_RGBFMT_R8G8B8 0x46530000 /* {R8,G8,B8 }. */ +#define MLC_RGBFMT_B8G8R8 0xC6530000 /* {B8,G8,R8 }. */ +#define MLC_RGBFMT_X8R8G8B8 0x46530000 /* {X8,R8,G8,B8}. */ +#define MLC_RGBFMT_X8B8G8R8 0xC6530000 /* {X8,B8,G8,R8}. */ +#define MLC_RGBFMT_A8R8G8B8 0x06530000 /* {A8,R8,G8,B8}. */ +#define MLC_RGBFMT_A8B8G8R8 0x86530000 /* {A8,B8,G8,R8}. */ + +/* the data output order in case of ITU-R BT.656 / 601. */ +#define DPC_YCORDER_CBYCRY 0 +#define DPC_YCORDER_CRYCBY 1 +#define DPC_YCORDER_YCBYCR 2 +#define DPC_YCORDER_YCRYCB 3 + +/* the PAD output clock. */ +#define DPC_PADCLKSEL_VCLK 0 /* VCLK */ +#define DPC_PADCLKSEL_VCLK2 1 /* VCLK2 */ + +/* display sync info for DPC */ +struct dp_sync_info { + int interlace; + int h_active_len; + int h_sync_width; + int h_back_porch; + int h_front_porch; + int h_sync_invert; /* default active low */ + int v_active_len; + int v_sync_width; + int v_back_porch; + int v_front_porch; + int v_sync_invert; /* default active low */ + int pixel_clock_hz; /* HZ */ +}; + +/* syncgen control (DPC) */ +#define DP_SYNC_DELAY_RGB_PVD (1 << 0) +#define DP_SYNC_DELAY_HSYNC_CP1 (1 << 1) +#define DP_SYNC_DELAY_VSYNC_FRAM (1 << 2) +#define DP_SYNC_DELAY_DE_CP (1 << 3) + +struct dp_ctrl_info { + /* clock gen */ + int clk_src_lv0; + int clk_div_lv0; + int clk_src_lv1; + int clk_div_lv1; + /* scan format */ + int interlace; + /* syncgen format */ + unsigned int out_format; + int invert_field; /* 0:normal(Low odd), 1:invert (low even) */ + int swap_RB; + unsigned int yc_order; /* for CCIR output */ + /* extern sync delay */ + int delay_mask; /* if 0, set defalut delays */ + int d_rgb_pvd; /* delay for RGB/PVD, 0~16, default 0 */ + int d_hsync_cp1; /* delay for HSYNC/CP1, 0~63, default 12 */ + int d_vsync_fram; /* delay for VSYNC/FRAM, 0~63, default 12 */ + int d_de_cp2; /* delay for DE/CP2, 0~63, default 12 */ + /* sync offset */ + int vs_start_offset; /* start vsync offset, defatult 0 */ + int vs_end_offset; /* end vsync offset, default 0 */ + int ev_start_offset; /* start even vsync offset, default 0 */ + int ev_end_offset; /* end even vsync offset , default 0 */ + /* pad clock seletor */ + int vck_select; /* 0=vclk0, 1=vclk2 */ + int clk_inv_lv0; /* OUTCLKINVn */ + int clk_delay_lv0; /* OUTCLKDELAYn */ + int clk_inv_lv1; /* OUTCLKINVn */ + int clk_delay_lv1; /* OUTCLKDELAYn */ + int clk_sel_div1; /* 0=clk1_inv, 1=clk1_div_2_ns */ +}; + +/* multi layer control (MLC) */ +struct dp_plane_top { + int screen_width; + int screen_height; + int video_prior; /* 0: video>RGBn, 1: RGB0>video>RGB1, + * 2: RGB0 > RGB1 > video .. */ + int interlace; + int plane_num; + unsigned int back_color; +}; + +struct dp_plane_info { + int layer; + unsigned int fb_base; + int left; + int top; + int width; + int height; + int pixel_byte; + unsigned int format; + int alpha_on; + int alpha_depth; + int tp_on; /* transparency color enable */ + unsigned int tp_color; + unsigned int mem_lock_size; /* memory burst access (4,8,16) */ + int video_layer; + int enable; +}; + +/* + * LCD device dependency struct + * RGB, LVDS, MiPi, HDMI + */ +enum { + DP_DEVICE_RESCONV = 0, + DP_DEVICE_RGBLCD = 1, + DP_DEVICE_HDMI = 2, + DP_DEVICE_MIPI = 3, + DP_DEVICE_LVDS = 4, + DP_DEVICE_CVBS = 5, + DP_DEVICE_DP0 = 6, + DP_DEVICE_DP1 = 7, + DP_DEVICE_END, +}; + +enum { + DP_CLOCK_RESCONV = 0, + DP_CLOCK_LCDIF = 1, + DP_CLOCK_MIPI = 2, + DP_CLOCK_LVDS = 3, + DP_CLOCK_HDMI = 4, + DP_CLOCK_END, +}; + +enum dp_lvds_format { + DP_LVDS_FORMAT_VESA = 0, + DP_LVDS_FORMAT_JEIDA = 1, + DP_LVDS_FORMAT_LOC = 2, +}; + +#define DEF_VOLTAGE_LEVEL (0x20) + +struct dp_lvds_dev { + enum dp_lvds_format lvds_format; /* 0:VESA, 1:JEIDA, 2: Location */ + int pol_inv_hs; /* hsync polarity invert for VESA, JEIDA */ + int pol_inv_vs; /* bsync polarity invert for VESA, JEIDA */ + int pol_inv_de; /* de polarity invert for VESA, JEIDA */ + int pol_inv_ck; /* input clock(pixel clock) polarity invert */ + int voltage_level; + /* Location setting */ + unsigned int loc_map[9]; /* Location Setting */ + unsigned int loc_mask[2]; /* Location Setting, 0 ~ 34 */ + unsigned int loc_pol[2]; /* Location Setting, 0 ~ 34 */ +}; + +#include "mipi_display.h" + +struct dp_mipi_dev { + int lp_bitrate; /* to lcd setup, low power bitrate (150, 100, 80 Mhz) */ + int hs_bitrate; /* to lcd data, high speed bitrate (1000, ... Mhz) */ + int lpm_trans; + int command_mode; + unsigned int hs_pllpms; + unsigned int hs_bandctl; + unsigned int lp_pllpms; + unsigned int lp_bandctl; + struct mipi_dsi_device dsi; +}; + +struct dp_rgb_dev { + int lcd_mpu_type; +}; + +struct dp_hdmi_dev { + int preset; +}; + +/* platform data for the driver model */ +struct nx_display_platdata { + int module; + struct dp_sync_info sync; + struct dp_ctrl_info ctrl; + struct dp_plane_top top; + struct dp_plane_info plane[DP_PLANS_NUM]; + int dev_type; + void *device; +}; + +/* Lcd api */ +void nx_lvds_display(int module, + struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, + struct dp_plane_top *top, + struct dp_plane_info *planes, + struct dp_lvds_dev *dev); + +void nx_rgb_display(int module, + struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, + struct dp_plane_top *top, struct dp_plane_info *planes, + struct dp_rgb_dev *dev); + +void nx_hdmi_display(int module, + struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, + struct dp_plane_top *top, + struct dp_plane_info *planes, + struct dp_hdmi_dev *dev); + +void nx_mipi_display(int module, + struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, + struct dp_plane_top *top, + struct dp_plane_info *planes, + struct dp_mipi_dev *dev); + +int nx_mipi_dsi_lcd_bind(struct mipi_dsi_device *dsi); + +/* disaply api */ +void dp_control_init(int module); +int dp_control_setup(int module, struct dp_sync_info *sync, + struct dp_ctrl_info *ctrl); +void dp_control_enable(int module, int on); + +void dp_plane_init(int module); +int dp_plane_screen_setup(int module, struct dp_plane_top *top); +void dp_plane_screen_enable(int module, int on); + +int dp_plane_layer_setup(int module, struct dp_plane_info *plane); +void dp_plane_layer_enable(int module, struct dp_plane_info *plane, int on); + +int dp_plane_set_enable(int module, int layer, int on); +int dp_plane_set_address(int module, int layer, unsigned int address); +int dp_plane_wait_vsync(int module, int layer, int fps); + +#if defined CONFIG_SPL_BUILD || \ + (!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL)) +int nx_display_probe(struct nx_display_platdata *plat); +#endif + +#endif diff --git a/arch/arm/mach-nexell/include/mach/display_dev.h b/arch/arm/mach-nexell/include/mach/display_dev.h new file mode 100644 index 0000000000..77eb614768 --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/display_dev.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2016 Nexell Co., Ltd. + * + * Author: junghyun, kim <jhkim@nexell.co.kr> + */ + +#ifndef _NX__DISPLAY_DEV_H_ +#define _NX__DISPLAY_DEV_H_ + +#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO +#include <video_fb.h> +#elif defined CONFIG_LCD +#include <lcd.h> +#endif + +struct nx_display_dev { +#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO + GraphicDevice graphic_device; +#elif defined CONFIG_LCD + vidinfo_t *panel_info; +#endif + unsigned long base; + int module; + struct dp_sync_info sync; + struct dp_ctrl_info ctrl; + struct dp_plane_top top; + struct dp_plane_info planes[DP_PLANS_NUM]; + int dev_type; + void *device; + struct dp_plane_info *fb_plane; + unsigned int depth; /* byte per pixel */ + unsigned int fb_addr; + unsigned int fb_size; +}; + +#endif diff --git a/arch/arm/mach-nexell/include/mach/ehci.h b/arch/arm/mach-nexell/include/mach/ehci.h new file mode 100644 index 0000000000..545153b145 --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/ehci.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * NEXELL USB HOST EHCI Controller + * + * (C) Copyright 2016 Nexell + * Hyunseok, Jung <hsjung@nexell.co.kr> + */ + +#ifndef __ASM_ARM_ARCH_EHCI_H__ +#define __ASM_ARM_ARCH_EHCI_H__ + +/* Nexell USBHOST PHY registers */ + +/* USBHOST Configuration 0 Register */ +#define NX_HOST_CON0 0x14 +#define NX_HOST_CON0_SS_WORD_IF BIT(26) +#define NX_HOST_CON0_SS_WORD_IF_ENB BIT(25) +#define NX_HOST_CON0_SS_WORD_IF_16 ( \ + NX_HOST_CON0_SS_WORD_IF | \ + NX_HOST_CON0_SS_WORD_IF_ENB) + +#define NX_HOST_CON0_HSIC_480M_FROM_OTG_PHY BIT(24) +#define NX_HOST_CON0_HSIC_FREE_CLOCK_ENB BIT(23) +#define NX_HOST_CON0_HSIC_CLK_MASK (0x3 << 23) + +#define NX_HOST_CON0_N_HOST_HSIC_RESET_SYNC BIT(22) +#define NX_HOST_CON0_N_HOST_UTMI_RESET_SYNC BIT(21) +#define NX_HOST_CON0_N_HOST_PHY_RESET_SYNC BIT(20) +#define NX_HOST_CON0_UTMI_RESET_SYNC ( \ + NX_HOST_CON0_N_HOST_HSIC_RESET_SYNC | \ + NX_HOST_CON0_N_HOST_UTMI_RESET_SYNC | \ + NX_HOST_CON0_N_HOST_PHY_RESET_SYNC) + +#define NX_HOST_CON0_N_AUXWELL_RESET_SYNC BIT(19) +#define NX_HOST_CON0_N_OHCI_RESET_SYNC BIT(18) +#define NX_HOST_CON0_N_RESET_SYNC BIT(17) +#define NX_HOST_CON0_AHB_RESET_SYNC ( \ + NX_HOST_CON0_N_AUXWELL_RESET_SYNC | \ + NX_HOST_CON0_N_OHCI_RESET_SYNC | \ + NX_HOST_CON0_N_RESET_SYNC) + +#define NX_HOST_CON0_HSIC_EN_PORT1 (0x2 << 14) +#define NX_HOST_CON0_HSIC_EN_MASK (0x7 << 14) + +/* USBHOST Configuration 1 Register */ +#define NX_HOST_CON1 0x18 + +/* USBHOST Configuration 2 Register */ +#define NX_HOST_CON2 0x1C +#define NX_HOST_CON2_SS_ENA_INCRX_ALIGN (0x1 << 28) +#define NX_HOST_CON2_SS_ENA_INCR4 (0x1 << 27) +#define NX_HOST_CON2_SS_ENA_INCR8 (0x1 << 26) +#define NX_HOST_CON2_SS_ENA_INCR16 (0x1 << 25) +#define NX_HOST_CON2_SS_DMA_BURST_MASK \ + (NX_HOST_CON2_SS_ENA_INCR16 | NX_HOST_CON2_SS_ENA_INCR8 | \ + NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN) + +#define NX_HOST_CON2_EHCI_SS_ENABLE_DMA_BURST \ + (NX_HOST_CON2_SS_ENA_INCR16 | NX_HOST_CON2_SS_ENA_INCR8 | \ + NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN) + +#define NX_HOST_CON2_OHCI_SS_ENABLE_DMA_BURST \ + (NX_HOST_CON2_SS_ENA_INCR4 | NX_HOST_CON2_SS_ENA_INCRX_ALIGN) + +#define NX_HOST_CON2_SS_FLADJ_VAL_0_OFFSET (21) +#define NX_HOST_CON2_SS_FLADJ_VAL_OFFSET (3) +#define NX_HOST_CON2_SS_FLADJ_VAL_NUM (6) +#define NX_HOST_CON2_SS_FLADJ_VAL_0_SEL BIT(5) +#define NX_HOST_CON2_SS_FLADJ_VAL_MAX 0x7 + +/* USBHOST Configuration 3 Register */ +#define NX_HOST_CON3 0x20 +#define NX_HOST_CON3_POR BIT(8) +#define NX_HOST_CON3_POR_ENB BIT(7) +#define NX_HOST_CON3_POR_MASK (0x3 << 7) + +/* USBHOST Configuration 4 Register */ +#define NX_HOST_CON4 0x24 +#define NX_HOST_CON4_WORDINTERFACE BIT(9) +#define NX_HOST_CON4_WORDINTERFACE_ENB BIT(8) +#define NX_HOST_CON4_WORDINTERFACE_16 ( \ + NX_HOST_CON4_WORDINTERFACE | \ + NX_HOST_CON4_WORDINTERFACE_ENB) + +/* USBHOST Configuration 5 Register */ +#define NX_HOST_CON5 0x28 +#define NX_HOST_CON5_HSIC_POR BIT(19) +#define NX_HOST_CON5_HSIC_POR_ENB BIT(18) +#define NX_HOST_CON5_HSIC_POR_MASK (0x3 << 18) + +/* USBHOST Configuration 6 Register */ +#define NX_HOST_CON6 0x2C +#define NX_HOST_CON6_HSIC_WORDINTERFACE BIT(13) +#define NX_HOST_CON6_HSIC_WORDINTERFACE_ENB BIT(12) +#define NX_HOST_CON6_HSIC_WORDINTERFACE_16 ( \ + NX_HOST_CON6_HSIC_WORDINTERFACE | \ + NX_HOST_CON6_HSIC_WORDINTERFACE_ENB) + +/* Register map for PHY control */ +struct nx_usb_phy { + unsigned int reserved; + unsigned int others[4]; + unsigned int usbhost_con[7]; +}; + +#endif /* __ASM_ARM_ARCH_EHCI_H__ */ diff --git a/arch/arm/mach-nexell/include/mach/gpio.h b/arch/arm/mach-nexell/include/mach/gpio.h new file mode 100644 index 0000000000..7167d3cf5b --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/gpio.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * (C) Copyright 2016 Nexell + * DeokJin, Lee <truevirtue@nexell.co.kr> + */ + +#ifndef __ASM_ARCH_NEXELL_GPIO_H +#define __ASM_ARCH_NEXELL_GPIO_H + +#include <asm/io.h> +#include <linux/errno.h> + +#define PIN_BASE 0 + +#define MAX_GPIO_BANKS 5 + +#endif /* __ASM_ARCH_NEXELL_GPIO_H */ diff --git a/arch/arm/mach-nexell/include/mach/mipi_display.h b/arch/arm/mach-nexell/include/mach/mipi_display.h new file mode 100644 index 0000000000..f3fdec6464 --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/mipi_display.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Defines for Mobile Industry Processor Interface (MIPI(R)) + * Display Working Group standards: DSI, DCS, DBI, DPI + * + * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> + * Copyright (C) 2006 Nokia Corporation + * Author: Imre Deak <imre.deak@nokia.com> + */ + +#ifndef MIPI_DISPLAY_H +#define MIPI_DISPLAY_H + +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* MIPI DSI Peripheral-to-Processor transaction types */ +enum { + MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, + MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, + MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, + MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, +}; + +/* MIPI DCS commands */ +enum { + MIPI_DCS_NOP = 0x00, + MIPI_DCS_SOFT_RESET = 0x01, + MIPI_DCS_GET_DISPLAY_ID = 0x04, + MIPI_DCS_GET_RED_CHANNEL = 0x06, + MIPI_DCS_GET_GREEN_CHANNEL = 0x07, + MIPI_DCS_GET_BLUE_CHANNEL = 0x08, + MIPI_DCS_GET_DISPLAY_STATUS = 0x09, + MIPI_DCS_GET_POWER_MODE = 0x0A, + MIPI_DCS_GET_ADDRESS_MODE = 0x0B, + MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, + MIPI_DCS_GET_DISPLAY_MODE = 0x0D, + MIPI_DCS_GET_SIGNAL_MODE = 0x0E, + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + MIPI_DCS_ENTER_SLEEP_MODE = 0x10, + MIPI_DCS_EXIT_SLEEP_MODE = 0x11, + MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, + MIPI_DCS_ENTER_NORMAL_MODE = 0x13, + MIPI_DCS_EXIT_INVERT_MODE = 0x20, + MIPI_DCS_ENTER_INVERT_MODE = 0x21, + MIPI_DCS_SET_GAMMA_CURVE = 0x26, + MIPI_DCS_SET_DISPLAY_OFF = 0x28, + MIPI_DCS_SET_DISPLAY_ON = 0x29, + MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, + MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, + MIPI_DCS_WRITE_MEMORY_START = 0x2C, + MIPI_DCS_WRITE_LUT = 0x2D, + MIPI_DCS_READ_MEMORY_START = 0x2E, + MIPI_DCS_SET_PARTIAL_AREA = 0x30, + MIPI_DCS_SET_SCROLL_AREA = 0x33, + MIPI_DCS_SET_TEAR_OFF = 0x34, + MIPI_DCS_SET_TEAR_ON = 0x35, + MIPI_DCS_SET_ADDRESS_MODE = 0x36, + MIPI_DCS_SET_SCROLL_START = 0x37, + MIPI_DCS_EXIT_IDLE_MODE = 0x38, + MIPI_DCS_ENTER_IDLE_MODE = 0x39, + MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, + MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, + MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, + MIPI_DCS_SET_TEAR_SCANLINE = 0x44, + MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_READ_DDB_START = 0xA1, + MIPI_DCS_READ_DDB_CONTINUE = 0xA8, +}; + +/* MIPI DCS pixel formats */ +#define MIPI_DCS_PIXEL_FMT_24BIT 7 +#define MIPI_DCS_PIXEL_FMT_18BIT 6 +#define MIPI_DCS_PIXEL_FMT_16BIT 5 +#define MIPI_DCS_PIXEL_FMT_12BIT 3 +#define MIPI_DCS_PIXEL_FMT_8BIT 2 +#define MIPI_DCS_PIXEL_FMT_3BIT 1 + +/* request ACK from peripheral */ +#define MIPI_DSI_MSG_REQ_ACK BIT(0) +/* use Low Power Mode to transmit message */ +#define MIPI_DSI_MSG_USE_LPM BIT(1) + +/** + * struct mipi_dsi_msg - read/write DSI buffer + * @channel: virtual channel id + * @type: payload data type + * @flags: flags controlling this message transmission + * @tx_len: length of @tx_buf + * @tx_buf: data to be written + * @rx_len: length of @rx_buf + * @rx_buf: data to be read, or NULL + */ +struct mipi_dsi_msg { + u8 channel; /* virtual channel id */ + u8 type; /* payload data type */ + u16 flags; /* flags controlling this message transmission */ + size_t tx_len; + const void *tx_buf; + size_t rx_len; + void *rx_buf; +}; + +/* DSI mode flags */ + +/* video mode */ +#define MIPI_DSI_MODE_VIDEO BIT(0) +/* video burst mode */ +#define MIPI_DSI_MODE_VIDEO_BURST BIT(1) +/* video pulse mode */ +#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2) +/* enable auto vertical count mode */ +#define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3) +/* enable hsync-end packets in vsync-pulse and v-porch area */ +#define MIPI_DSI_MODE_VIDEO_HSE BIT(4) +/* disable hfront-porch area */ +#define MIPI_DSI_MODE_VIDEO_HFP BIT(5) +/* disable hback-porch area */ +#define MIPI_DSI_MODE_VIDEO_HBP BIT(6) +/* disable hsync-active area */ +#define MIPI_DSI_MODE_VIDEO_HSA BIT(7) +/* flush display FIFO on vsync pulse */ +#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) +/* disable EoT packets in HS mode */ +#define MIPI_DSI_MODE_EOT_PACKET BIT(9) +/* device supports non-continuous clock behavior (DSI spec 5.6.1) */ +#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) +/* transmit data in low power */ +#define MIPI_DSI_MODE_LPM BIT(11) /* DSI mode flags */ + +enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB888, + MIPI_DSI_FMT_RGB666, + MIPI_DSI_FMT_RGB666_PACKED, + MIPI_DSI_FMT_RGB565, +}; + +/** + * struct mipi_dsi_device - DSI peripheral device + * @host: DSI host for this peripheral + * @dev: driver model device node for this peripheral + * @channel: virtual channel assigned to the peripheral + * @format: pixel format for video mode + * @lanes: number of active data lanes + * @mode_flags: DSI operation mode related flags + */ +struct mipi_dsi_device { + unsigned int channel; + unsigned int lanes; + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; + struct mipi_panel_ops *ops; + ssize_t (*write_buffer)(struct mipi_dsi_device *dsi, + const void *data, size_t len); +}; + +struct mipi_panel_ops { + int (*init)(struct mipi_dsi_device *dsi, int width, int height); + int (*prepare)(struct mipi_dsi_device *dsi); + int (*unprepare)(struct mipi_dsi_device *dsi); + int (*enable)(struct mipi_dsi_device *dsi); + int (*disable)(struct mipi_dsi_device *dsi); + void *private_data; +}; + +#endif diff --git a/arch/arm/mach-nexell/include/mach/nexell.h b/arch/arm/mach-nexell/include/mach/nexell.h new file mode 100644 index 0000000000..e42805fa01 --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/nexell.h @@ -0,0 +1,352 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * (C) Copyright 2016 Nexell + * Hyunseok, Jung <hsjung@nexell.co.kr> + */ + +#ifndef __NEXELL_H__ +#define __NEXELL_H__ + +#define PHY_BASEADDR_DMA0 (0xC0000000) +#define PHY_BASEADDR_DMA1 (0xC0001000) +#if defined(CONFIG_ARCH_S5P4418) +#define PHY_BASEADDR_INTC0 (0xC0002000) +#define PHY_BASEADDR_INTC1 (0xC0003000) +#elif defined(CONFIG_ARCH_S5P6818) +#define PHY_BASEADDR_INTC (0xC0008000) +#endif +#define PHY_BASEADDR_CLKPWR (0xC0010000) +#define PHY_BASEADDR_RTC (0xC0010C00) +#define PHY_BASEADDR_ALIVE (0xC0010800) +#define PHY_BASEADDR_RSTCON (0xC0012000) +#define PHY_BASEADDR_TIEOFF (0xC0011000) +#define PHY_BASEADDR_PDM (0xC0014000) +#define PHY_BASEADDR_CRYPTO (0xC0015000) +#define PHY_BASEADDR_TIMER (0xC0017000) +#define PHY_BASEADDR_PWM (0xC0018000) +#define PHY_BASEADDR_WDT (0xC0019000) +#define PHY_BASEADDR_GPIOA (0xC001A000) +#define PHY_BASEADDR_GPIOB (0xC001B000) +#define PHY_BASEADDR_GPIOC (0xC001C000) +#define PHY_BASEADDR_GPIOD (0xC001D000) +#define PHY_BASEADDR_GPIOE (0xC001E000) +#define PHY_BASEADDR_OHCI (0xC0020000) +#define PHY_BASEADDR_EHCI (0xC0030000) +#define PHY_BASEADDR_HSOTG (0xC0040000) +#define PHY_BASEADDR_ADC (0xC0053000) +#define PHY_BASEADDR_PPM (0xC0054000) +#define PHY_BASEADDR_I2S0 (0xC0055000) +#define PHY_BASEADDR_I2S1 (0xC0056000) +#define PHY_BASEADDR_I2S2 (0xC0057000) +#define PHY_BASEADDR_AC97 (0xC0058000) +#define PHY_BASEADDR_SPDIF_TX (0xC0059000) +#define PHY_BASEADDR_SPDIF_RX (0xC005A000) +#define PHY_BASEADDR_SSP0 (0xC005B000) +#define PHY_BASEADDR_SSP1 (0xC005C000) +#define PHY_BASEADDR_SSP2 (0xC005F000) +#define PHY_BASEADDR_MPEGTSI (0xC005D000) +#define PHY_BASEADDR_GMAC (0xC0060000) +#define PHY_BASEADDR_VIP0 (0xC0063000) +#define PHY_BASEADDR_VIP1 (0xC0064000) +#if defined(CONFIG_ARCH_S5P6818) +#define PHY_BASEADDR_VIP2 (0xC0099000) +#endif +#define PHY_BASEADDR_DEINTERLACE (0xC0065000) +#define PHY_BASEADDR_SCALER (0xC0066000) +#define PHY_BASEADDR_ECID (0xC0067000) +#define PHY_BASEADDR_SDMMC0 (0xC0062000) +#define PHY_BASEADDR_SDMMC1 (0xC0068000) +#define PHY_BASEADDR_SDMMC2 (0xC0069000) +#define PHY_BASEADDR_MALI400 (0xC0070000) +#define PHY_BASEADDR_CODA_APB0 (0xC0080000) +#define PHY_BASEADDR_CODA_APB1 (0xC0081000) +#define PHY_BASEADDR_CODA_APB2 (0xC0082000) +#define PHY_BASEADDR_CODA_APB3 (0xC0083000) +/* dma (O), modem(X), UART0_MODULE */ +#define PHY_BASEADDR_UART0 (0xC00A1000) +/* dma (O), modem(O), pl01115_Uart_modem_MODULE */ +#define PHY_BASEADDR_UART1 (0xC00A0000) +/* dma (O), modem(X), UART1_MODULE */ +#define PHY_BASEADDR_UART2 (0xC00A2000) +/* dma (X), modem(X), pl01115_Uart_nodma0_MODULE */ +#define PHY_BASEADDR_UART3 (0xC00A3000) +/* dma (X), modem(X), pl01115_Uart_nodma1_MODULE */ +#define PHY_BASEADDR_UART4 (0xC006D000) +/* dma (X), modem(X), pl01115_Uart_nodma2_MODULE */ +#define PHY_BASEADDR_UART5 (0xC006F000) +#define PHY_BASEADDR_I2C0 (0xC00A4000) +#define PHY_BASEADDR_I2C1 (0xC00A5000) +#define PHY_BASEADDR_I2C2 (0xC00A6000) +#define PHY_BASEADDR_CAN0 (0xC00CE000) +#define PHY_BASEADDR_CAN1 (0xC00CF000) +#define PHY_BASEADDR_MIPI (0xC00D0000) +#define PHY_BASEADDR_DISPLAYTOP (0xC0100000) + +#define PHY_BASEADDR_CLKGEN0 (0xC00BB000) /* TIMER_1 */ +#define PHY_BASEADDR_CLKGEN1 (0xC00BC000) /* TIMER_2 */ +#define PHY_BASEADDR_CLKGEN2 (0xC00BD000) /* TIMER_3 */ +#define PHY_BASEADDR_CLKGEN3 (0xC00BE000) /* PWM_1 */ +#define PHY_BASEADDR_CLKGEN4 (0xC00BF000) /* PWM_2 */ +#define PHY_BASEADDR_CLKGEN5 (0xC00C0000) /* PWM_3 */ +#define PHY_BASEADDR_CLKGEN6 (0xC00AE000) /* I2C_0 */ +#define PHY_BASEADDR_CLKGEN7 (0xC00AF000) /* I2C_1 */ +#define PHY_BASEADDR_CLKGEN8 (0xC00B0000) /* I2C_2 */ +#define PHY_BASEADDR_CLKGEN9 (0xC00CA000) /* MIPI */ +#define PHY_BASEADDR_CLKGEN10 (0xC00C8000) /* GMAC */ +#define PHY_BASEADDR_CLKGEN11 (0xC00B8000) /* SPDIF_TX */ +#define PHY_BASEADDR_CLKGEN12 (0xC00B7000) /* MPEGTSI */ +#define PHY_BASEADDR_CLKGEN13 (0xC00BA000) /* PWM_0 */ +#define PHY_BASEADDR_CLKGEN14 (0xC00B9000) /* TIMER_0 */ +#define PHY_BASEADDR_CLKGEN15 (0xC00B2000) /* I2S_0 */ +#define PHY_BASEADDR_CLKGEN16 (0xC00B3000) /* I2S_1 */ +#define PHY_BASEADDR_CLKGEN17 (0xC00B4000) /* I2S_2 */ +#define PHY_BASEADDR_CLKGEN18 (0xC00C5000) /* SDHC_0 */ +#define PHY_BASEADDR_CLKGEN19 (0xC00CC000) /* SDHC_1 */ +#define PHY_BASEADDR_CLKGEN20 (0xC00CD000) /* SDHC_2 */ +#define PHY_BASEADDR_CLKGEN21 (0xC00C3000) /* MALI */ +#define PHY_BASEADDR_CLKGEN22 (0xC00A9000) /* UART_0 */ +#define PHY_BASEADDR_CLKGEN23 (0xC00AA000) /* UART_2 */ +#define PHY_BASEADDR_CLKGEN24 (0xC00A8000) /* UART_1 */ +#define PHY_BASEADDR_CLKGEN25 (0xC00AB000) /* UART_3 */ +#define PHY_BASEADDR_CLKGEN26 (0xC006E000) /* UART_4 */ +#define PHY_BASEADDR_CLKGEN27 (0xC00B1000) /* UART_5 */ +#define PHY_BASEADDR_CLKGEN28 (0xC00B5000) /* DEINTERLACE */ +#define PHY_BASEADDR_CLKGEN29 (0xC00C4000) /* PPM */ +#define PHY_BASEADDR_CLKGEN30 (0xC00C1000) /* VIP_0 */ +#define PHY_BASEADDR_CLKGEN31 (0xC00C2000) /* VIP_1 */ +#define PHY_BASEADDR_CLKGEN32 (0xC006B000) /* USB2HOST */ +#define PHY_BASEADDR_CLKGEN33 (0xC00C7000) /* CODA */ +#define PHY_BASEADDR_CLKGEN34 (0xC00C6000) /* CRYPTO */ +#define PHY_BASEADDR_CLKGEN35 (0xC00B6000) /* SCALER */ +#define PHY_BASEADDR_CLKGEN36 (0xC00CB000) /* PDM */ +#define PHY_BASEADDR_CLKGEN37 (0xC00AC000) /* SPI0 */ +#define PHY_BASEADDR_CLKGEN38 (0xC00AD000) /* SPI1 */ +#define PHY_BASEADDR_CLKGEN39 (0xC00A7000) /* SPI2 */ +#if defined(CONFIG_ARCH_S5P6818) +#define PHY_BASEADDR_CLKGEN40 (0xC009A000) +#endif +#define PHY_BASEADDR_DREX (0xC00E0000) + +#define PHY_BASEADDR_CS_NAND (0x2C000000) + +#define PHY_BASEADDR_SRAM (0xFFFF0000) + +/* + * Nexell clock generator + */ +#define CLK_ID_TIMER_1 0 +#define CLK_ID_TIMER_2 1 +#define CLK_ID_TIMER_3 2 +#define CLK_ID_PWM_1 3 +#define CLK_ID_PWM_2 4 +#define CLK_ID_PWM_3 5 +#define CLK_ID_I2C_0 6 +#define CLK_ID_I2C_1 7 +#define CLK_ID_I2C_2 8 +#define CLK_ID_MIPI 9 +#define CLK_ID_GMAC 10 /* External Clock 1 */ +#define CLK_ID_SPDIF_TX 11 +#define CLK_ID_MPEGTSI 12 +#define CLK_ID_PWM_0 13 +#define CLK_ID_TIMER_0 14 +#define CLK_ID_I2S_0 15 /* External Clock 1 */ +#define CLK_ID_I2S_1 16 /* External Clock 1 */ +#define CLK_ID_I2S_2 17 /* External Clock 1 */ +#define CLK_ID_SDHC_0 18 +#define CLK_ID_SDHC_1 19 +#define CLK_ID_SDHC_2 20 +#define CLK_ID_MALI 21 +#define CLK_ID_UART_0 22 /* UART0_MODULE */ +#define CLK_ID_UART_2 23 /* UART1_MODULE */ +#define CLK_ID_UART_1 24 /* pl01115_Uart_modem_MODULE */ +#define CLK_ID_UART_3 25 /* pl01115_Uart_nodma0_MODULE */ +#define CLK_ID_UART_4 26 /* pl01115_Uart_nodma1_MODULE */ +#define CLK_ID_UART_5 27 /* pl01115_Uart_nodma2_MODULE */ +#define CLK_ID_DIT 28 +#define CLK_ID_PPM 29 +#define CLK_ID_VIP_0 30 /* External Clock 1 */ +#define CLK_ID_VIP_1 31 /* External Clock 1, 2 */ +#define CLK_ID_USB2HOST 32 /* External Clock 2 */ +#define CLK_ID_CODA 33 +#define CLK_ID_CRYPTO 34 +#define CLK_ID_SCALER 35 +#define CLK_ID_PDM 36 +#define CLK_ID_SPI_0 37 +#define CLK_ID_SPI_1 38 +#define CLK_ID_SPI_2 39 +#define CLK_ID_MAX 39 + +/* + * Nexell Reset control + */ +#define RESET_ID_AC97 0 +#define RESET_ID_CPU1 1 +#define RESET_ID_CPU2 2 +#define RESET_ID_CPU3 3 +#define RESET_ID_WD1 4 +#define RESET_ID_WD2 5 +#define RESET_ID_WD3 6 +#define RESET_ID_CRYPTO 7 +#define RESET_ID_DEINTERLACE 8 +#define RESET_ID_DISP_TOP 9 +#define RESET_ID_DISPLAY 10 +#define RESET_ID_RESCONV 11 +#define RESET_ID_LCDIF 12 +#define RESET_ID_HDMI 13 +#define RESET_ID_HDMI_VIDEO 14 +#define RESET_ID_HDMI_SPDIF 15 +#define RESET_ID_HDMI_TMDS 16 +#define RESET_ID_HDMI_PHY 17 +#define RESET_ID_LVDS 18 +#define RESET_ID_ECID 19 +#define RESET_ID_I2C0 20 +#define RESET_ID_I2C1 21 +#define RESET_ID_I2C2 22 +#define RESET_ID_I2S0 23 +#define RESET_ID_I2S1 24 +#define RESET_ID_I2S2 25 +#define RESET_ID_DREX_C 26 +#define RESET_ID_DREX_A 27 +#define RESET_ID_DREX 28 +#define RESET_ID_MIPI 29 +#define RESET_ID_MIPI_DSI 30 +#define RESET_ID_MIPI_CSI 31 +#define RESET_ID_MIPI_PHY_S 32 +#define RESET_ID_MIPI_PHY_M 33 +#define RESET_ID_MPEGTSI 34 +#define RESET_ID_PDM 35 +#define RESET_ID_TIMER 36 +#define RESET_ID_PWM 37 +#define RESET_ID_SCALER 38 +#define RESET_ID_SDMMC0 39 +#define RESET_ID_SDMMC1 40 +#define RESET_ID_SDMMC2 41 +#define RESET_ID_SPDIFRX 42 +#define RESET_ID_SPDIFTX 43 +#define RESET_ID_SSP0_P 44 +#define RESET_ID_SSP0 45 +#define RESET_ID_SSP1_P 46 +#define RESET_ID_SSP1 47 +#define RESET_ID_SSP2_P 48 +#define RESET_ID_SSP2 49 +#define RESET_ID_UART0 50 /* UART1 */ +#define RESET_ID_UART1 51 /* pl01115_Uart_modem */ +#define RESET_ID_UART2 52 /* UART1 */ +#define RESET_ID_UART3 53 /* pl01115_Uart_nodma0 */ +#define RESET_ID_UART4 54 /* pl01115_Uart_nodma1 */ +#define RESET_ID_UART5 55 /* pl01115_Uart_nodma2 */ +#define RESET_ID_USB20HOST 56 +#define RESET_ID_USB20OTG 57 +#define RESET_ID_WDT 58 +#define RESET_ID_WDT_POR 59 +#define RESET_ID_ADC 60 +#define RESET_ID_CODA_A 61 +#define RESET_ID_CODA_P 62 +#define RESET_ID_CODA_C 63 +#define RESET_ID_DWC_GMAC 64 +#define RESET_ID_MALI400 65 +#define RESET_ID_PPM 66 +#define RESET_ID_VIP1 67 +#define RESET_ID_VIP0 68 +#if defined(CONFIG_ARCH_S5P6818) +#define RESET_ID_VIP2 69 +#endif + +/* + * device name + */ +#define DEV_NAME_UART "nx-uart" /* pl0115 (amba-pl011.c) */ +#define DEV_NAME_FB "nx-fb" +#define DEV_NAME_DISP "nx-disp" +#define DEV_NAME_LCD "nx-lcd" +#define DEV_NAME_LVDS "nx-lvds" +#define DEV_NAME_HDMI "nx-hdmi" +#define DEV_NAME_RESCONV "nx-resconv" +#define DEV_NAME_MIPI "nx-mipi" +#define DEV_NAME_PCM "nx-pcm" +#define DEV_NAME_I2S "nx-i2s" +#define DEV_NAME_SPDIF_TX "nx-spdif-tx" +#define DEV_NAME_SPDIF_RX "nx-spdif-rx" +#define DEV_NAME_I2C "nx-i2c" +#define DEV_NAME_NAND "nx-nand" +#define DEV_NAME_KEYPAD "nx-keypad" +#define DEV_NAME_SDHC "nx-sdhc" +#define DEV_NAME_PWM "nx-pwm" +#define DEV_NAME_TIMER "nx-timer" +#define DEV_NAME_SOC_PWM "nx-soc-pwm" +#define DEV_NAME_GPIO "nx-gpio" +#define DEV_NAME_RTC "nx-rtc" +#define DEV_NAME_GMAC "nx-gmac" +#define DEV_NAME_MPEGTSI "nx-mpegtsi" +#define DEV_NAME_MALI "nx-mali" +#define DEV_NAME_DIT "nx-deinterlace" +#define DEV_NAME_PPM "nx-ppm" +#define DEV_NAME_VIP "nx-vip" +#define DEV_NAME_CODA "nx-coda" +#define DEV_NAME_USB2HOST "nx-usb2h" +#define DEV_NAME_CRYPTO "nx-crypto" +#define DEV_NAME_SCALER "nx-scaler" +#define DEV_NAME_PDM "nx-pdm" +#define DEV_NAME_SPI "nx-spi" +#define DEV_NAME_CPUFREQ "nx-cpufreq" + +/* + * clock generator + */ +#define CORECLK_NAME_PLL0 "pll0" /* cpu clock */ +#define CORECLK_NAME_PLL1 "pll1" +#define CORECLK_NAME_PLL2 "pll2" +#define CORECLK_NAME_PLL3 "pll3" +#define CORECLK_NAME_FCLK "fclk" +#define CORECLK_NAME_MCLK "mclk" +#define CORECLK_NAME_BCLK "bclk" +#define CORECLK_NAME_PCLK "pclk" +#define CORECLK_NAME_HCLK "hclk" + +#define CORECLK_ID_PLL0 0 +#define CORECLK_ID_PLL1 1 +#define CORECLK_ID_PLL2 2 +#define CORECLK_ID_PLL3 3 +#define CORECLK_ID_FCLK 4 +#define CORECLK_ID_MCLK 5 +#define CORECLK_ID_BCLK 6 +#define CORECLK_ID_PCLK 7 +#define CORECLK_ID_HCLK 8 + +#define ALIVEPWRGATEREG (PHY_BASEADDR_ALIVE + 0x0) + +#if defined(CONFIG_ARCH_S5P4418) +#define SCR_ARM_SECOND_BOOT (0xC0010C1C) /* PWR scratch */ +#define SCR_ARM_SECOND_BOOT_REG1 (0xc0010234) /* ToDo : Check Address */ +#elif defined(CONFIG_ARCH_S5P6818) +#define SCR_ARM_SECOND_BOOT (0xc0010230) /* PWR scratch */ +#define SCR_ARM_SECOND_BOOT_REG1 (0xc0010234) /* PWR scratch */ +#define SCR_ARM_SECOND_BOOT_REG2 (0xc0010238) /* PWR scratch */ +#endif + +#define SCR_ALIVE_BASE (PHY_BASEADDR_ALIVE) +#define SCR_SIGNAGURE_RESET (SCR_ALIVE_BASE + 0x068) +#define SCR_SIGNAGURE_SET (SCR_ALIVE_BASE + 0x06C) +#define SCR_SIGNAGURE_READ (SCR_ALIVE_BASE + 0x070) + +#define SYSRSTCONFIG (0x23C) +#define DEVICEBOOTINFO (0x50) +#define BOOTMODE_MASK (0x7) +#define BOOTMODE_SDMMC 5 +#define BOOTMODE_USB 6 +#define BOOTMODE_SDMMC_PORT_VAL(x) ((((x) >> 3) & 1) | \ + (((x) >> 19 & 1) << 1)) +#define EMMC_PORT_NUM 2 +#define SD_PORT_NUM 0 +#define ID_REG_EC0 (0x54) +#define WIRE0_MASK (0x1) + +#ifndef __ASSEMBLY__ + +#define NS_IN_HZ (1000000000UL) +#define TO_PERIOD_NS(freq) (NS_IN_HZ / (freq)) +#define TO_DUTY_NS(duty, freq) (duty ? TO_PERIOD_NS(freq) / (100 / duty) : 0) + +#endif /* __ASSEMBLY__ */ + +#endif /* __NEXELL_H__ */ diff --git a/arch/arm/mach-nexell/include/mach/nx_gpio.h b/arch/arm/mach-nexell/include/mach/nx_gpio.h new file mode 100644 index 0000000000..91803d28cb --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/nx_gpio.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * (C) Copyright 2016 Nexell + * Youngbok, Park <ybpark@nexell.co.kr> + */ + +#include <linux/types.h> +#include <asm/io.h> + +#ifndef __nx_gpio_h__ +#define __nx_gpio_h__ + +struct nx_gpio_register_set { + u32 gpioxout; + u32 gpioxoutenb; + u32 gpioxdetmode[2]; + u32 gpioxintenb; + u32 gpioxdet; + u32 gpioxpad; + u32 gpioxpuenb; + u32 gpioxaltfn[2]; + u32 gpioxdetmodeex; + u32 __reserved[4]; + u32 gpioxdetenb; + u32 gpiox_slew; + u32 gpiox_slew_disable_default; + u32 gpiox_drv1; + u32 gpiox_drv1_disable_default; + u32 gpiox_drv0; + u32 gpiox_drv0_disable_default; + u32 gpiox_pullsel; + u32 gpiox_pullsel_disable_default; + u32 gpiox_pullenb; + u32 gpiox_pullenb_disable_default; + u32 gpiox_input_mux_select0; + u32 gpiox_input_mux_select1; + u8 __reserved1[0x1000 - 0x70]; +}; + +enum { + nx_gpio_padfunc_0 = 0ul, + nx_gpio_padfunc_1 = 1ul, + nx_gpio_padfunc_2 = 2ul, + nx_gpio_padfunc_3 = 3ul +}; + +enum { + nx_gpio_drvstrength_0 = 0ul, + nx_gpio_drvstrength_1 = 1ul, + nx_gpio_drvstrength_2 = 2ul, + nx_gpio_drvstrength_3 = 3ul +}; + +enum { + nx_gpio_pull_down = 0ul, + nx_gpio_pull_up = 1ul, + nx_gpio_pull_off = 2ul +}; + +int nx_gpio_initialize(void); +u32 nx_gpio_get_number_of_module(void); +u32 nx_gpio_get_size_of_register_set(void); +void nx_gpio_set_base_address(u32 module_index, void *base_address); +void *nx_gpio_get_base_address(u32 module_index); +int nx_gpio_open_module(u32 module_index); +int nx_gpio_close_module(u32 module_index); +int nx_gpio_check_busy(u32 module_index); +void nx_gpio_set_detect_enable(u32 module_index, u32 bit_number, + int detect_enb); +void nx_gpio_set_pad_function(u32 module_index, u32 bit_number, u32 padfunc); +void nx_gpio_set_pad_function32(u32 module_index, u32 msbvalue, u32 lsbvalue); +int nx_gpio_get_pad_function(u32 module_index, u32 bit_number); +void nx_gpio_set_output_enable(u32 module_index, u32 bit_number, + int output_enb); +int nx_gpio_get_detect_enable(u32 module_index, u32 bit_number); +u32 nx_gpio_get_detect_enable32(u32 module_index); +void nx_gpio_set_detect_enable(u32 module_index, u32 bit_number, + int detect_enb); +void nx_gpio_set_detect_enable32(u32 module_index, u32 enable_flag); +int nx_gpio_get_output_enable(u32 module_index, u32 bit_number); +void nx_gpio_set_output_enable32(u32 module_index, int output_enb); +u32 nx_gpio_get_output_enable32(u32 module_index); +void nx_gpio_set_output_value(u32 module_index, u32 bit_number, int value); +int nx_gpio_get_output_value(u32 module_index, u32 bit_number); +void nx_gpio_set_output_value32(u32 module_index, u32 value); +u32 nx_gpio_get_output_value32(u32 module_index); +int nx_gpio_get_input_value(u32 module_index, u32 bit_number); +void nx_gpio_set_pull_select(u32 module_index, u32 bit_number, int enable); +void nx_gpio_set_pull_select32(u32 module_index, u32 value); +int nx_gpio_get_pull_select(u32 module_index, u32 bit_number); +u32 nx_gpio_get_pull_select32(u32 module_index); +void nx_gpio_set_pull_mode(u32 module_index, u32 bit_number, u32 mode); +void nx_gpio_set_fast_slew(u32 module_index, u32 bit_number, int enable); +void nx_gpio_set_drive_strength_disable_default(u32 module_index, + u32 bit_number, int enable); +void nx_gpio_set_drive_strength_disable_default(u32 module_index, + u32 bit_number, int enable); +void nx_gpio_set_drive_strength(u32 module_index, u32 bit_number, + u32 drvstrength); +void nx_gpio_set_drive_strength_disable_default(u32 module_index, + u32 bit_number, int enable); +u32 nx_gpio_get_drive_strength(u32 module_index, u32 bit_number); +#endif diff --git a/arch/arm/mach-nexell/include/mach/pwm.h b/arch/arm/mach-nexell/include/mach/pwm.h new file mode 100644 index 0000000000..08a287d308 --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/pwm.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2009 Samsung Electronics + * Kyungmin Park <kyungmin.park@samsung.com> + * Minkyu Kang <mk7.kang@samsung.com> + */ + +#ifndef __ASM_ARM_ARCH_PWM_H_ +#define __ASM_ARM_ARCH_PWM_H_ + +#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */ +#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ + +/* Divider MUX */ +#define MUX_DIV_1 0 /* 1/1 period */ +#define MUX_DIV_2 1 /* 1/2 period */ +#define MUX_DIV_4 2 /* 1/4 period */ +#define MUX_DIV_8 3 /* 1/8 period */ +#define MUX_DIV_16 4 /* 1/16 period */ + +#define MUX_DIV_SHIFT(x) ((x) * 4) + +#define TCON_OFFSET(x) (((x) + 1) * (!!(x)) << 2) + +#define TCON_START(x) (1 << TCON_OFFSET(x)) +#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1)) +#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2)) +#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3)) +#define TCON4_AUTO_RELOAD (1 << 22) + +#ifndef __ASSEMBLY__ +struct s5p_timer { + unsigned int tcfg0; + unsigned int tcfg1; + unsigned int tcon; + unsigned int tcntb0; + unsigned int tcmpb0; + unsigned int tcnto0; + unsigned int tcntb1; + unsigned int tcmpb1; + unsigned int tcnto1; + unsigned int tcntb2; + unsigned int tcmpb2; + unsigned int tcnto2; + unsigned int tcntb3; + unsigned int res1; + unsigned int tcnto3; + unsigned int tcntb4; + unsigned int tcnto4; + unsigned int tintcstat; +}; +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/arm/mach-nexell/include/mach/reset.h b/arch/arm/mach-nexell/include/mach/reset.h new file mode 100644 index 0000000000..e1301d4e53 --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/reset.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * (C) Copyright 2016 Nexell + * Youngbok, Park <ybpark@nexell.co.kr> + */ + +#ifndef __NEXELL_RESET__ +#define __NEXELL_RESET__ + +#define NUMBER_OF_RESET_MODULE_PIN 69 + +enum rstcon { + RSTCON_ASSERT = 0UL, + RSTCON_NEGATE = 1UL +}; + +void nx_rstcon_setrst(u32 rstindex, enum rstcon status); + +#endif /* __NEXELL_RESET__ */ diff --git a/arch/arm/mach-nexell/include/mach/sec_reg.h b/arch/arm/mach-nexell/include/mach/sec_reg.h new file mode 100644 index 0000000000..e3ae5ac1bb --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/sec_reg.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * (C) Copyright 2016 Nexell + * Youngbok, Park <park@nexell.co.kr> + */ + +#define NEXELL_L2C_SEC_ID 0 +#define NEXELL_MALI_SEC_ID 2 +#define NEXELL_MIPI_SEC_ID 4 +#define NEXELL_TOFF_SEC_ID 6 + +int write_sec_reg_by_id(void __iomem *reg, int val, int id); +int read_sec_reg_by_id(void __iomem *reg, int id); +int read_sec_reg(void __iomem *reg); +int write_sec_reg(void __iomem *reg, int val); diff --git a/arch/arm/mach-nexell/include/mach/tieoff.h b/arch/arm/mach-nexell/include/mach/tieoff.h new file mode 100644 index 0000000000..70e9652b6d --- /dev/null +++ b/arch/arm/mach-nexell/include/mach/tieoff.h @@ -0,0 +1,423 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * (C) Copyright 2016 Nexell + * Youngbok, Park <park@nexell.co.kr> + */ + +#ifndef _NEXELL_TIEOFF_H +#define _NEXELL_TIEOFF_H + +void nx_tieoff_set(u32 tieoff_index, u32 tieoff_value); +u32 nx_tieoff_get(u32 tieoff_index); + +#if defined(CONFIG_ARCH_S5P4418) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPCOREOUT ((1 << 16) | 0) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPCPU0 ((1 << 16) | 1) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPCPU1 ((1 << 16) | 2) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPCPU2 ((1 << 16) | 3) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPCPU3 ((1 << 16) | 4) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_COREPWRDOWN ((1 << 16) | 5) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CPU0PWRDOWN ((1 << 16) | 6) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CPU1PWRDOWN ((1 << 16) | 7) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CPU2PWRDOWN ((1 << 16) | 8) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CPU3PWRDOWN ((1 << 16) | 9) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2_CFGENDIAN ((1 << 16) | 10) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L1EMAS ((1 << 16) | 11) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_0 ((1 << 16) | 12) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1 ((1 << 16) | 13) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2PGEN_0 ((1 << 16) | 14) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2PGEN_1 ((1 << 16) | 15) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPL2_0 ((1 << 16) | 16) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CLAMPL2_1 ((1 << 16) | 17) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_VINITHI ((4 << 16) | 18) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2EMA ((3 << 16) | 22) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_TEINIT ((4 << 16) | 25) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L1EMAW ((2 << 16) | 29) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2EMAW ((2 << 16) | 32) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L1EMA ((3 << 16) | 34) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_CPUCLKOFF ((4 << 16) | 37) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_PWRCTLI0 ((2 << 16) | 41) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_PWRCTLI1 ((2 << 16) | 43) +#define NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_PWRCTLI2 ((2 << 16) | 45) +#elif defined(CONFIG_ARCH_S5P6818) +#define NX_TIEOFF_MMC_8BIT ((1 << 16) | 5) +#endif +#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAA ((3 << 16) | 47) +#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAB ((3 << 16) | 50) +#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAWA ((2 << 16) | 53) +#define NX_TIEOFF_AXISRAM0_i_TIE_ra2w_EMAWB ((2 << 16) | 55) +#define NX_TIEOFF_AXISRAM0_i_nPowerDown ((1 << 16) | 57) +#define NX_TIEOFF_AXISRAM0_i_nSleep ((1 << 16) | 58) +#define NX_TIEOFF_CAN0_i_TIE_rf1_EMA ((3 << 16) | 59) +#define NX_TIEOFF_CAN0_i_TIE_rf1_EMAW ((2 << 16) | 62) +#define NX_TIEOFF_CAN0_i_nPowerDown ((1 << 16) | 64) +#define NX_TIEOFF_CAN0_i_nSleep ((1 << 16) | 65) +#define NX_TIEOFF_CAN1_i_TIE_rf1_EMA ((3 << 16) | 66) +#define NX_TIEOFF_CAN1_i_TIE_rf1_EMAW ((2 << 16) | 69) +#define NX_TIEOFF_CAN1_i_nPowerDown ((1 << 16) | 71) +#define NX_TIEOFF_CAN1_i_nSleep ((1 << 16) | 72) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF1_EMA ((3 << 16) | 73) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF1_EMAW ((2 << 16) | 76) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2_EMAA ((3 << 16) | 78) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2_EMAB ((3 << 16) | 81) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2W_EMAA ((3 << 16) | 84) +#define NX_TIEOFF_DEINTERLACE0_i_NX_RF2W_EMAB ((3 << 16) | 87) +#define NX_TIEOFF_DISPLAYTOP0_i_ResConv_nPowerDown ((1 << 16) | 90) +#define NX_TIEOFF_DISPLAYTOP0_i_ResConv_nSleep ((1 << 16) | 91) +#define NX_TIEOFF_DISPLAYTOP0_i_HDMI_nPowerDown ((2 << 16) | 92) +#define NX_TIEOFF_DISPLAYTOP0_i_HDMI_nSleep ((2 << 16) | 94) +#define NX_TIEOFF_DISPLAYTOP0_i_HDMI_PHY_REFCLK_SEL ((1 << 16) | 96) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_SPSRAM_EMA ((3 << 16) | 97) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_SPSRAM_EMAW ((2 << 16) | 100) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_1R1W_EMAA ((3 << 16) | 102) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_1R1W_EMAB ((3 << 16) | 105) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAA ((3 << 16) | 108) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAB ((3 << 16) | 111) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAWA ((2 << 16) | 114) +#define NX_TIEOFF_DISPLAYTOP0_i_TIEOFF_DPSRAM_EMAWB ((2 << 16) | 116) +#define NX_TIEOFF_MCUSTOP0_i_vrom_EMA ((3 << 16) | 118) +#define NX_TIEOFF_DREX0_CKE_INIT ((1 << 16) | 121) +#define NX_TIEOFF_DREX0_CA_SWAP ((1 << 16) | 122) +#define NX_TIEOFF_DREX0_CSYSREQ ((1 << 16) | 123) +#define NX_TIEOFF_DREX0_PAUSE_REQ ((1 << 16) | 124) +#define NX_TIEOFF_DREX0_PEREV_TRIGGER ((1 << 16) | 125) +#define NX_TIEOFF_DREX0_CTRL_HCKE ((1 << 16) | 126) +#define NX_TIEOFF_DREX0_DFI_RESET_N_P0 ((1 << 16) | 127) +#define NX_TIEOFF_DREX0_DFI_RESET_N_P1 ((1 << 16) | 128) +#define NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAA ((3 << 16) | 129) +#define NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAB ((3 << 16) | 132) +#define NX_TIEOFF_MIPI0_i_NX_NPOWERDOWN ((4 << 16) | 135) +#define NX_TIEOFF_MIPI0_i_NX_NSLEEP ((4 << 16) | 139) +#define NX_TIEOFF_SCALER0_i_NX_EMA ((3 << 16) | 143) +#define NX_TIEOFF_SCALER0_i_NX_EMAW ((2 << 16) | 146) +#define NX_TIEOFF_UART0_USESMC ((1 << 16) | 148) +#define NX_TIEOFF_UART0_SMCTXENB ((1 << 16) | 149) +#define NX_TIEOFF_UART0_SMCRXENB ((1 << 16) | 150) +#define NX_TIEOFF_UART1_USESMC ((1 << 16) | 151) +#define NX_TIEOFF_UART1_SMCTXENB ((1 << 16) | 152) +#define NX_TIEOFF_UART1_SMCRXENB ((1 << 16) | 153) +#define NX_TIEOFF_UART2_USESMC ((1 << 16) | 154) +#define NX_TIEOFF_UART2_SMCTXENB ((1 << 16) | 155) +#define NX_TIEOFF_UART2_SMCRXENB ((1 << 16) | 156) +#define NX_TIEOFF_UART3_USESMC ((1 << 16) | 157) +#define NX_TIEOFF_UART3_SMCTXENB ((1 << 16) | 158) +#define NX_TIEOFF_UART3_SMCRXENB ((1 << 16) | 159) +#define NX_TIEOFF_UART4_USESMC ((1 << 16) | 160) +#define NX_TIEOFF_UART4_SMCTXENB ((1 << 16) | 161) +#define NX_TIEOFF_UART4_SMCRXENB ((1 << 16) | 162) +#define NX_TIEOFF_UART5_USESMC ((1 << 16) | 163) +#define NX_TIEOFF_UART5_SMCTXENB ((1 << 16) | 164) +#define NX_TIEOFF_UART5_SMCRXENB ((1 << 16) | 165) +#define NX_TIEOFF_USB20HOST0_i_nPowerDown ((1 << 16) | 166) +#define NX_TIEOFF_USB20HOST0_i_nSleep ((1 << 16) | 167) +#define NX_TIEOFF_USB20HOST0_i_NX_RF1_EMA ((3 << 16) | 168) +#define NX_TIEOFF_USB20HOST0_i_NX_RF1_EMAW ((2 << 16) | 171) +#define NX_TIEOFF_USB20HOST0_sys_interrupt_i ((1 << 16) | 173) +#define NX_TIEOFF_USB20HOST0_i_hsic_en ((3 << 16) | 174) +#define NX_TIEOFF_USB20HOST0_i_nResetSync ((1 << 16) | 177) +#define NX_TIEOFF_USB20HOST0_i_nResetSync_ohci ((1 << 16) | 178) +#define NX_TIEOFF_USB20HOST0_i_nAuxWellResetSync ((1 << 16) | 179) +#define NX_TIEOFF_USB20HOST0_i_nHostPhyResetSync ((1 << 16) | 180) +#define NX_TIEOFF_USB20HOST0_i_nHostUtmiResetSync ((1 << 16) | 181) +#define NX_TIEOFF_USB20HOST0_i_nHostHsicResetSync ((1 << 16) | 182) +#define NX_TIEOFF_USB20HOST0_i_HSIC_FREE_CLOCK_ENB ((1 << 16) | 183) +#define NX_TIEOFF_USB20HOST0_i_HSIC_480M_FROM_OTG_PHY ((1 << 16) | 184) +#define NX_TIEOFF_USB20HOST0_ss_word_if_enb_i ((1 << 16) | 185) +#define NX_TIEOFF_USB20HOST0_ss_word_if_i ((1 << 16) | 186) +#define NX_TIEOFF_USB20HOST0_ss_utmi_backward_enb_i ((1 << 16) | 187) +#define NX_TIEOFF_USB20HOST0_ss_resume_utmi_pls_dis_i ((1 << 16) | 188) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_0_i ((3 << 16) | 189) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_1_i ((3 << 16) | 192) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_2_i ((3 << 16) | 195) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_3_i ((3 << 16) | 198) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_4_i ((3 << 16) | 201) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_5_i ((3 << 16) | 204) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_6_i ((3 << 16) | 207) +#define NX_TIEOFF_USB20HOST0_phy_vstatus_7_i ((3 << 16) | 210) +#define NX_TIEOFF_USB20HOST0_ss_power_state_valid_i ((1 << 16) | 213) +#define NX_TIEOFF_USB20HOST0_ss_nxt_power_state_valid_i ((1 << 16) | 214) +#define NX_TIEOFF_USB20HOST0_ss_power_state_i ((2 << 16) | 215) +#define NX_TIEOFF_USB20HOST0_ss_next_power_state_i ((2 << 16) | 217) +#define NX_TIEOFF_USB20HOST0_app_prt_ovrcur_i ((3 << 16) | 219) +#define NX_TIEOFF_USB20HOST0_ss_simulation_mode_i ((1 << 16) | 222) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_host_i ((6 << 16) | 224) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_5_i ((3 << 16) | 230) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_4_i ((3 << 16) | 233) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_3_i ((3 << 16) | 236) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_2_i ((3 << 16) | 239) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_1_i ((3 << 16) | 242) +#define NX_TIEOFF_USB20HOST0_ss_fladj_val_0_i ((3 << 16) | 245) +#define NX_TIEOFF_USB20HOST0_ss_autoppd_on_overcur_en_i ((1 << 16) | 248) +#define NX_TIEOFF_USB20HOST0_ss_ena_incr16_i ((1 << 16) | 249) +#define NX_TIEOFF_USB20HOST0_ss_ena_incr8_i ((1 << 16) | 250) +#define NX_TIEOFF_USB20HOST0_ss_ena_incr4_i ((1 << 16) | 251) +#define NX_TIEOFF_USB20HOST0_ss_ena_incrx_align_i ((1 << 16) | 252) +#define NX_TIEOFF_USB20HOST0_i_ohci_0_cntsel_n ((1 << 16) | 253) +#define NX_TIEOFF_USB20HOST0_ohci_0_app_irq1_i ((1 << 16) | 254) +#define NX_TIEOFF_USB20HOST0_ohci_0_app_irq12_i ((1 << 16) | 255) +#define NX_TIEOFF_USB20HOST0_ohci_0_app_io_hit_i ((1 << 16) | 256) +#define NX_TIEOFF_USB20HOST0_ss_hubsetup_min_i ((1 << 16) | 257) +#define NX_TIEOFF_USB20HOST0_app_start_clk_i ((1 << 16) | 258) +#define NX_TIEOFF_USB20HOST0_ohci_susp_lgcy_i ((1 << 16) | 259) +#define NX_TIEOFF_USB20HOST0_i_SIDDQ ((1 << 16) | 260) +#define NX_TIEOFF_USB20HOST0_i_VATESTENB ((2 << 16) | 261) +#define NX_TIEOFF_USB20HOST0_i_POR_ENB ((1 << 16) | 263) +#define NX_TIEOFF_USB20HOST0_i_POR ((1 << 16) | 264) +#define NX_TIEOFF_USB20HOST0_i_REFCLKSEL ((2 << 16) | 265) +#define NX_TIEOFF_USB20HOST0_i_FSEL ((3 << 16) | 267) +#define NX_TIEOFF_USB20HOST0_i_COMMONONN ((1 << 16) | 270) +#define NX_TIEOFF_USB20HOST0_i_RESREQIN ((1 << 16) | 271) +#define NX_TIEOFF_USB20HOST0_i_PORTRESET ((1 << 16) | 272) +#define NX_TIEOFF_USB20HOST0_i_OTGDISABLE ((1 << 16) | 273) +#define NX_TIEOFF_USB20HOST0_i_LOOPBACKENB ((1 << 16) | 274) +#define NX_TIEOFF_USB20HOST0_i_IDPULLUPi ((1 << 16) | 275) +#define NX_TIEOFF_USB20HOST0_i_DRVVBUS ((1 << 16) | 276) +#define NX_TIEOFF_USB20HOST0_i_ADPCHRG ((1 << 16) | 277) +#define NX_TIEOFF_USB20HOST0_i_ADPDISCHRG ((1 << 16) | 278) +#define NX_TIEOFF_USB20HOST0_i_ADPPRBENB ((1 << 16) | 279) +#define NX_TIEOFF_USB20HOST0_i_VBUSVLDEXT ((1 << 16) | 280) +#define NX_TIEOFF_USB20HOST0_i_VBUSVLDEXTSEL ((1 << 16) | 281) +#define NX_TIEOFF_USB20HOST0_i_DPPULLDOWN ((1 << 16) | 282) +#define NX_TIEOFF_USB20HOST0_i_DMPULLDOWN ((1 << 16) | 283) +#define NX_TIEOFF_USB20HOST0_i_SUSPENDM_ENB ((1 << 16) | 284) +#define NX_TIEOFF_USB20HOST0_i_SUSPENDM ((1 << 16) | 285) +#define NX_TIEOFF_USB20HOST0_i_SLEEPM_ENB ((1 << 16) | 286) +#define NX_TIEOFF_USB20HOST0_i_SLEEPM ((1 << 16) | 287) +#define NX_TIEOFF_USB20HOST0_i_OPMODE_ENB ((1 << 16) | 288) +#define NX_TIEOFF_USB20HOST0_i_OPMODE ((2 << 16) | 289) +#define NX_TIEOFF_USB20HOST0_i_TERMSEL_ENB ((1 << 16) | 291) +#define NX_TIEOFF_USB20HOST0_i_TERMSEL ((1 << 16) | 292) +#define NX_TIEOFF_USB20HOST0_i_XCVRSEL_ENB ((1 << 16) | 293) +#define NX_TIEOFF_USB20HOST0_i_XCVRSEL ((2 << 16) | 294) +#define NX_TIEOFF_USB20HOST0_i_WORDINTERFACE_ENB ((1 << 16) | 296) +#define NX_TIEOFF_USB20HOST0_i_WORDINTERFACE ((1 << 16) | 297) +#define NX_TIEOFF_USB20HOST0_i_TXBITSTUFFEN ((1 << 16) | 298) +#define NX_TIEOFF_USB20HOST0_i_TXBITSTUFFENH ((1 << 16) | 299) +#define NX_TIEOFF_USB20HOST0_i_BYPASSDPDATA ((1 << 16) | 300) +#define NX_TIEOFF_USB20HOST0_i_BYPASSDMDATA ((1 << 16) | 301) +#define NX_TIEOFF_USB20HOST0_i_BYPASSDPEN ((1 << 16) | 302) +#define NX_TIEOFF_USB20HOST0_i_BYPASSDMEN ((1 << 16) | 303) +#define NX_TIEOFF_USB20HOST0_i_BYPASSSEL ((1 << 16) | 304) +#define NX_TIEOFF_USB20HOST0_i_COMPDISTUNE ((3 << 16) | 305) +#define NX_TIEOFF_USB20HOST0_i_SQRXTUNE ((3 << 16) | 308) +#define NX_TIEOFF_USB20HOST0_i_OTGTUNE ((3 << 16) | 311) +#define NX_TIEOFF_USB20HOST0_i_TXHSXVTUNE ((2 << 16) | 314) +#define NX_TIEOFF_USB20HOST0_i_TXFSLSTUNE ((4 << 16) | 316) +#define NX_TIEOFF_USB20HOST0_i_TXVREFTUNE ((4 << 16) | 320) +#define NX_TIEOFF_USB20HOST0_i_TXRISETUNE ((2 << 16) | 324) +#define NX_TIEOFF_USB20HOST0_i_TXRESTUNE ((2 << 16) | 326) +#define NX_TIEOFF_USB20HOST0_i_TXPREEMPAMPTUNE ((2 << 16) | 328) +#define NX_TIEOFF_USB20HOST0_i_TXPREEMPPULSETUNE ((1 << 16) | 330) +#define NX_TIEOFF_USB20HOST0_i_CHRGSEL ((1 << 16) | 331) +#define NX_TIEOFF_USB20HOST0_i_VDATDETENB ((1 << 16) | 332) +#define NX_TIEOFF_USB20HOST0_i_VDATSRCENB ((1 << 16) | 333) +#define NX_TIEOFF_USB20HOST0_i_DCDENB ((1 << 16) | 334) +#define NX_TIEOFF_USB20HOST0_i_ACAENB ((1 << 16) | 335) +#define NX_TIEOFF_USB20HOST0_i_HSIC_MSTRXCVR ((1 << 16) | 336) +#define NX_TIEOFF_USB20HOST0_i_HSIC_SIDDQ ((1 << 16) | 337) +#define NX_TIEOFF_USB20HOST0_i_HSIC_POR_ENB ((1 << 16) | 338) +#define NX_TIEOFF_USB20HOST0_i_HSIC_POR ((1 << 16) | 339) +#define NX_TIEOFF_USB20HOST0_i_HSIC_REFCLKDIV ((7 << 16) | 340) +#define NX_TIEOFF_USB20HOST0_i_HSIC_REFCLKSEL ((2 << 16) | 347) +#define NX_TIEOFF_USB20HOST0_i_HSIC_COMMONONN ((1 << 16) | 349) +#define NX_TIEOFF_USB20HOST0_i_HSIC_PORTRESET ((1 << 16) | 350) +#define NX_TIEOFF_USB20HOST0_i_HSIC_LOOPBACKENB ((1 << 16) | 351) +#define NX_TIEOFF_USB20HOST0_i_HSIC_DPPULLDOWN ((1 << 16) | 352) +#define NX_TIEOFF_USB20HOST0_i_HSIC_DMPULLDOWN ((1 << 16) | 353) +#define NX_TIEOFF_USB20HOST0_i_HSIC_SUSPENDM_ENB ((1 << 16) | 354) +#define NX_TIEOFF_USB20HOST0_i_HSIC_SUSPENDM ((1 << 16) | 355) +#define NX_TIEOFF_USB20HOST0_i_HSIC_SLEEPM_ENB ((1 << 16) | 356) +#define NX_TIEOFF_USB20HOST0_i_HSIC_SLEEPM ((1 << 16) | 357) +#define NX_TIEOFF_USB20HOST0_i_HSIC_MSTRXOPU ((1 << 16) | 358) +#define NX_TIEOFF_USB20HOST0_i_HSIC_OPMODE_ENB ((1 << 16) | 359) +#define NX_TIEOFF_USB20HOST0_i_HSIC_OPMODE ((2 << 16) | 360) +#define NX_TIEOFF_USB20HOST0_i_HSIC_XCVRSELECT_ENB ((1 << 16) | 362) +#define NX_TIEOFF_USB20HOST0_i_HSIC_XCVRSELECT ((1 << 16) | 363) +#define NX_TIEOFF_USB20HOST0_i_HSIC_WORDINTERFACE_ENB ((1 << 16) | 364) +#define NX_TIEOFF_USB20HOST0_i_HSIC_WORDINTERFACE ((1 << 16) | 365) +#define NX_TIEOFF_USB20HOST0_i_HSIC_TXBITSTUFFEN ((1 << 16) | 366) +#define NX_TIEOFF_USB20HOST0_i_HSIC_TXBITSTUFFENH ((1 << 16) | 367) +#define NX_TIEOFF_USB20HOST0_i_HSIC_TXRPUTUNE ((2 << 16) | 368) +#define NX_TIEOFF_USB20HOST0_i_HSIC_TXRPDTUNE ((2 << 16) | 370) +#define NX_TIEOFF_USB20HOST0_i_HSIC_TXSRTUNE ((4 << 16) | 372) +#define NX_TIEOFF_USB20OTG0_i_nPowerDown ((1 << 16) | 376) +#define NX_TIEOFF_USB20OTG0_i_nSleep ((1 << 16) | 377) +#define NX_TIEOFF_USB20OTG0_i_NX_RF1_EMA ((3 << 16) | 378) +#define NX_TIEOFF_USB20OTG0_i_NX_RF1_EMAW ((2 << 16) | 381) +#define NX_TIEOFF_USB20OTG0_i_ss_scaledown_mode ((2 << 16) | 384) +#define NX_TIEOFF_USB20OTG0_i_gp_in ((16 << 16) | 386) +#define NX_TIEOFF_USB20OTG0_i_sof_count ((14 << 16) | 402) +#define NX_TIEOFF_USB20OTG0_i_sys_dma_done ((1 << 16) | 416) +#define NX_TIEOFF_USB20OTG0_i_if_select_hsic ((1 << 16) | 417) +#define NX_TIEOFF_USB20OTG0_i_nResetSync ((1 << 16) | 418) +#define NX_TIEOFF_USB20OTG0_i_nUtmiResetSync ((1 << 16) | 419) +#define NX_TIEOFF_USB20OTG0_i_SIDDQ ((1 << 16) | 420) +#define NX_TIEOFF_USB20OTG0_i_VATESTENB ((2 << 16) | 421) +#define NX_TIEOFF_USB20OTG0_i_POR_ENB ((1 << 16) | 423) +#define NX_TIEOFF_USB20OTG0_i_POR ((1 << 16) | 424) +#define NX_TIEOFF_USB20OTG0_i_REFCLKSEL ((2 << 16) | 425) +#define NX_TIEOFF_USB20OTG0_i_FSEL ((3 << 16) | 427) +#define NX_TIEOFF_USB20OTG0_i_COMMONONN ((1 << 16) | 430) +#define NX_TIEOFF_USB20OTG0_i_RESREQIN ((1 << 16) | 431) +#define NX_TIEOFF_USB20OTG0_i_PORTRESET ((1 << 16) | 432) +#define NX_TIEOFF_USB20OTG0_i_OTGDISABLE ((1 << 16) | 433) +#define NX_TIEOFF_USB20OTG0_i_LOOPBACKENB ((1 << 16) | 434) +#define NX_TIEOFF_USB20OTG0_i_IDPULLUP ((1 << 16) | 435) +#define NX_TIEOFF_USB20OTG0_i_DRVVBUS ((1 << 16) | 436) +#define NX_TIEOFF_USB20OTG0_i_ADPCHRG ((1 << 16) | 437) +#define NX_TIEOFF_USB20OTG0_i_ADPDISCHRG ((1 << 16) | 438) +#define NX_TIEOFF_USB20OTG0_i_ADPPRBENB ((1 << 16) | 439) +#define NX_TIEOFF_USB20OTG0_i_VBUSVLDEXT ((1 << 16) | 440) +#define NX_TIEOFF_USB20OTG0_i_VBUSVLDEXTSEL ((1 << 16) | 441) +#define NX_TIEOFF_USB20OTG0_i_DPPULLDOWN ((1 << 16) | 442) +#define NX_TIEOFF_USB20OTG0_i_DMPULLDOWN ((1 << 16) | 443) +#define NX_TIEOFF_USB20OTG0_i_SUSPENDM_ENB ((1 << 16) | 444) +#define NX_TIEOFF_USB20OTG0_i_SUSPENDM ((1 << 16) | 445) +#define NX_TIEOFF_USB20OTG0_i_SLEEPM_ENB ((1 << 16) | 446) +#define NX_TIEOFF_USB20OTG0_i_SLEEPM ((1 << 16) | 447) +#define NX_TIEOFF_USB20OTG0_i_OPMODE_ENB ((1 << 16) | 448) +#define NX_TIEOFF_USB20OTG0_i_OPMODE ((2 << 16) | 449) +#define NX_TIEOFF_USB20OTG0_i_TERMSEL_ENB ((1 << 16) | 451) +#define NX_TIEOFF_USB20OTG0_i_TERMSEL ((1 << 16) | 452) +#define NX_TIEOFF_USB20OTG0_i_XCVRSEL_ENB ((1 << 16) | 453) +#define NX_TIEOFF_USB20OTG0_i_XCVRSEL ((2 << 16) | 454) +#define NX_TIEOFF_USB20OTG0_i_WORDINTERFACE_ENB ((1 << 16) | 456) +#define NX_TIEOFF_USB20OTG0_i_WORDINTERFACE ((1 << 16) | 457) +#define NX_TIEOFF_USB20OTG0_i_TXBITSTUFFEN ((1 << 16) | 458) +#define NX_TIEOFF_USB20OTG0_i_TXBITSTUFFENH ((1 << 16) | 459) +#define NX_TIEOFF_USB20OTG0_i_BYPASSDPDATA ((1 << 16) | 460) +#define NX_TIEOFF_USB20OTG0_i_BYPASSDMDATA ((1 << 16) | 461) +#define NX_TIEOFF_USB20OTG0_i_BYPASSDPEN ((1 << 16) | 462) +#define NX_TIEOFF_USB20OTG0_i_BYPASSDMEN ((1 << 16) | 463) +#define NX_TIEOFF_USB20OTG0_i_BYPASSSEL ((1 << 16) | 464) +#define NX_TIEOFF_USB20OTG0_i_COMPDISTUNE ((3 << 16) | 465) +#define NX_TIEOFF_USB20OTG0_i_SQRXTUNE ((3 << 16) | 468) +#define NX_TIEOFF_USB20OTG0_i_OTGTUNE ((3 << 16) | 471) +#define NX_TIEOFF_USB20OTG0_i_TXHSXVTUNE ((2 << 16) | 474) +#define NX_TIEOFF_USB20OTG0_i_TXFSLSTUNE ((4 << 16) | 476) +#define NX_TIEOFF_USB20OTG0_i_TXVREFTUNE ((4 << 16) | 480) +#define NX_TIEOFF_USB20OTG0_i_TXRISETUNE ((2 << 16) | 484) +#define NX_TIEOFF_USB20OTG0_i_TXRESTUNE ((2 << 16) | 486) +#define NX_TIEOFF_USB20OTG0_i_TXPREEMPAMPTUNE ((2 << 16) | 488) +#define NX_TIEOFF_USB20OTG0_i_TXPREEMPPULSETUNE ((1 << 16) | 490) +#define NX_TIEOFF_USB20OTG0_i_CHRGSEL ((1 << 16) | 491) +#define NX_TIEOFF_USB20OTG0_i_VDATDETENB ((1 << 16) | 492) +#define NX_TIEOFF_USB20OTG0_i_VDATSRCENB ((1 << 16) | 493) +#define NX_TIEOFF_USB20OTG0_i_DCDENB ((1 << 16) | 494) +#define NX_TIEOFF_USB20OTG0_i_ACAENB ((1 << 16) | 495) +#define NX_TIEOFF_USB20OTG0_i_IDPULLUP_ENB ((1 << 16) | 496) +#define NX_TIEOFF_USB20OTG0_i_DPPULLDOWN_ENB ((1 << 16) | 497) +#define NX_TIEOFF_USB20OTG0_i_DMPULLDOWN_ENB ((1 << 16) | 498) +#define NX_TIEOFF_USB20OTG0_i_DRVVBUS_ENB ((1 << 16) | 499) +#define NX_TIEOFF_USB20OTG0_i_LPMClkMuxCntrl ((1 << 16) | 500) +#define NX_TIEOFF_USB20OTG0_i_GLITCHLESSMUXCntrl ((1 << 16) | 501) +#define NX_TIEOFF_CODA9600_i_nPWRDN00 ((4 << 16) | 502) +#define NX_TIEOFF_CODA9600_i_nSLEEP00 ((4 << 16) | 506) +#define NX_TIEOFF_CODA9600_i_nPWRDN01 ((8 << 16) | 512) +#define NX_TIEOFF_CODA9600_i_nSLEEP01 ((8 << 16) | 520) +#define NX_TIEOFF_CODA9600_i_nPWRDN02 ((10 << 16) | 528) +#define NX_TIEOFF_CODA9600_i_nSLEEP02 ((10 << 16) | 544) +#define NX_TIEOFF_CODA9600_i_nPWRDN03 ((2 << 16) | 554) +#define NX_TIEOFF_CODA9600_i_nSLEEP03 ((2 << 16) | 556) +#define NX_TIEOFF_CODA9600_i_nPWRDN04 ((8 << 16) | 558) +#define NX_TIEOFF_CODA9600_i_nSLEEP04 ((8 << 16) | 566) +#define NX_TIEOFF_CODA9600_i_nPWRDN05 ((3 << 16) | 576) +#define NX_TIEOFF_CODA9600_i_nSLEEP05 ((3 << 16) | 579) +#define NX_TIEOFF_CODA9600_i_nPWRDN06 ((7 << 16) | 582) +#define NX_TIEOFF_CODA9600_i_nSLEEP06 ((7 << 16) | 589) +#define NX_TIEOFF_CODA9600_i_nPWRDN07 ((12 << 16) | 596) +#define NX_TIEOFF_CODA9600_i_nSLEEP07 ((12 << 16) | 608) +#define NX_TIEOFF_CODA9600_i_nPWRDN08 ((1 << 16) | 620) +#define NX_TIEOFF_CODA9600_i_nSLEEP08 ((1 << 16) | 621) +#define NX_TIEOFF_CODA9600_i_nPWRDN09 ((2 << 16) | 622) +#define NX_TIEOFF_CODA9600_i_nSLEEP09 ((2 << 16) | 624) +#define NX_TIEOFF_CODA9600_i_nPWRDN10 ((10 << 16) | 626) +#define NX_TIEOFF_CODA9600_i_nSLEEP10 ((10 << 16) | 640) +#define NX_TIEOFF_CODA9600_i_nPWRDN11 ((1 << 16) | 650) +#define NX_TIEOFF_CODA9600_i_nSLEEP11 ((1 << 16) | 651) +#define NX_TIEOFF_CODA9600_i_TIE_rf2_EMAA ((3 << 16) | 652) +#define NX_TIEOFF_CODA9600_i_TIE_rf2_EMAB ((3 << 16) | 655) +#define NX_TIEOFF_CODA9600_i_TIE_rf2w_EMAA ((3 << 16) | 658) +#define NX_TIEOFF_CODA9600_i_TIE_rf2w_EMAB ((3 << 16) | 661) +#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAA ((3 << 16) | 664) +#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAB ((3 << 16) | 667) +#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAWA ((2 << 16) | 670) +#define NX_TIEOFF_CODA9600_i_TIE_ra2_EMAWB ((2 << 16) | 672) +#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAA ((3 << 16) | 674) +#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAB ((3 << 16) | 677) +#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAWA ((2 << 16) | 680) +#define NX_TIEOFF_CODA9600_i_TIE_ra2w_EMAWB ((2 << 16) | 682) +#define NX_TIEOFF_CODA9600_i_TIE_rf1_EMA ((3 << 16) | 684) +#define NX_TIEOFF_CODA9600_i_TIE_rf1_EMAW ((2 << 16) | 687) +#define NX_TIEOFF_CODA9600_i_TIE_rf1w_EMA ((3 << 16) | 689) +#define NX_TIEOFF_CODA9600_i_TIE_rf1w_EMAW ((2 << 16) | 692) +#define NX_TIEOFF_DWC_GMAC0_sbd_flowctrl_i ((1 << 16) | 694) +#define NX_TIEOFF_DWC_GMAC0_phy_intf_sel_i ((3 << 16) | 695) +#define NX_TIEOFF_DWC_GMAC0_i_NX_RF2_EMAA ((3 << 16) | 698) +#define NX_TIEOFF_DWC_GMAC0_i_NX_RF2_EMAB ((3 << 16) | 701) +#define NX_TIEOFF_MALI4000_NX_DPSRAM_1R1W_EMAA ((3 << 16) | 704) +#define NX_TIEOFF_MALI4000_NX_DPSRAM_1R1W_EMAB ((3 << 16) | 707) +#define NX_TIEOFF_MALI4000_NX_SPSRAM_EMA ((3 << 16) | 710) +#define NX_TIEOFF_MALI4000_NX_SPSRAM_EMAW ((2 << 16) | 713) +#define NX_TIEOFF_MALI4000_NX_SPSRAM_BW_EMA ((3 << 16) | 715) +#define NX_TIEOFF_MALI4000_NX_SPSRAM_BW_EMAW ((2 << 16) | 718) +#define NX_TIEOFF_MALI4000_PWRDNBYPASS ((1 << 16) | 720) +#define NX_TIEOFF_MALI4000_GP_NX_NPOWERDOWN ((15 << 16) | 721) +#define NX_TIEOFF_MALI4000_GP_NX_NSLEEP ((15 << 16) | 736) +#define NX_TIEOFF_MALI4000_L2_NX_NPOWERDOWN ((3 << 16) | 751) +#define NX_TIEOFF_MALI4000_L2_NX_NSLEEP ((3 << 16) | 754) +#define NX_TIEOFF_MALI4000_PP0_NX_NPOWERDOWN ((32 << 16) | 768) +#define NX_TIEOFF_MALI4000_PP0_NX_NSLEEP ((32 << 16) | 800) +#define NX_TIEOFF_MALI4000_PP1_NX_NPOWERDOWN ((32 << 16) | 832) +#define NX_TIEOFF_MALI4000_PP1_NX_NSLEEP ((32 << 16) | 864) +#define NX_TIEOFF_MALI4000_PP2_NX_NPOWERDOWN ((32 << 16) | 896) +#define NX_TIEOFF_MALI4000_PP2_NX_NSLEEP ((32 << 16) | 928) +#define NX_TIEOFF_MALI4000_PP3_NX_NPOWERDOWN ((32 << 16) | 960) +#define NX_TIEOFF_MALI4000_PP3_NX_NSLEEP ((32 << 16) | 992) +#define NX_TIEOFF_A3BM_AXI_PERI_BUS0_SYNCMODEREQm9 ((1 << 16) | 1024) +#define NX_TIEOFF_A3BM_AXI_PERI_BUS0_SYNCMODEREQm10 ((1 << 16) | 1025) +#define NX_TIEOFF_A3BM_AXI_PERI_BUS0_SYNCMODEREQm16 ((1 << 16) | 1026) +#define NX_TIEOFF_A3BM_AXI_TOP_MASTER_BUS0_REMAP ((2 << 16) | 1027) +#if defined(CONFIG_ARCH_S5P6818) +#define NX_TIEOFF_Inst_ARMTOP_SMPEN ((4 << 16) | 2816) +#define NX_TIEOFF_Inst_ARMTOP_STANBYWFI ((4 << 16) | 2880) +#define NX_TIEOFF_Inst_ARMTOP_STANBYWFIL2 ((1 << 16) | 2884) +#define NX_TIEOFF_Inst_ARMTOP_DBGNOPWRDWN ((4 << 16) | 2889) +#define NX_TIEOFF_Inst_ARMTOP_DBGPWRUPREQ ((4 << 16) | 2893) +#define NX_TIEOFF_Inst_ARMTOP_COREPWRDOWNPRE ((1 << 16) | 2901) +#define NX_TIEOFF_Inst_ARMTOP_CPU0PWRDOWNPRE ((1 << 16) | 2902) +#define NX_TIEOFF_Inst_ARMTOP_CPU1PWRDOWNPRE ((1 << 16) | 2903) +#define NX_TIEOFF_Inst_ARMTOP_CPU2PWRDOWNPRE ((1 << 16) | 2904) +#define NX_TIEOFF_Inst_ARMTOP_CPU3PWRDOWNPRE ((1 << 16) | 2905) +#define NX_TIEOFF_Inst_ARMTOP_COREPWRDOWNALL ((1 << 16) | 2906) +#define NX_TIEOFF_Inst_ARMTOP_CPU0PWRDOWNALL ((1 << 16) | 2907) +#define NX_TIEOFF_Inst_ARMTOP_CPU1PWRDOWNALL ((1 << 16) | 2908) +#define NX_TIEOFF_Inst_ARMTOP_CPU2PWRDOWNALL ((1 << 16) | 2909) +#define NX_TIEOFF_Inst_ARMTOP_CPU3PWRDOWNALL ((1 << 16) | 2910) +#define NX_TIEOFF_Inst_ARMTOP_CLAMPL2 ((1 << 16) | 2920) +#define NX_TIEOFF_Inst_ARMTOP_L2FLUSHREQ ((1 << 16) | 3018) +#define NX_TIEOFF_Inst_ARMTOP_L2FLUSHDONE ((1 << 16) | 3019) +#define NX_TIEOFF_Inst_ARMTOP_ACINACTM ((1 << 16) | 3023) +#define NX_TIEOFF_Inst_ARMTOP_P1_SMPEN ((4 << 16) | 3360) +#define NX_TIEOFF_Inst_ARMTOP_P1_STANBYWFI ((4 << 16) | 3424) +#define NX_TIEOFF_Inst_ARMTOP_P1_STANBYWFIL2 ((1 << 16) | 3428) +#define NX_TIEOFF_Inst_ARMTOP_P1_DBGNOPWRDWN ((4 << 16) | 3442) +#define NX_TIEOFF_Inst_ARMTOP_P1_DBGPWRUPREQ ((4 << 16) | 3443) +#define NX_TIEOFF_Inst_ARMTOP_P1_DBGPWRDUP ((4 << 16) | 3444) +#define NX_TIEOFF_Inst_ARMTOP_P1_COREPWRDOWNPRE ((1 << 16) | 3445) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU0PWRDOWNPRE ((1 << 16) | 3446) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU1PWRDOWNPRE ((1 << 16) | 3447) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU2PWRDOWNPRE ((1 << 16) | 3448) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU3PWRDOWNPRE ((1 << 16) | 3449) +#define NX_TIEOFF_Inst_ARMTOP_P1_COREPWRDOWNALL ((1 << 16) | 3450) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU0PWRDOWNALL ((1 << 16) | 3451) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU1PWRDOWNALL ((1 << 16) | 3452) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU2PWRDOWNALL ((1 << 16) | 3453) +#define NX_TIEOFF_Inst_ARMTOP_P1_CPU3PWRDOWNALL ((1 << 16) | 3454) +#define NX_TIEOFF_Inst_ARMTOP_P1_CLAMPL2 ((1 << 16) | 3464) +#define NX_TIEOFF_Inst_ARMTOP_P1_L2FLUSHREQ ((1 << 16) | 3562) +#define NX_TIEOFF_Inst_ARMTOP_P1_L2FLUSHDONE ((1 << 16) | 3563) +#define NX_TIEOFF_Inst_ARMTOP_P1_ACINACTM ((1 << 16) | 3567) +#endif + +#endif /* _NEXELL_TIEOFF_H */ diff --git a/arch/arm/mach-nexell/nx_gpio.c b/arch/arm/mach-nexell/nx_gpio.c new file mode 100644 index 0000000000..dfba3a2374 --- /dev/null +++ b/arch/arm/mach-nexell/nx_gpio.c @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Nexell + * Youngbok, Park <ybpark@nexell.co.kr> + */ + +/* + * FIXME : will be remove after support pinctrl + */ +#include <linux/types.h> +#include <asm/io.h> +#include <asm/arch/nexell.h> +#include "asm/arch/nx_gpio.h" +#define NUMBER_OF_GPIO_MODULE 5 +u32 __g_nx_gpio_valid_bit[NUMBER_OF_GPIO_MODULE] = { + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}; + +static struct { + struct nx_gpio_register_set *pregister; +} __g_module_variables[NUMBER_OF_GPIO_MODULE] = { + { (struct nx_gpio_register_set *)PHY_BASEADDR_GPIOA }, + { (struct nx_gpio_register_set *)PHY_BASEADDR_GPIOB }, + { (struct nx_gpio_register_set *)PHY_BASEADDR_GPIOC }, + { (struct nx_gpio_register_set *)PHY_BASEADDR_GPIOD }, + { (struct nx_gpio_register_set *)PHY_BASEADDR_GPIOE }, +}; + +enum { nx_gpio_max_bit = 32 }; + +void nx_gpio_set_bit(u32 *value, u32 bit, int enable) +{ + register u32 newvalue; + + newvalue = *value; + newvalue &= ~(1ul << bit); + newvalue |= (u32)enable << bit; + writel(newvalue, value); +} + +int nx_gpio_get_bit(u32 value, u32 bit) +{ + return (int)((value >> bit) & (1ul)); +} + +void nx_gpio_set_bit2(u32 *value, u32 bit, u32 bit_value) +{ + register u32 newvalue = *value; + + newvalue = (u32)(newvalue & ~(3ul << (bit * 2))); + newvalue = (u32)(newvalue | (bit_value << (bit * 2))); + + writel(newvalue, value); +} + +u32 nx_gpio_get_bit2(u32 value, u32 bit) +{ + return (u32)((u32)(value >> (bit * 2)) & 3ul); +} + +int nx_gpio_initialize(void) +{ + static int binit; + u32 i; + + binit = 0; + + if (binit == 0) { + for (i = 0; i < NUMBER_OF_GPIO_MODULE; i++) + __g_module_variables[i].pregister = NULL; + binit = true; + } + for (i = 0; i < NUMBER_OF_GPIO_MODULE; i++) { + __g_nx_gpio_valid_bit[i] = 0xFFFFFFFF; + }; + return true; +} + +u32 nx_gpio_get_number_of_module(void) +{ + return NUMBER_OF_GPIO_MODULE; +} + +u32 nx_gpio_get_size_of_register_set(void) +{ + return sizeof(struct nx_gpio_register_set); +} + +void nx_gpio_set_base_address(u32 module_index, void *base_address) +{ + __g_module_variables[module_index].pregister = + (struct nx_gpio_register_set *)base_address; +} + +void *nx_gpio_get_base_address(u32 module_index) +{ + return (void *)__g_module_variables[module_index].pregister; +} + +int nx_gpio_open_module(u32 module_index) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + writel(0xFFFFFFFF, &pregister->gpiox_slew_disable_default); + writel(0xFFFFFFFF, &pregister->gpiox_drv1_disable_default); + writel(0xFFFFFFFF, &pregister->gpiox_drv0_disable_default); + writel(0xFFFFFFFF, &pregister->gpiox_pullsel_disable_default); + writel(0xFFFFFFFF, &pregister->gpiox_pullenb_disable_default); + return true; +} + +int nx_gpio_close_module(u32 module_index) { return true; } + +int nx_gpio_check_busy(u32 module_index) { return false; } + +void nx_gpio_set_pad_function(u32 module_index, u32 bit_number, + u32 padfunc) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + nx_gpio_set_bit2(&pregister->gpioxaltfn[bit_number / 16], + bit_number % 16, padfunc); +} + +void nx_gpio_set_pad_function32(u32 module_index, u32 msbvalue, u32 lsbvalue) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + writel(lsbvalue, &pregister->gpioxaltfn[0]); + writel(msbvalue, &pregister->gpioxaltfn[1]); +} + +int nx_gpio_get_pad_function(u32 module_index, u32 bit_number) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + return (int)nx_gpio_get_bit2 + (readl(&pregister->gpioxaltfn[bit_number / 16]), + bit_number % 16); +} + +void nx_gpio_set_output_enable(u32 module_index, u32 bit_number, + int output_enb) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + nx_gpio_set_bit(&pregister->gpioxoutenb, bit_number, output_enb); +} + +int nx_gpio_get_detect_enable(u32 module_index, u32 bit_number) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + return nx_gpio_get_bit(readl(&pregister->gpioxdetenb), bit_number); +} + +u32 nx_gpio_get_detect_enable32(u32 module_index) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + return readl(&pregister->gpioxdetenb); +} + +void nx_gpio_set_detect_enable(u32 module_index, u32 bit_number, + int detect_enb) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + nx_gpio_set_bit(&pregister->gpioxdetenb, bit_number, detect_enb); +} + +void nx_gpio_set_detect_enable32(u32 module_index, u32 enable_flag) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + writel(enable_flag, &pregister->gpioxdetenb); +} + +int nx_gpio_get_output_enable(u32 module_index, u32 bit_number) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + return nx_gpio_get_bit(readl(&pregister->gpioxoutenb), bit_number); +} + +void nx_gpio_set_output_enable32(u32 module_index, int output_enb) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + if (output_enb) + writel(0xFFFFFFFF, &pregister->gpioxoutenb); + else + writel(0x0, &pregister->gpioxoutenb); +} + +u32 nx_gpio_get_output_enable32(u32 module_index) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + return readl(&pregister->gpioxoutenb); +} + +void nx_gpio_set_output_value(u32 module_index, u32 bit_number, int value) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + nx_gpio_set_bit(&pregister->gpioxout, bit_number, value); +} + +int nx_gpio_get_output_value(u32 module_index, u32 bit_number) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + return nx_gpio_get_bit(readl(&pregister->gpioxout), bit_number); +} + +void nx_gpio_set_output_value32(u32 module_index, u32 value) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + writel(value, &pregister->gpioxout); +} + +u32 nx_gpio_get_output_value32(u32 module_index) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + return readl(&pregister->gpioxout); +} + +int nx_gpio_get_input_value(u32 module_index, u32 bit_number) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + return nx_gpio_get_bit(readl(&pregister->gpioxpad), bit_number); +} + +void nx_gpio_set_pull_select(u32 module_index, u32 bit_number, int enable) +{ + nx_gpio_set_bit(&__g_module_variables[module_index] + .pregister->gpiox_pullsel_disable_default, + bit_number, true); + nx_gpio_set_bit + (&__g_module_variables[module_index].pregister->gpiox_pullsel, + bit_number, enable); +} + +void nx_gpio_set_pull_select32(u32 module_index, u32 value) +{ + writel(value, + &__g_module_variables[module_index].pregister->gpiox_pullsel); +} + +int nx_gpio_get_pull_select(u32 module_index, u32 bit_number) +{ + return nx_gpio_get_bit + (__g_module_variables[module_index].pregister->gpiox_pullsel, + bit_number); +} + +u32 nx_gpio_get_pull_select32(u32 module_index) +{ + return __g_module_variables[module_index].pregister->gpiox_pullsel; +} + +void nx_gpio_set_pull_mode(u32 module_index, u32 bit_number, u32 mode) +{ + nx_gpio_set_bit(&__g_module_variables[module_index] + .pregister->gpiox_pullsel_disable_default, + bit_number, true); + nx_gpio_set_bit(&__g_module_variables[module_index] + .pregister->gpiox_pullenb_disable_default, + bit_number, true); + if (mode == nx_gpio_pull_off) { + nx_gpio_set_bit + (&__g_module_variables[module_index].pregister->gpiox_pullenb, + bit_number, false); + nx_gpio_set_bit + (&__g_module_variables[module_index].pregister->gpiox_pullsel, + bit_number, false); + } else { + nx_gpio_set_bit + (&__g_module_variables[module_index].pregister->gpiox_pullsel, + bit_number, (mode & 1 ? true : false)); + nx_gpio_set_bit + (&__g_module_variables[module_index].pregister->gpiox_pullenb, + bit_number, true); + } +} + +void nx_gpio_set_fast_slew(u32 module_index, u32 bit_number, + int enable) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + nx_gpio_set_bit(&pregister->gpiox_slew, bit_number, + (int)(!enable)); +} + +void nx_gpio_set_drive_strength(u32 module_index, u32 bit_number, + u32 drvstrength) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + nx_gpio_set_bit(&pregister->gpiox_drv1, bit_number, + (int)(((u32)drvstrength >> 0) & 0x1)); + nx_gpio_set_bit(&pregister->gpiox_drv0, bit_number, + (int)(((u32)drvstrength >> 1) & 0x1)); +} + +void nx_gpio_set_drive_strength_disable_default(u32 module_index, + u32 bit_number, int enable) +{ + register struct nx_gpio_register_set *pregister; + + pregister = __g_module_variables[module_index].pregister; + nx_gpio_set_bit(&pregister->gpiox_drv1_disable_default, bit_number, + (int)(enable)); + nx_gpio_set_bit(&pregister->gpiox_drv0_disable_default, bit_number, + (int)(enable)); +} + +u32 nx_gpio_get_drive_strength(u32 module_index, u32 bit_number) +{ + register struct nx_gpio_register_set *pregister; + register u32 retvalue; + + pregister = __g_module_variables[module_index].pregister; + retvalue = + nx_gpio_get_bit(readl(&pregister->gpiox_drv0), bit_number) << 1; + retvalue |= + nx_gpio_get_bit(readl(&pregister->gpiox_drv1), bit_number) << 0; + return retvalue; +} diff --git a/arch/arm/mach-nexell/nx_sec_reg.c b/arch/arm/mach-nexell/nx_sec_reg.c new file mode 100644 index 0000000000..3d3dd9fd8b --- /dev/null +++ b/arch/arm/mach-nexell/nx_sec_reg.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Nexell + * Youngbok, Park <park@nexell.co.kr> + */ + +#include <linux/types.h> +#include <asm/io.h> +#include <asm/arch/nexell.h> +#include <asm/arch/sec_reg.h> +#include <linux/linkage.h> + +#define NEXELL_SMC_BASE 0x82000000 + +#define NEXELL_SMC_FN(n) (NEXELL_SMC_BASE + (n)) + +#define NEXELL_SMC_SEC_REG_WRITE NEXELL_SMC_FN(0x0) +#define NEXELL_SMC_SEC_REG_READ NEXELL_SMC_FN(0x1) + +#define SECURE_ID_SHIFT 8 + +#define SEC_4K_OFFSET ((4 * 1024) - 1) +#define SEC_64K_OFFSET ((64 * 1024) - 1) + +asmlinkage int __invoke_nexell_fn_smc(u32, u32, u32, u32); + +int write_sec_reg_by_id(void __iomem *reg, int val, int id) +{ + int ret = 0; + u32 off = 0; + + switch (id) { + case NEXELL_L2C_SEC_ID: + case NEXELL_MIPI_SEC_ID: + case NEXELL_TOFF_SEC_ID: + off = (u32)reg & SEC_4K_OFFSET; + break; + case NEXELL_MALI_SEC_ID: + off = (u32)reg & SEC_64K_OFFSET; + break; + } + ret = __invoke_nexell_fn_smc(NEXELL_SMC_SEC_REG_WRITE | + ((1 << SECURE_ID_SHIFT) + id), off, val, 0); + return ret; +} + +int read_sec_reg_by_id(void __iomem *reg, int id) +{ + int ret = 0; + u32 off = 0; + + switch (id) { + case NEXELL_L2C_SEC_ID: + case NEXELL_MIPI_SEC_ID: + case NEXELL_TOFF_SEC_ID: + off = (u32)reg & SEC_4K_OFFSET; + break; + case NEXELL_MALI_SEC_ID: + off = (u32)reg & SEC_64K_OFFSET; + break; + } + ret = __invoke_nexell_fn_smc(NEXELL_SMC_SEC_REG_READ | + ((1 << SECURE_ID_SHIFT) + id), off, 0, 0); + return ret; +} + +int write_sec_reg(void __iomem *reg, int val) +{ + int ret = 0; + + ret = __invoke_nexell_fn_smc(NEXELL_SMC_SEC_REG_WRITE, + (u32)reg, val, 0); + return ret; +} + +int read_sec_reg(void __iomem *reg) +{ + int ret = 0; + + ret = __invoke_nexell_fn_smc(NEXELL_SMC_SEC_REG_READ, (u32)reg, 0, 0); + return ret; +} diff --git a/arch/arm/mach-nexell/reg-call.S b/arch/arm/mach-nexell/reg-call.S new file mode 100644 index 0000000000..5fdf51520d --- /dev/null +++ b/arch/arm/mach-nexell/reg-call.S @@ -0,0 +1,23 @@ +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> + +#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF) +#define __opcode_to_mem_arm(x) ___opcode_identity32(x) +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x) + +#define ___opcode_identity32(x) ((u32)(x)) +#define ___inst_arm(x) .long x +#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x)) + +#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode) + +#define __SMC(imm4) __inst_arm_thumb32( \ + 0xE1600070 | (((imm4) & 0xF) << 0), \ + 0xF7F08000 | (((imm4) & 0xF) << 16) \ +) + +ENTRY(__invoke_nexell_fn_smc) + __SMC(0) + bx lr +ENDPROC(__invoke_nexell_fn_smc) diff --git a/arch/arm/mach-nexell/reset.c b/arch/arm/mach-nexell/reset.c new file mode 100644 index 0000000000..1f732a3d37 --- /dev/null +++ b/arch/arm/mach-nexell/reset.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Nexell + * Youngbok, Park <park@nexell.co.kr> + */ + +/* + *FIXME : Not support device tree & reset control driver. + * will remove after support device tree & reset control driver. + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/nexell.h> +#include <asm/arch/reset.h> + +struct nx_rstcon_registerset { + u32 regrst[(NUMBER_OF_RESET_MODULE_PIN + 31) >> 5]; +}; + +static struct nx_rstcon_registerset *nx_rstcon = + (struct nx_rstcon_registerset *)PHY_BASEADDR_RSTCON; + +void nx_rstcon_setrst(u32 rstindex, enum rstcon status) +{ + u32 regnum, bitpos, curstat; + + regnum = rstindex >> 5; + curstat = (u32)readl(&nx_rstcon->regrst[regnum]); + bitpos = rstindex & 0x1f; + curstat &= ~(1UL << bitpos); + curstat |= (status & 0x01) << bitpos; + writel(curstat, &nx_rstcon->regrst[regnum]); +} diff --git a/arch/arm/mach-nexell/tieoff.c b/arch/arm/mach-nexell/tieoff.c new file mode 100644 index 0000000000..5a4744c296 --- /dev/null +++ b/arch/arm/mach-nexell/tieoff.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Nexell + * Youngbok, Park <park@nexell.co.kr> + */ + +#include <common.h> +#include <asm/arch/nexell.h> +#include <asm/arch/clk.h> +#include <asm/arch/reset.h> +#include <asm/arch/nx_gpio.h> +#include <asm/arch/tieoff.h> +#include <asm/arch/sec_reg.h> + +#define NX_PIN_FN_SIZE 4 +#define TIEOFF_REG_NUM 33 + +struct nx_tieoff_registerset { + u32 tieoffreg[TIEOFF_REG_NUM]; +}; + +static struct nx_tieoff_registerset *nx_tieoff = (void *)PHY_BASEADDR_TIEOFF; + +static int tieoff_readl(void __iomem *reg) +{ + if (IS_ENABLED(CONFIG_ARCH_S5P4418)) + return read_sec_reg_by_id(reg, NEXELL_TOFF_SEC_ID); + else + return readl(reg); +} + +static int tieoff_writetl(void __iomem *reg, int val) +{ + if (IS_ENABLED(CONFIG_ARCH_S5P4418)) + return write_sec_reg_by_id(reg, val, NEXELL_TOFF_SEC_ID); + else + return writel(val, reg); +} + +void nx_tieoff_set(u32 tieoff_index, u32 tieoff_value) +{ + u32 regindex, mask; + u32 lsb, msb; + u32 regval; + + u32 position; + u32 bitwidth; + + position = tieoff_index & 0xffff; + bitwidth = (tieoff_index >> 16) & 0xffff; + + regindex = position >> 5; + + lsb = position & 0x1F; + msb = lsb + bitwidth; + + if (msb > 32) { + msb &= 0x1F; + mask = ~(0xffffffff << lsb); + regval = tieoff_readl(&nx_tieoff->tieoffreg[regindex]) & mask; + regval |= ((tieoff_value & ((1UL << bitwidth) - 1)) << lsb); + tieoff_writetl(&nx_tieoff->tieoffreg[regindex], regval); + + mask = (0xffffffff << msb); + regval = tieoff_readl(&nx_tieoff->tieoffreg[regindex]) & mask; + regval |= ((tieoff_value & ((1UL << bitwidth) - 1)) >> msb); + tieoff_writetl(&nx_tieoff->tieoffreg[regindex + 1], regval); + } else { + mask = (0xffffffff << msb) | (~(0xffffffff << lsb)); + regval = tieoff_readl(&nx_tieoff->tieoffreg[regindex]) & mask; + regval |= ((tieoff_value & ((1UL << bitwidth) - 1)) << lsb); + tieoff_writetl(&nx_tieoff->tieoffreg[regindex], regval); + } +} + +u32 nx_tieoff_get(u32 tieoff_index) +{ + u32 regindex, mask; + u32 lsb, msb; + u32 regval; + + u32 position; + u32 bitwidth; + + position = tieoff_index & 0xffff; + bitwidth = (tieoff_index >> 16) & 0xffff; + + regindex = position / 32; + lsb = position % 32; + msb = lsb + bitwidth; + + if (msb > 32) { + msb &= 0x1F; + mask = 0xffffffff << lsb; + regval = tieoff_readl(&nx_tieoff->tieoffreg[regindex]) & mask; + regval >>= lsb; + + mask = ~(0xffffffff << msb); + regval |= ((tieoff_readl(&nx_tieoff->tieoffreg[regindex + 1]) + & mask) << (32 - lsb)); + } else { + mask = ~(0xffffffff << msb) & (0xffffffff << lsb); + regval = tieoff_readl(&nx_tieoff->tieoffreg[regindex]) & mask; + regval >>= lsb; + } + return regval; +} diff --git a/arch/arm/mach-nexell/timer.c b/arch/arm/mach-nexell/timer.c new file mode 100644 index 0000000000..fecee67265 --- /dev/null +++ b/arch/arm/mach-nexell/timer.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Nexell + * Hyunseok, Jung <hsjung@nexell.co.kr> + */ + +#include <common.h> +#include <log.h> + +#include <asm/io.h> +#include <asm/arch/nexell.h> +#include <asm/arch/clk.h> +#if defined(CONFIG_ARCH_S5P4418) +#include <asm/arch/reset.h> +#endif + +#if (CONFIG_TIMER_SYS_TICK_CH > 3) +#error Not support timer channel. Please use "0~3" channels. +#endif + +/* global variables to save timer count + * + * Section ".data" must be used because BSS is not available before relocation, + * in board_init_f(), respectively! I.e. global variables can not be used! + */ +static unsigned long timestamp __attribute__ ((section(".data"))); +static unsigned long lastdec __attribute__ ((section(".data"))); +static int timerinit __attribute__ ((section(".data"))); + +/* macro to hw timer tick config */ +static long TIMER_FREQ = 1000000; +static long TIMER_HZ = 1000000 / CONFIG_SYS_HZ; +static long TIMER_COUNT = 0xFFFFFFFF; + +#define REG_TCFG0 (0x00) +#define REG_TCFG1 (0x04) +#define REG_TCON (0x08) +#define REG_TCNTB0 (0x0C) +#define REG_TCMPB0 (0x10) +#define REG_TCNT0 (0x14) +#define REG_CSTAT (0x44) + +#define TCON_BIT_AUTO (1 << 3) +#define TCON_BIT_INVT (1 << 2) +#define TCON_BIT_UP (1 << 1) +#define TCON_BIT_RUN (1 << 0) +#define TCFG0_BIT_CH(ch) ((ch) == 0 || (ch) == 1 ? 0 : 8) +#define TCFG1_BIT_CH(ch) ((ch) * 4) +#define TCON_BIT_CH(ch) ((ch) ? (ch) * 4 + 4 : 0) +#define TINT_CH(ch) (ch) +#define TINT_CSTAT_BIT_CH(ch) ((ch) + 5) +#define TINT_CSTAT_MASK (0x1F) +#define TIMER_TCNT_OFFS (0xC) + +void reset_timer_masked(void); +unsigned long get_timer_masked(void); + +/* + * Timer HW + */ +static inline void timer_clock(void __iomem *base, int ch, int mux, int scl) +{ + u32 val = readl(base + REG_TCFG0) & ~(0xFF << TCFG0_BIT_CH(ch)); + + writel(val | ((scl - 1) << TCFG0_BIT_CH(ch)), base + REG_TCFG0); + val = readl(base + REG_TCFG1) & ~(0xF << TCFG1_BIT_CH(ch)); + writel(val | (mux << TCFG1_BIT_CH(ch)), base + REG_TCFG1); +} + +static inline void timer_count(void __iomem *base, int ch, unsigned int cnt) +{ + writel((cnt - 1), base + REG_TCNTB0 + (TIMER_TCNT_OFFS * ch)); + writel((cnt - 1), base + REG_TCMPB0 + (TIMER_TCNT_OFFS * ch)); +} + +static inline void timer_start(void __iomem *base, int ch) +{ + int on = 0; + u32 val = readl(base + REG_CSTAT) & ~(TINT_CSTAT_MASK << 5 | 0x1 << ch); + + writel(val | (0x1 << TINT_CSTAT_BIT_CH(ch) | on << ch), + base + REG_CSTAT); + val = readl(base + REG_TCON) & ~(0xE << TCON_BIT_CH(ch)); + writel(val | (TCON_BIT_UP << TCON_BIT_CH(ch)), base + REG_TCON); + + val &= ~(TCON_BIT_UP << TCON_BIT_CH(ch)); + val |= ((TCON_BIT_AUTO | TCON_BIT_RUN) << TCON_BIT_CH(ch)); + writel(val, base + REG_TCON); + dmb(); +} + +static inline void timer_stop(void __iomem *base, int ch) +{ + int on = 0; + u32 val = readl(base + REG_CSTAT) & ~(TINT_CSTAT_MASK << 5 | 0x1 << ch); + + writel(val | (0x1 << TINT_CSTAT_BIT_CH(ch) | on << ch), + base + REG_CSTAT); + val = readl(base + REG_TCON) & ~(TCON_BIT_RUN << TCON_BIT_CH(ch)); + writel(val, base + REG_TCON); +} + +static inline unsigned long timer_read(void __iomem *base, int ch) +{ + unsigned long ret; + + ret = TIMER_COUNT - readl(base + REG_TCNT0 + (TIMER_TCNT_OFFS * ch)); + return ret; +} + +int timer_init(void) +{ + struct clk *clk = NULL; + char name[16] = "pclk"; + int ch = CONFIG_TIMER_SYS_TICK_CH; + unsigned long rate, tclk = 0; + unsigned long mout, thz, cmp = -1UL; + int tcnt, tscl = 0, tmux = 0; + int mux = 0, scl = 0; + void __iomem *base = (void __iomem *)PHY_BASEADDR_TIMER; + + if (timerinit) + return 0; + + /* get with PCLK */ + clk = clk_get(name); + rate = clk_get_rate(clk); + for (mux = 0; mux < 5; mux++) { + mout = rate / (1 << mux), scl = mout / TIMER_FREQ, + thz = mout / scl; + if (!(mout % TIMER_FREQ) && 256 > scl) { + tclk = thz, tmux = mux, tscl = scl; + break; + } + if (scl > 256) + continue; + if (abs(thz - TIMER_FREQ) >= cmp) + continue; + tclk = thz, tmux = mux, tscl = scl; + cmp = abs(thz - TIMER_FREQ); + } + tcnt = tclk; /* Timer Count := 1 Mhz counting */ + + TIMER_FREQ = tcnt; /* Timer Count := 1 Mhz counting */ + TIMER_HZ = TIMER_FREQ / CONFIG_SYS_HZ; + tcnt = TIMER_COUNT == 0xFFFFFFFF ? TIMER_COUNT + 1 : tcnt; + + timer_stop(base, ch); + timer_clock(base, ch, tmux, tscl); + timer_count(base, ch, tcnt); + timer_start(base, ch); + + reset_timer_masked(); + timerinit = 1; + + return 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +unsigned long get_timer(unsigned long base) +{ + long ret; + unsigned long time = get_timer_masked(); + unsigned long hz = TIMER_HZ; + + ret = time / hz - base; + return ret; +} + +void set_timer(unsigned long t) +{ + timestamp = (unsigned long)t; +} + +void reset_timer_masked(void) +{ + void __iomem *base = (void __iomem *)PHY_BASEADDR_TIMER; + int ch = CONFIG_TIMER_SYS_TICK_CH; + + /* reset time */ + /* capure current decrementer value time */ + lastdec = timer_read(base, ch); + /* start "advancing" time stamp from 0 */ + timestamp = 0; +} + +unsigned long get_timer_masked(void) +{ + void __iomem *base = (void __iomem *)PHY_BASEADDR_TIMER; + int ch = CONFIG_TIMER_SYS_TICK_CH; + + unsigned long now = timer_read(base, ch); /* current tick value */ + + if (now >= lastdec) { /* normal mode (non roll) */ + /* move stamp fordward with absolute diff ticks */ + timestamp += now - lastdec; + } else { + /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"... + * it could also roll and cause problems. + */ + timestamp += now + TIMER_COUNT - lastdec; + } + /* save last */ + lastdec = now; + + debug("now=%lu, last=%lu, timestamp=%lu\n", now, lastdec, timestamp); + return (unsigned long)timestamp; +} + +void __udelay(unsigned long usec) +{ + unsigned long tmo, tmp; + + debug("+udelay=%ld\n", usec); + + if (!timerinit) + timer_init(); + + /* if "big" number, spread normalization to seconds */ + if (usec >= 1000) { + /* start to normalize for usec to ticks per sec */ + tmo = usec / 1000; + /* find number of "ticks" to wait to achieve target */ + tmo *= TIMER_FREQ; + /* finish normalize. */ + tmo /= 1000; + /* else small number, don't kill it prior to HZ multiply */ + } else { + tmo = usec * TIMER_FREQ; + tmo /= (1000 * 1000); + } + + tmp = get_timer_masked(); /* get current timestamp */ + debug("A. tmo=%ld, tmp=%ld\n", tmo, tmp); + + /* if setting this fordward will roll time stamp */ + if (tmp > (tmo + tmp + 1)) + /* reset "advancing" timestamp to 0, set lastdec value */ + reset_timer_masked(); + else + /* set advancing stamp wake up time */ + tmo += tmp; + + debug("B. tmo=%ld, tmp=%ld\n", tmo, tmp); + + /* loop till event */ + do { + tmp = get_timer_masked(); + } while (tmo > tmp); + debug("-udelay=%ld\n", usec); +} + +void udelay_masked(unsigned long usec) +{ + unsigned long tmo, endtime; + signed long diff; + + /* if "big" number, spread normalization to seconds */ + if (usec >= 1000) { + /* start to normalize for usec to ticks per sec */ + tmo = usec / 1000; + /* find number of "ticks" to wait to achieve target */ + tmo *= TIMER_FREQ; + /* finish normalize. */ + tmo /= 1000; + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * TIMER_FREQ; + tmo /= (1000 * 1000); + } + + endtime = get_timer_masked() + tmo; + + do { + unsigned long now = get_timer_masked(); + + diff = endtime - now; + } while (diff >= 0); +} + +unsigned long long get_ticks(void) +{ + return get_timer_masked(); +} + +#if defined(CONFIG_ARCH_S5P4418) +ulong get_tbclk(void) +{ + ulong tbclk = TIMER_FREQ; + return tbclk; +} +#endif diff --git a/arch/arm/mach-omap2/config.mk b/arch/arm/mach-omap2/config.mk index af455366ed..4f0d2598fa 100644 --- a/arch/arm/mach-omap2/config.mk +++ b/arch/arm/mach-omap2/config.mk @@ -18,9 +18,9 @@ ifeq ($(CONFIG_TI_SECURE_DEVICE),y) # Refer to README.ti-secure for more info # For booting spl from QSPI or NOR use # u-boot-spl_HS_X-LOADER ifeq ($(CONFIG_OMAP54XX),y) -ALL-y += u-boot-spl_HS_MLO -ALL-y += u-boot-spl_HS_ULO -ALL-y += u-boot-spl_HS_X-LOADER +INPUTS-y += u-boot-spl_HS_MLO +INPUTS-y += u-boot-spl_HS_ULO +INPUTS-y += u-boot-spl_HS_X-LOADER endif # On AM43XX: # @@ -30,8 +30,8 @@ endif # For booting spl from all other media use # u-boot-spl_HS_ISSW ifeq ($(CONFIG_AM43XX),y) -ALL-y += u-boot-spl_HS_SPI_X-LOADER -ALL-y += u-boot-spl_HS_ISSW +INPUTS-y += u-boot-spl_HS_SPI_X-LOADER +INPUTS-y += u-boot-spl_HS_ISSW endif # On AM33XX: # @@ -47,21 +47,21 @@ endif # For booting spl over UART, USB, or Ethernet use # u-boot-spl_HS_2ND ifeq ($(CONFIG_AM33XX),y) -ALL-y += u-boot-spl_HS_SPI_X-LOADER -ALL-y += u-boot-spl_HS_X-LOADER -ALL-y += u-boot-spl_HS_MLO -ALL-y += u-boot-spl_HS_2ND +INPUTS-y += u-boot-spl_HS_SPI_X-LOADER +INPUTS-y += u-boot-spl_HS_X-LOADER +INPUTS-y += u-boot-spl_HS_MLO +INPUTS-y += u-boot-spl_HS_2ND endif else -ALL-y += MLO +INPUTS-y += MLO ifeq ($(CONFIG_AM33XX),y) -ALL-y += MLO.byteswap +INPUTS-y += MLO.byteswap endif endif else ifeq ($(CONFIG_TI_SECURE_DEVICE),y) -ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER -ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img +INPUTS-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER +INPUTS-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img endif -ALL-y += u-boot.img +INPUTS-y += u-boot.img endif diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index c8f93c68bb..07f607dd9d 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -2,6 +2,9 @@ if RCAR_GEN3 menu "Select Target SoC" +config R8A774A1 + bool "Renesas SoC R8A774A1" + config R8A7795 bool "Renesas SoC R8A7795" imply CLK_R8A7795 @@ -43,6 +46,11 @@ choice prompt "Renesas ARM64 SoCs board select" optional +config TARGET_BEACON_RZG2M + bool "Beacon EmbeddedWorks RZ/G2M Dev Kit" + select R8A774A1 + select PINCTRL_PFC_R8A774A1 + config TARGET_CONDOR bool "Condor board" imply R8A77980 @@ -100,6 +108,7 @@ source "board/renesas/eagle/Kconfig" source "board/renesas/ebisu/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" +source "board/beacon/beacon-rzg2m/Kconfig" config MULTI_DTB_FIT_UNCOMPRESS_SZ default 0x80000 if TARGET_SALVATOR_X diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index a3fdcc3bc0..3206bce722 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -84,5 +84,5 @@ spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin # if srec_cat is present build u-boot-spl.scif by default has_srec_cat = $(call try-run,srec_cat -VERSion,y,n) -ALL-$(has_srec_cat) += u-boot-spl.scif +INPUTS-$(has_srec_cat) += u-boot-spl.scif CLEAN_FILES += u-boot-spl.scif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index fcab1d5cee..407bf3fbea 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -367,6 +367,15 @@ config TPL_ROCKCHIP_EARLYRETURN_TO_BROM config SPL_MMC_SUPPORT default y if !SPL_ROCKCHIP_BACK_TO_BROM +config ROCKCHIP_SPI_IMAGE + bool "Build a SPI image for rockchip" + depends on HAS_ROM + help + Some Rockchip SoCs support booting from SPI flash. Enable this + option to produce a 4MB SPI-flash image (called u-boot.rom) + containing U-Boot. The image is built by binman. U-Boot sits near + the start of the image. + source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3128/Kconfig" diff --git a/arch/arm/mach-rockchip/fit_spl_optee.sh b/arch/arm/mach-rockchip/fit_spl_optee.sh deleted file mode 100755 index 4118472d9f..0000000000 --- a/arch/arm/mach-rockchip/fit_spl_optee.sh +++ /dev/null @@ -1,84 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2019 Rockchip Electronic Co.,Ltd -# -# Script to generate FIT image source for 32-bit Rockchip SoCs with -# U-Boot proper, OPTEE, and devicetree. -# -# usage: $0 <dt_name> - -[ -z "$TEE" ] && TEE="tee.bin" - -if [ ! -f $TEE ]; then - echo "WARNING: TEE file $TEE NOT found, U-Boot.itb is non-functional" >&2 - echo "Please export path for TEE or copy tee.bin to U-Boot folder" >&2 - TEE=/dev/null -fi - -dtname=$1 -text_base=`sed -n "/SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" .config \ - |tr -d '\r'` -dram_base=`sed -n "/SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" \ - include/autoconf.mk|tr -d '\r'` -tee_base=`echo "obase=16;$(($dram_base+0x8400000))"|bc` -tee_base='0x'$tee_base - -cat << __HEADER_EOF -/* - * Copyright (C) 2017-2019 Rockchip Electronic Co.,Ltd - * - * Simple U-boot FIT source file containing U-Boot, dtb and optee - */ - -/dts-v1/; - -/ { - description = "FIT image with OP-TEE support"; - #address-cells = <1>; - - images { - uboot { - description = "U-Boot"; - data = /incbin/("u-boot-nodtb.bin"); - type = "standalone"; - os = "U-Boot"; - arch = "arm"; - compression = "none"; - load = <$text_base>; - }; - optee { - description = "OP-TEE"; - data = /incbin/("$TEE"); - type = "firmware"; - arch = "arm"; - os = "tee"; - compression = "none"; - load = <$tee_base>; - entry = <$tee_base>; - }; - fdt { - description = "$(basename $dtname .dtb)"; - data = /incbin/("$dtname"); - type = "flat_dt"; - compression = "none"; - }; -__HEADER_EOF - -cat << __CONF_HEADER_EOF - }; - - configurations { - default = "conf"; - conf { - description = "$(basename $dtname .dtb)"; - firmware = "optee"; - loadables = "uboot"; - fdt = "fdt"; - }; -__CONF_HEADER_EOF - -cat << __ITS_EOF - }; -}; -__ITS_EOF diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index afb62fca78..20a00c5be7 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -5,7 +5,9 @@ choice config TARGET_CHROMEBOOK_JERRY bool "Google/Rockchip Veyron-Jerry Chromebook" + select HAS_ROM select BOARD_LATE_INIT + select ROCKCHIP_SPI_IMAGE help Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports, HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and @@ -46,6 +48,7 @@ config TARGET_CHROMEBOOK_SPEEDY config TARGET_EVB_RK3288 bool "Evb-RK3288" + select HAS_ROM select BOARD_LATE_INIT select TPL help diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 254b9c5b4d..17628f9171 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -5,6 +5,8 @@ choice config TARGET_CHROMEBOOK_BOB bool "Asus Flip C101PA Chromebook (RK3399)" + select HAS_ROM + select ROCKCHIP_SPI_IMAGE help Bob is a small RK3299-based device similar in apperance to Minnie. It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 10.1", diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index cddf4fd3d5..f148d48b6a 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -54,7 +54,8 @@ u32 spl_boot_device(void) #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ - defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) + defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) || \ + defined(CONFIG_TARGET_CHROMEBOOK_BOB) return BOOT_DEVICE_SPI; #endif if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 85526186c6..69d65c82e3 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -114,7 +114,7 @@ static int msm_clk_probe(struct udevice *dev) { struct msm_clk_priv *priv = dev_get_priv(dev); - priv->base = devfdt_get_addr(dev); + priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index 442d236255..4c2af21308 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -56,7 +56,7 @@ static int msm_pinctrl_probe(struct udevice *dev) { struct msm_pinctrl_priv *priv = dev_get_priv(dev); - priv->base = devfdt_get_addr(dev); + priv->base = dev_read_addr(dev); priv->data = (struct msm_pinctrl_data *)dev->driver_data; return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 4003c2e38b..478fd2f17d 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -1,6 +1,7 @@ if ARCH_STM32MP config SPL + select SPL_BOARD_INIT select SPL_CLK select SPL_DM select SPL_DM_SEQ_ALIAS diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index c5b8841b23..e4199dbaa5 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -560,7 +560,7 @@ static int init_device(struct stm32prog_data *data, #ifdef CONFIG_MMC case STM32PROG_MMC: mmc = find_mmc_device(dev->dev_id); - if (mmc_init(mmc)) { + if (!mmc || mmc_init(mmc)) { stm32prog_err("mmc device %d not found", dev->dev_id); return -ENODEV; } diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index 70940f01f3..8aad4be467 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -5,6 +5,7 @@ #include <common.h> #include <console.h> +#include <dm.h> #include <dfu.h> #include <malloc.h> #include <serial.h> diff --git a/arch/arm/mach-stm32mp/config.mk b/arch/arm/mach-stm32mp/config.mk index 403af2a225..c30bf482f7 100644 --- a/arch/arm/mach-stm32mp/config.mk +++ b/arch/arm/mach-stm32mp/config.mk @@ -4,10 +4,10 @@ # ifndef CONFIG_SPL -ALL-y += u-boot.stm32 +INPUTS-y += u-boot.stm32 else ifdef CONFIG_SPL_BUILD -ALL-y += u-boot-spl.stm32 +INPUTS-y += u-boot-spl.stm32 endif endif diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 382067190c..b7fcee2b36 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -154,15 +154,20 @@ static void security_init(void) */ static void dbgmcu_init(void) { - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - /* * Freeze IWDG2 if Cortex-A7 is in debug mode * done in TF-A for TRUSTED boot and * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ - if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) + if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); + } +} + +void spl_board_init(void) +{ + dbgmcu_init(); } #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ @@ -220,9 +225,10 @@ static void early_enable_caches(void) dcache_enable(); if (IS_ENABLED(CONFIG_SPL_BUILD)) - mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE, - STM32_SYSRAM_SIZE, - DCACHE_DEFAULT_OPTION); + mmu_set_region_dcache_behaviour( + ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), + round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), + DCACHE_DEFAULT_OPTION); else mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, DCACHE_DEFAULT_OPTION); @@ -241,7 +247,6 @@ int arch_cpu_init(void) timer_init(); #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) - dbgmcu_init(); #ifndef CONFIG_TFABOOT security_init(); update_bootmode(); diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index 39413e9a0e..e84bdad7bf 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -147,7 +147,7 @@ void spl_board_prepare_for_boot(void) dcache_disable(); } -void spl_board_prepare_for_boot_linux(void) +void spl_board_prepare_for_linux(void) { dcache_disable(); } diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 15e7684028..a397748b72 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -41,7 +41,6 @@ config TEGRA_PMC_SECURE config TEGRA_COMMON bool "Tegra common options" - select BINMAN select BOARD_EARLY_INIT_F select CLK select DM @@ -69,6 +68,7 @@ config TEGRA_NO_BPMP config TEGRA_ARMV7_COMMON bool "Tegra 32-bit common options" + select BINMAN select CPU_V7A select SPL select SPL_BOARD_INIT if SPL diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 2bd260e5d7..ff6b3c7e3d 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -20,14 +20,6 @@ config TARGET_MICROBLAZE_GENERIC endchoice -config STACK_SIZE - hex "Define max stack size that can be used by u-boot" - default 0x200000 - help - Defines Max stack size that can be used by u-boot so that the - initrd_high will be calculated as base stack pointer minus this - stack size. - source "board/xilinx/microblaze-generic/Kconfig" endmenu diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 997e145450..e0f6b6c4b3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -112,9 +112,11 @@ config ARCH_OCTEON select DISPLAY_CPUINFO select DMA_ADDR_T_64BIT select DM - select DM_SERIAL - select DM_GPIO select DM_ETH + select DM_GPIO + select DM_I2C + select DM_SERIAL + select DM_SPI select MIPS_L2_CACHE select MIPS_MACH_EARLY_INIT select MIPS_TUNE_OCTEON3 diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi index a7bd55f8ad..f5ad4a6213 100644 --- a/arch/mips/dts/mrvl,cn73xx.dtsi +++ b/arch/mips/dts/mrvl,cn73xx.dtsi @@ -5,6 +5,8 @@ /dts-v1/; +#include <dt-bindings/clock/octeon-clock.h> + / { #address-cells = <2>; #size-cells = <2>; @@ -38,6 +40,38 @@ #size-cells = <1>; }; + clk: clock { + compatible = "mrvl,octeon-clk"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-7890-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + nr-gpios = <32>; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pins connect to 16 consecutive CUI bits */ + interrupts = <0x03000 4>, <0x03001 4>, + <0x03002 4>, <0x03003 4>, + <0x03004 4>, <0x03005 4>, + <0x03006 4>, <0x03007 4>, + <0x03008 4>, <0x03009 4>, + <0x0300a 4>, <0x0300b 4>, + <0x0300c 4>, <0x0300d 4>, + <0x0300e 4>, <0x0300f 4>; + }; + reset: reset@1180006001600 { compatible = "mrvl,cn7xxx-rst"; reg = <0x11800 0x06001600 0x0 0x200>; @@ -60,5 +94,37 @@ reg-shift = <3>; interrupts = <0x08040 4>; }; + + i2c0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7890-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + /* INT_ST, INT_TS, INT_CORE */ + interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>; + clock-frequency = <100000>; + clocks = <&clk OCTEON_CLK_IO>; + }; + + i2c1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7890-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + /* INT_ST, INT_TS, INT_CORE */ + interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>; + clock-frequency = <100000>; + clocks = <&clk OCTEON_CLK_IO>; + }; + + spi: spi@1070000001000 { + compatible = "cavium,octeon-3010-spi"; + reg = <0x10700 0x00001000 0x0 0x100>; + interrupts = <0x05001 1>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <25000000>; + clocks = <&clk OCTEON_CLK_IO>; + }; }; }; diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts index 4e9c2de7d4..6b2e5e84bc 100644 --- a/arch/mips/dts/mrvl,octeon-ebb7304.dts +++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts @@ -5,7 +5,7 @@ /dts-v1/; -/include/ "mrvl,cn73xx.dtsi" +#include "mrvl,cn73xx.dtsi" / { model = "cavium,ebb7304"; @@ -13,6 +13,7 @@ aliases { serial0 = &uart0; + spi0 = &spi; }; chosen { @@ -94,3 +95,21 @@ &uart0 { clock-frequency = <1200000000>; }; + +&i2c0 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&i2c1 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&spi { + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <2000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/mach-mscc/include/mach/jr2/jr2.h b/arch/mips/mach-mscc/include/mach/jr2/jr2.h index 67244f63fa..3a779e7035 100644 --- a/arch/mips/mach-mscc/include/mach/jr2/jr2.h +++ b/arch/mips/mach-mscc/include/mach/jr2/jr2.h @@ -8,9 +8,6 @@ #ifndef _MSCC_JR2_H_ #define _MSCC_JR2_H_ -#include <linux/bitops.h> -#include <dm.h> - /* * Target offset base(s) */ diff --git a/arch/mips/mach-mscc/include/mach/luton/luton.h b/arch/mips/mach-mscc/include/mach/luton/luton.h index 19f02ede66..dda665fc15 100644 --- a/arch/mips/mach-mscc/include/mach/luton/luton.h +++ b/arch/mips/mach-mscc/include/mach/luton/luton.h @@ -8,9 +8,6 @@ #ifndef _MSCC_OCELOT_H_ #define _MSCC_OCELOT_H_ -#include <linux/bitops.h> -#include <dm.h> - /* * Target offset base(s) */ diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h index 2cb2135d37..72b07c33cd 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot.h @@ -8,9 +8,6 @@ #ifndef _MSCC_OCELOT_H_ #define _MSCC_OCELOT_H_ -#include <linux/bitops.h> -#include <dm.h> - /* * Target offset base(s) */ diff --git a/arch/mips/mach-mscc/include/mach/serval/serval.h b/arch/mips/mach-mscc/include/mach/serval/serval.h index 763d18fe62..a78c6e59bb 100644 --- a/arch/mips/mach-mscc/include/mach/serval/serval.h +++ b/arch/mips/mach-mscc/include/mach/serval/serval.h @@ -8,9 +8,6 @@ #ifndef _MSCC_SERVAL_H_ #define _MSCC_SERVAL_H_ -#include <linux/bitops.h> -#include <dm.h> - /* * Target offset base(s) */ diff --git a/arch/mips/mach-mscc/include/mach/servalt/servalt.h b/arch/mips/mach-mscc/include/mach/servalt/servalt.h index 9015bc7dad..4d7d0886dd 100644 --- a/arch/mips/mach-mscc/include/mach/servalt/servalt.h +++ b/arch/mips/mach-mscc/include/mach/servalt/servalt.h @@ -8,9 +8,6 @@ #ifndef _MSCC_SERVALT_H_ #define _MSCC_SERVALT_H_ -#include <linux/bitops.h> -#include <dm.h> - /* * Target offset base(s) */ diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 7f5e731a0f..e7ca9882fc 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -79,7 +79,8 @@ int arch_cpu_init_dm(void) return 0; } -static int altera_nios2_get_desc(struct udevice *dev, char *buf, int size) +static int altera_nios2_get_desc(const struct udevice *dev, char *buf, + int size) { const char *cpu_name = "Nios-II"; @@ -90,7 +91,8 @@ static int altera_nios2_get_desc(struct udevice *dev, char *buf, int size) return 0; } -static int altera_nios2_get_info(struct udevice *dev, struct cpu_info *info) +static int altera_nios2_get_info(const struct udevice *dev, + struct cpu_info *info) { info->cpu_freq = gd->cpu_clk; info->features = (1 << CPU_FEAT_L1_CACHE) | @@ -99,7 +101,7 @@ static int altera_nios2_get_info(struct udevice *dev, struct cpu_info *info) return 0; } -static int altera_nios2_get_count(struct udevice *dev) +static int altera_nios2_get_count(const struct udevice *dev) { return 1; } diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index c2c577f60c..6a2e88fed2 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -20,7 +20,7 @@ config MPC85xx select CREATE_ARCH_SYMLINK select SYS_FSL_DDR select SYS_FSL_DDR_BE - select BINMAN + select BINMAN if OF_SEPARATE imply CMD_HASH imply CMD_IRQ imply USB_EHCI_HCD if USB diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 1620fba014..192a02d347 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2002-2010 + * Copyright 2020 NXP * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ @@ -15,9 +16,6 @@ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; u32 sdhc_per_clk; -#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT) - u8 sdhc_adapter; -#endif #endif #if defined(CONFIG_MPC8xx) unsigned long brg_clk; diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index afdb4f4402..5302677ee4 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -3,6 +3,8 @@ * (C) Copyright 2019 SiFive, Inc */ +#include <dt-bindings/reset/sifive-fu540-prci.h> + / { cpus { assigned-clocks = <&prci PRCI_CLK_COREPLL>; @@ -59,6 +61,16 @@ reg = <0x0 0x2000000 0x0 0xc0000>; u-boot,dm-spl; }; + prci: clock-controller@10000000 { + #reset-cells = <1>; + resets = <&prci PRCI_RST_DDR_CTRL_N>, + <&prci PRCI_RST_DDR_AXI_N>, + <&prci PRCI_RST_DDR_AHB_N>, + <&prci PRCI_RST_DDR_PHY_N>, + <&prci PRCI_RST_GEMGXL_N>; + reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb", + "ddr_phy", "gemgxl_reset"; + }; dmc: dmc@100b0000 { compatible = "sifive,fu540-c000-ddr"; reg = <0x0 0x100b0000 0x0 0x0800 diff --git a/arch/riscv/include/asm/arch-fu540/reset.h b/arch/riscv/include/asm/arch-fu540/reset.h new file mode 100644 index 0000000000..e42797a395 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/reset.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 SiFive, Inc. + * + * Author: Sagar Kadam <sagar.kadam@sifive.com> + */ + +#ifndef __RESET_SIFIVE_H +#define __RESET_SIFIVE_H + +int sifive_reset_bind(struct udevice *dev, ulong count); + +#endif diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index e1f68cd552..c76ecc013c 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -15,6 +15,20 @@ #sound-dai-cells = <1>; }; + buttons { + compatible = "gpio-keys"; + + summer { + gpios = <&gpio_a 3 0>; + label = "summer"; + }; + + christmas { + gpios = <&gpio_a 4 0>; + label = "christmas"; + }; + }; + gpio_a: gpios@0 { u-boot,dm-pre-reloc; gpio-controller; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 3744a46603..491893a17d 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -51,6 +51,20 @@ #sound-dai-cells = <1>; }; + buttons { + compatible = "gpio-keys"; + + summer { + gpios = <&gpio_a 3 0>; + label = "summer"; + }; + + christmas { + gpios = <&gpio_a 4 0>; + label = "christmas"; + }; + }; + cros_ec: cros-ec { reg = <0 0>; compatible = "google,cros-ec-sandbox"; @@ -355,22 +369,22 @@ hog_input_active_low { gpio-hog; input; - gpios = <0 GPIO_ACTIVE_LOW>; + gpios = <10 GPIO_ACTIVE_LOW>; }; hog_input_active_high { gpio-hog; input; - gpios = <1 GPIO_ACTIVE_HIGH>; + gpios = <11 GPIO_ACTIVE_HIGH>; }; hog_output_low { gpio-hog; output-low; - gpios = <2 GPIO_ACTIVE_HIGH>; + gpios = <12 GPIO_ACTIVE_HIGH>; }; hog_output_high { gpio-hog; output-high; - gpios = <3 GPIO_ACTIVE_HIGH>; + gpios = <13 GPIO_ACTIVE_HIGH>; }; }; @@ -521,6 +535,10 @@ }; }; + chipid: chipid { + compatible = "sandbox,soc"; + }; + i2s: i2s { compatible = "sandbox,i2s"; #sound-dai-cells = <1>; diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index ff4f06ed79..a34b108fff 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -360,6 +360,8 @@ config HAVE_FSP bool "Add an Firmware Support Package binary" depends on !EFI select USE_HOB + select HAS_ROM + select ROM_NEEDS_BLOBS help Select this option to add an Firmware Support Package binary to the resulting U-Boot image. It is a binary blob which U-Boot uses @@ -519,6 +521,8 @@ config ENABLE_MRC_CACHE config HAVE_MRC bool "Add a System Agent binary" + select HAS_ROM + select ROM_NEEDS_BLOBS depends on !HAVE_FSP help Select this option to add a System Agent binary to @@ -590,8 +594,13 @@ config HAVE_REFCODE Various peripherals may fail to work. config HAVE_MICROCODE - bool + bool "Board requires a microcode binary" default y if !FSP_VERSION2 + help + Enable this if the board requires microcode to be loaded on boot. + Typically this is handed by the FSP for modern boards, but for + some older boards, it must be programmed by U-Boot, and that form + part of the image. config SMP bool "Enable Symmetric Multiprocessing" @@ -802,7 +811,7 @@ config S3_VGA_ROM_RUN graphics console won't work without VGA options ROMs. Set it to N if your kernel is only on a serial console. -config STACK_SIZE +config STACK_SIZE_RESUME hex depends on HAVE_ACPI_RESUME default 0x1000 diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c index aa7a3dbd63..0a6d2ad7a4 100644 --- a/arch/x86/cpu/apollolake/cpu.c +++ b/arch/x86/cpu/apollolake/cpu.c @@ -9,7 +9,7 @@ #include <asm/cpu_common.h> #include <asm/cpu_x86.h> -static int apl_get_info(struct udevice *dev, struct cpu_info *info) +static int apl_get_info(const struct udevice *dev, struct cpu_info *info) { return cpu_intel_get_info(info, INTEL_BCLK_MHZ); } diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c index 9130af9ce0..bbf04b5009 100644 --- a/arch/x86/cpu/apollolake/fsp_bindings.c +++ b/arch/x86/cpu/apollolake/fsp_bindings.c @@ -90,6 +90,28 @@ static void read_u32_prop(ofnode node, char *name, size_t count, u32 *dst) } /** + * read_u64_prop() - Read an u64 property from devicetree (scalar or array) + * @node: Valid node reference to read property from + * @name: Name of the property to read from + * @count: If the property is expected to be an array, this is the + * number of expected elements + * set to 0 if the property is expected to be a scalar + * @dst: Pointer to destination of where to save the value(s) read + * from devicetree + */ +static int read_u64_prop(ofnode node, char *name, size_t count, u64 *dst) +{ + if (count == 0) { + ofnode_read_u64(node, name, dst); + } else { + debug("ERROR: %s u64 arrays not supported!\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** * read_string_prop() - Read a string property from devicetree * @node: Valid node reference to read property from * @name: Name of the property to read from @@ -206,6 +228,12 @@ static int fsp_update_config_from_dtb(ofnode node, u8 *cfg, read_u32_prop(node, fspb->propname, fspb->count, (u32 *)&cfg[fspb->offset]); break; + case FSP_UINT64: + ret = read_u64_prop(node, fspb->propname, fspb->count, + (u64 *)&cfg[fspb->offset]); + if (ret) + return ret; + break; case FSP_STRING: read_string_prop(node, fspb->propname, fspb->count, (char *)&cfg[fspb->offset]); @@ -605,6 +633,17 @@ const struct fsp_binding fsp_m_bindings[] = { .offset = offsetof(struct fsp_m_config, variable_nvs_buffer_ptr), .propname = "fspm,variable-nvs-buffer-ptr", }, { + .type = FSP_UINT64, + .offset = offsetof(struct fsp_m_config, start_timer_ticker_of_pfet_assert), + .propname = "fspm,start-timer-ticker-of-pfet-assert", + }, { + .type = FSP_UINT8, .offset = offsetof(struct fsp_m_config, rt_en), + .propname = "fspm,rt-en", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_m_config, skip_pcie_power_sequence), + .propname = "fspm,skip-pcie-power-sequence", + }, { .propname = NULL } }; @@ -1794,6 +1833,18 @@ const struct fsp_binding fsp_s_bindings[] = { .count = ARRAY_SIZE_OF_MEMBER(struct fsp_s_config, port_usb20_hs_npre_drv_sel), }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, os_selection), + .propname = "fsps,os-selection", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, dptf_enabled), + .propname = "fsps,dptf-enabled", + }, { + .type = FSP_UINT8, + .offset = offsetof(struct fsp_s_config, pwm_enabled), + .propname = "fsps,pwm-enabled", + }, { .propname = NULL } }; diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 18e48ffa53..309a50a116 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -150,7 +150,7 @@ static unsigned long tsc_freq(void) return bclk * ((platform_info.lo >> 8) & 0xff); } -static int baytrail_get_info(struct udevice *dev, struct cpu_info *info) +static int baytrail_get_info(const struct udevice *dev, struct cpu_info *info) { info->cpu_freq = tsc_freq(); info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU; @@ -158,7 +158,7 @@ static int baytrail_get_info(struct udevice *dev, struct cpu_info *info) return 0; } -static int baytrail_get_count(struct udevice *dev) +static int baytrail_get_count(const struct udevice *dev) { int ecx = 0; diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index 64a1cd414f..706f68f63d 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -626,12 +626,12 @@ void cpu_set_power_limits(int power_limit_1_time) } } -static int broadwell_get_info(struct udevice *dev, struct cpu_info *info) +static int broadwell_get_info(const struct udevice *dev, struct cpu_info *info) { return cpu_intel_get_info(info, INTEL_BCLK_MHZ); } -static int broadwell_get_count(struct udevice *dev) +static int broadwell_get_count(const struct udevice *dev) { return 4; } diff --git a/arch/x86/cpu/call32.S b/arch/x86/cpu/call32.S index e185b9a42b..e641e781c0 100644 --- a/arch/x86/cpu/call32.S +++ b/arch/x86/cpu/call32.S @@ -32,8 +32,7 @@ cpu_call32: push %rdi /* 32-bit code segment */ lea compat(%rip), %rax push %rax - .byte 0x48 /* REX prefix to force 64-bit far return */ - retf + retfq .code32 compat: /* @@ -60,4 +59,4 @@ compat: /* Jump to the required target */ pushl %edi /* 32-bit code segment */ pushl %esi /* 32-bit target address */ - retf + retfl diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c index 3f2ba0881e..7e83051646 100644 --- a/arch/x86/cpu/cpu_x86.c +++ b/arch/x86/cpu/cpu_x86.c @@ -26,7 +26,7 @@ int cpu_x86_bind(struct udevice *dev) return 0; } -int cpu_x86_get_vendor(struct udevice *dev, char *buf, int size) +int cpu_x86_get_vendor(const struct udevice *dev, char *buf, int size) { const char *vendor = cpu_vendor_name(gd->arch.x86_vendor); @@ -38,7 +38,7 @@ int cpu_x86_get_vendor(struct udevice *dev, char *buf, int size) return 0; } -int cpu_x86_get_desc(struct udevice *dev, char *buf, int size) +int cpu_x86_get_desc(const struct udevice *dev, char *buf, int size) { char *ptr; @@ -52,7 +52,7 @@ int cpu_x86_get_desc(struct udevice *dev, char *buf, int size) return 0; } -int cpu_x86_get_count(struct udevice *dev) +int cpu_x86_get_count(const struct udevice *dev) { int node, cpu; int num = 0; diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 5954a24873..55f7cc2b2e 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -410,14 +410,15 @@ static int model_206ax_init(struct udevice *dev) return 0; } -static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info) +static int model_206ax_get_info(const struct udevice *dev, + struct cpu_info *info) { return cpu_intel_get_info(info, INTEL_BCLK_MHZ); return 0; } -static int model_206ax_get_count(struct udevice *dev) +static int model_206ax_get_count(const struct udevice *dev) { return 4; } diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 99bc48021e..dd6b8753de 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <fdtdec.h> #include <init.h> diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c index f40fb4d087..9ce86b379c 100644 --- a/arch/x86/cpu/qemu/cpu.c +++ b/arch/x86/cpu/qemu/cpu.c @@ -10,7 +10,7 @@ #include <qfw.h> #include <asm/cpu.h> -int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size) +int cpu_qemu_get_desc(const struct udevice *dev, char *buf, int size) { if (size < CPU_MAX_NAME_LEN) return -ENOSPC; @@ -20,7 +20,7 @@ int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size) return 0; } -static int cpu_qemu_get_count(struct udevice *dev) +static int cpu_qemu_get_count(const struct udevice *dev) { return qemu_fwcfg_online_cpus(); } diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig index 430cce184d..2fee38aed7 100644 --- a/arch/x86/cpu/quark/Kconfig +++ b/arch/x86/cpu/quark/Kconfig @@ -24,6 +24,7 @@ if INTEL_QUARK config HAVE_RMU bool "Add a Remote Management Unit (RMU) binary" + select ROM_NEEDS_BLOBS help Select this option to add a Remote Management Unit (RMU) binary to the resulting U-Boot image. It is a data block (up to 64K) of diff --git a/arch/x86/cpu/sipi_vector.S b/arch/x86/cpu/sipi_vector.S index 40cc27f1e1..fa1e6cb19a 100644 --- a/arch/x86/cpu/sipi_vector.S +++ b/arch/x86/cpu/sipi_vector.S @@ -131,12 +131,12 @@ ap_start: jnz microcode_done /* Determine if parallel microcode loading is allowed */ - cmp $0xffffffff, microcode_lock + cmpl $0xffffffff, microcode_lock je load_microcode /* Protect microcode loading */ lock_microcode: - lock bts $0, microcode_lock + lock btsl $0, microcode_lock jc lock_microcode load_microcode: @@ -154,7 +154,7 @@ load_microcode: popa /* Unconditionally unlock microcode loading */ - cmp $0xffffffff, microcode_lock + cmpl $0xffffffff, microcode_lock je microcode_done xor %eax, %eax diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index f0f8c71761..fa8106c8b8 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -75,11 +75,15 @@ u-boot { offset = <CONFIG_SYS_TEXT_BASE>; }; -# else +# elif defined(CONFIG_HAVE_MICROCODE) /* If there is no SPL then we need to put microcode in U-Boot */ u-boot-with-ucode-ptr { offset = <CONFIG_X86_OFFSET_U_BOOT>; }; +# else + u-boot-nodtb { + offset = <CONFIG_X86_OFFSET_U_BOOT>; + }; # endif #endif #ifdef CONFIG_HAVE_MICROCODE @@ -92,6 +96,8 @@ u-boot-dtb { }; #endif + fdtmap { + }; #ifdef CONFIG_HAVE_X86_FIT intel-fit { }; @@ -139,8 +145,6 @@ filename = CONFIG_FSP_FILE_S; }; #endif - fdtmap { - }; #ifdef CONFIG_HAVE_CMC intel-cmc { filename = CONFIG_CMC_FILE; diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h index 5275b75f3b..78c338e9ff 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h @@ -122,7 +122,10 @@ struct __packed fsp_m_config { /* 0x150 */ void *variable_nvs_buffer_ptr; - u8 reserved_fspm_upd[12]; + u64 start_timer_ticker_of_pfet_assert; + u8 rt_en; + u8 skip_pcie_power_sequence; + u8 reserved_fspm_upd[2]; }; /** FSP-M UPD Configuration */ diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h index 451a7a254a..be80f5db09 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h @@ -351,7 +351,10 @@ struct __packed fsp_s_config { u8 port_usb20_hs_npre_drv_sel[8]; /* 0x370 */ - u8 reserved_fsps_upd[16]; + u8 os_selection; + u8 dptf_enabled; + u8 pwm_enabled; + u8 reserved_fsps_upd[13]; }; /** struct fsps_upd - FSP-S Configuration */ @@ -563,4 +566,8 @@ struct __packed fsps_upd { #define PCIE_RP_SELECTABLE_DEEMPHASIS_6_DB 0 #define PCIE_RP_SELECTABLE_DEEMPHASIS_3_5_DB 1 +#define OS_SELECTION_WINDOWS 0 +#define OS_SELECTION_ANDROID 1 +#define OS_SELECTION_LINUX 3 + #endif diff --git a/arch/x86/include/asm/arch-apollolake/fsp_bindings.h b/arch/x86/include/asm/arch-apollolake/fsp_bindings.h index b4939519ce..a80e66bbfa 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp_bindings.h +++ b/arch/x86/include/asm/arch-apollolake/fsp_bindings.h @@ -17,6 +17,7 @@ enum conf_type { FSP_UINT8, FSP_UINT16, FSP_UINT32, + FSP_UINT64, FSP_STRING, FSP_LPDDR4_SWIZZLE, }; diff --git a/arch/x86/include/asm/cpu_x86.h b/arch/x86/include/asm/cpu_x86.h index ae8f4dcd5d..4fd5f03fdc 100644 --- a/arch/x86/include/asm/cpu_x86.h +++ b/arch/x86/include/asm/cpu_x86.h @@ -28,7 +28,7 @@ int cpu_x86_bind(struct udevice *dev); * @size: Size of string space * @return: 0 if OK, -ENOSPC if buffer is too small, other -ve on error */ -int cpu_x86_get_desc(struct udevice *dev, char *buf, int size); +int cpu_x86_get_desc(const struct udevice *dev, char *buf, int size); /** * cpu_x86_get_count() - Get the number of cores for an x86 CPU @@ -40,7 +40,7 @@ int cpu_x86_get_desc(struct udevice *dev, char *buf, int size); * @return: Number of cores if successful, * -ENOENT if not "/cpus" entry is found in the device tree */ -int cpu_x86_get_count(struct udevice *dev); +int cpu_x86_get_count(const struct udevice *dev); /** * cpu_x86_get_vendor() - Get a vendor string for an x86 CPU @@ -53,6 +53,6 @@ int cpu_x86_get_count(struct udevice *dev); * @size: Size of string space * @return: 0 if OK, -ENOSPC if buffer is too small, other -ve on error */ -int cpu_x86_get_vendor(struct udevice *dev, char *buf, int size); +int cpu_x86_get_vendor(const struct udevice *dev, char *buf, int size); #endif /* _ASM_CPU_X86_H */ diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index e5c916070c..bee0760c2d 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -12,8 +12,8 @@ * Intel interrupt router configuration mechanism * * There are two known ways of Intel interrupt router configuration mechanism - * so far. On most cases, the IRQ routing configuraiton is controlled by PCI - * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). + * so far. On most cases, the IRQ routing configuration is controlled by PCI + * configuration registers on the legacy bridge, normally PCI BDF(0, 31, 0). * On some newer platforms like BayTrail and Braswell, the IRQ routing is now * in the IBASE register block where IBASE is memory-mapped. */ @@ -36,7 +36,7 @@ struct pirq_regmap { * @link_base: link value base number * @link_num: number of PIRQ links supported * @has_regmap: has mapping table between PIRQ link and routing register offset - * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means + * @irq_mask: IRQ mask representing the 16 IRQs in 8259, bit N is 1 means * IRQ N is available to be routed * @lb_bdf: irq router's PCI bus/device/function number encoding * @ibase: IBASE register block base address diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 01d498c21e..faa819fab4 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -121,7 +121,7 @@ unsigned int install_e820_map(unsigned int max_entries, ulong stack_size; stack_size = CONFIG_IS_ENABLED(HAVE_ACPI_RESUME, - (CONFIG_STACK_SIZE), (0)); + (CONFIG_STACK_SIZE_RESUME), (0)); /* * Everything between U-Boot's stack and ram top needs to be * reserved in order for ACPI S3 resume to work. |