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-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c14
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/imx53-kp.dts4
-rw-r--r--arch/arm/dts/imx6ul-geam-u-boot.dtsi (renamed from arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi)0
-rw-r--r--arch/arm/dts/imx6ul-geam.dts (renamed from arch/arm/dts/imx6ul-geam-kit.dts)0
-rw-r--r--arch/arm/dts/imx7-colibri.dts28
-rw-r--r--arch/arm/dts/imx7s.dtsi491
-rw-r--r--arch/arm/mach-imx/cache.c42
-rw-r--r--arch/arm/mach-imx/mx7/soc.c7
-rw-r--r--arch/x86/cpu/cpu.c2
-rw-r--r--arch/x86/cpu/efi/payload.c12
-rw-r--r--arch/x86/cpu/qemu/Makefile5
-rw-r--r--arch/x86/cpu/x86_64/setjmp.S49
-rw-r--r--arch/x86/cpu/x86_64/setjmp.c19
-rw-r--r--arch/x86/include/asm/posix_types.h3
-rw-r--r--arch/x86/include/asm/setjmp.h17
16 files changed, 480 insertions, 215 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 8fef4019af..7818d72908 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -15,7 +15,7 @@
#include "mxs_init.h"
-static uint32_t dram_vals[] = {
+__weak uint32_t mxs_dram_vals[] = {
/*
* i.MX28 DDR2 at 200MHz
*/
@@ -100,11 +100,11 @@ static void initialize_dram_values(void)
int i;
debug("SPL: Setting mx28 board specific SDRAM parameters\n");
- mxs_adjust_memory_params(dram_vals);
+ mxs_adjust_memory_params(mxs_dram_vals);
debug("SPL: Applying SDRAM parameters\n");
- for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
- writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++)
+ writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
#else
static void initialize_dram_values(void)
@@ -112,7 +112,7 @@ static void initialize_dram_values(void)
int i;
debug("SPL: Setting mx23 board specific SDRAM parameters\n");
- mxs_adjust_memory_params(dram_vals);
+ mxs_adjust_memory_params(mxs_dram_vals);
/*
* HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
@@ -124,10 +124,10 @@ static void initialize_dram_values(void)
* So skip the initialization of these HW_DRAM_CTL registers.
*/
debug("SPL: Applying SDRAM parameters\n");
- for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
+ for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) {
if (i == 8 || i == 27 || i == 28 || i == 35)
continue;
- writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
/*
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 493652ea8c..baad87d4d7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -425,7 +425,7 @@ dtb-$(CONFIG_MX6SX) += \
imx6sx-sdb.dtb
dtb-$(CONFIG_MX6UL) += \
- imx6ul-geam-kit.dtb \
+ imx6ul-geam.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-nand.dtb \
imx6ul-opos6uldev.dtb
diff --git a/arch/arm/dts/imx53-kp.dts b/arch/arm/dts/imx53-kp.dts
index fd64a9f2f6..ca98fb59c6 100644
--- a/arch/arm/dts/imx53-kp.dts
+++ b/arch/arm/dts/imx53-kp.dts
@@ -86,6 +86,10 @@
MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
/* BOOSTER_OFF */
MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
+ /* LCD BACKLIGHT */
+ MX53_PAD_GPIO_1__GPIO1_1 0x1e4
+ /* KEY1 GPIO */
+ MX53_PAD_EIM_RW__GPIO2_26 0x1e4
>;
};
diff --git a/arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi b/arch/arm/dts/imx6ul-geam-u-boot.dtsi
index 3141a07f04..3141a07f04 100644
--- a/arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx6ul-geam-u-boot.dtsi
diff --git a/arch/arm/dts/imx6ul-geam-kit.dts b/arch/arm/dts/imx6ul-geam.dts
index 07c21cb0a2..07c21cb0a2 100644
--- a/arch/arm/dts/imx6ul-geam-kit.dts
+++ b/arch/arm/dts/imx6ul-geam.dts
diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts
index a2cade762a..dca501be25 100644
--- a/arch/arm/dts/imx7-colibri.dts
+++ b/arch/arm/dts/imx7-colibri.dts
@@ -16,6 +16,15 @@
};
};
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ fsl,use-minimum-ecc;
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
@@ -48,6 +57,25 @@
};
&iomuxc {
+ pinctrl_gpmi_nand: gpmi-nand-grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CLK__NAND_CLE 0x71
+ MX7D_PAD_SD3_CMD__NAND_ALE 0x71
+ MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
+ MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
+ MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
+ MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
+ MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
+ MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
+ MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
+ MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
+ MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
+ MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
+ MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
+ MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
+ >;
+ };
+
pinctrl_i2c4: i2c4-grp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi
index a7d48e785d..4d42335c0d 100644
--- a/arch/arm/dts/imx7s.dtsi
+++ b/arch/arm/dts/imx7s.dtsi
@@ -42,6 +42,7 @@
*/
#include <dt-bindings/clock/imx7d-clock.h>
+#include <dt-bindings/power/imx7-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -57,7 +58,7 @@
* Also for U-Boot there must be a pre-existing /memory node.
*/
chosen {};
- memory { device_type = "memory"; reg = <0 0>; };
+ memory { device_type = "memory"; };
aliases {
gpio0 = &gpio1;
@@ -115,11 +116,77 @@
clock-output-names = "osc";
};
+ usbphynop1: usbphynop1 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clks IMX7D_USB_PHY1_CLK>;
+ clock-names = "main_clk";
+ #phy-cells = <0>;
+ };
+
+ usbphynop3: usbphynop3 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
+ clock-names = "main_clk";
+ #phy-cells = <0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupt-parent = <&gpc>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ };
+
+ replicator {
+ /*
+ * non-configurable replicators don't show up on the
+ * AMBA bus. As such no need to add "arm,primecell"
+ */
+ compatible = "arm,coresight-replicator";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+
+ /* replicator input port */
+ port@2 {
+ reg = <0>;
+ replicator_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- interrupt-parent = <&intc>;
+ interrupt-parent = <&gpc>;
ranges;
funnel@30041000 {
@@ -259,62 +326,18 @@
};
};
- replicator {
- /*
- * non-configurable replicators don't show up on the
- * AMBA bus. As such no need to add "arm,primecell"
- */
- compatible = "arm,coresight-replicator";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* replicator output ports */
- port@0 {
- reg = <0>;
- replicator_out_port0: endpoint {
- remote-endpoint = <&tpiu_in_port>;
- };
- };
-
- port@1 {
- reg = <1>;
- replicator_out_port1: endpoint {
- remote-endpoint = <&etr_in_port>;
- };
- };
-
- /* replicator input port */
- port@2 {
- reg = <0>;
- replicator_in_port0: endpoint {
- slave-mode;
- remote-endpoint = <&etf_out_port>;
- };
- };
- };
- };
-
intc: interrupt-controller@31001000 {
compatible = "arm,cortex-a7-gic";
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
+ interrupt-parent = <&intc>;
reg = <0x31001000 0x1000>,
<0x31002000 0x2000>,
<0x31004000 0x2000>,
<0x31006000 0x2000>;
};
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
aips1: aips-bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
@@ -482,20 +505,49 @@
status = "disabled";
};
+ kpp: kpp@30320000 {
+ compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
+ reg = <0x30320000 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_KPP_ROOT_CLK>;
+ status = "disabled";
+ };
+
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
- compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx7d-iomuxc-gpr",
+ "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
ocotp: ocotp-ctrl@30350000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "fsl,imx7d-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clks IMX7D_OCOTP_CLK>;
+
+ tempmon_calib: calib@3c {
+ reg = <0x3c 0x4>;
+ };
+
+ tempmon_temp_grade: temp-grade@10 {
+ reg = <0x10 0x4>;
+ };
+ };
+
+ tempmon: tempmon {
+ compatible = "fsl,imx7d-tempmon";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon =<&anatop>;
+ nvmem-cells = <&tempmon_calib>,
+ <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
};
anatop: anatop@30360000 {
@@ -504,8 +556,11 @@
reg = <0x30360000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- reg_1p0d: regulator-vdd1p0d {
+ reg_1p0d: regulator-vdd1p0d@30360210 {
+ reg = <0x30360210>;
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p0d";
regulator-min-microvolt = <800000>;
@@ -516,6 +571,7 @@
anatop-min-bit-val = <8>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1200000>;
+ anatop-enable-bit = <0>;
};
};
@@ -529,12 +585,15 @@
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
};
snvs_poweroff: snvs-poweroff {
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
+ value = <0x60>;
mask = <0x60>;
};
@@ -558,11 +617,32 @@
};
src: src@30390000 {
- compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
+ compatible = "fsl,imx7d-src", "syscon";
reg = <0x30390000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx7d-gpc";
+ reg = <0x303a0000 0x10000>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&intc>;
+ #power-domain-cells = <1>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_pcie_phy: pgc-power-domain@1 {
+ #power-domain-cells = <0>;
+ reg = <1>;
+ power-supply = <&reg_1p0d>;
+ };
+ };
+ };
};
aips2: aips-bus@30400000 {
@@ -609,7 +689,7 @@
clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
<&clks IMX7D_PWM1_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -620,7 +700,7 @@
clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
<&clks IMX7D_PWM2_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -631,7 +711,7 @@
clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
<&clks IMX7D_PWM3_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -642,7 +722,7 @@
clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
<&clks IMX7D_PWM4_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -664,118 +744,156 @@
reg = <0x30800000 0x400000>;
ranges;
- ecspi1: ecspi@30820000 {
+ spba-bus@30800000 {
+ compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
- reg = <0x30820000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
- <&clks IMX7D_ECSPI1_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ #size-cells = <1>;
+ reg = <0x30800000 0x100000>;
+ ranges;
+
+ ecspi1: ecspi@30820000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
+ <&clks IMX7D_ECSPI1_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- ecspi2: ecspi@30830000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
- reg = <0x30830000 0x10000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
- <&clks IMX7D_ECSPI2_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ ecspi2: ecspi@30830000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30830000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
+ <&clks IMX7D_ECSPI2_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- ecspi3: ecspi@30840000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
- reg = <0x30840000 0x10000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
- <&clks IMX7D_ECSPI3_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ ecspi3: ecspi@30840000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30840000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
+ <&clks IMX7D_ECSPI3_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- uart1: serial@30860000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_UART1_ROOT_CLK>,
- <&clks IMX7D_UART1_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ uart1: serial@30860000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART1_ROOT_CLK>,
+ <&clks IMX7D_UART1_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- uart2: serial@30890000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_UART2_ROOT_CLK>,
- <&clks IMX7D_UART2_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ uart2: serial@30890000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART2_ROOT_CLK>,
+ <&clks IMX7D_UART2_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- uart3: serial@30880000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_UART3_ROOT_CLK>,
- <&clks IMX7D_UART3_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ uart3: serial@30880000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART3_ROOT_CLK>,
+ <&clks IMX7D_UART3_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- sai1: sai@308a0000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
- reg = <0x308a0000 0x10000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_SAI1_IPG_CLK>,
- <&clks IMX7D_SAI1_ROOT_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "rx", "tx";
- dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
- status = "disabled";
- };
+ sai1: sai@308a0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308a0000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI1_IPG_CLK>,
+ <&clks IMX7D_SAI1_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
+ status = "disabled";
+ };
- sai2: sai@308b0000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
- reg = <0x308b0000 0x10000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_SAI2_IPG_CLK>,
- <&clks IMX7D_SAI2_ROOT_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "rx", "tx";
- dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
- status = "disabled";
+ sai2: sai@308b0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308b0000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI2_IPG_CLK>,
+ <&clks IMX7D_SAI2_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
+ status = "disabled";
+ };
+
+ sai3: sai@308c0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308c0000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI3_IPG_CLK>,
+ <&clks IMX7D_SAI3_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
+ status = "disabled";
+ };
};
- sai3: sai@308c0000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
- reg = <0x308c0000 0x10000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_SAI3_IPG_CLK>,
- <&clks IMX7D_SAI3_ROOT_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "rx", "tx";
- dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
- status = "disabled";
+ crypto: caam@30900000 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30900000 0x40000>;
+ ranges = <0 0x30900000 0x40000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CAAM_CLK>,
+ <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
+ clock-names = "ipg", "aclk";
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr1@3000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
flexcan1: can@30a00000 {
@@ -918,24 +1036,12 @@
reg = <0x30b30200 0x200>;
};
- usbphynop1: usbphynop1 {
- compatible = "usb-nop-xceiv";
- clocks = <&clks IMX7D_USB_PHY1_CLK>;
- clock-names = "main_clk";
- };
-
- usbphynop3: usbphynop3 {
- compatible = "usb-nop-xceiv";
- clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
- clock-names = "main_clk";
- };
-
usdhc1: usdhc@30b40000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>,
+ clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+ <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
<&clks IMX7D_USDHC1_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
@@ -946,8 +1052,8 @@
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>,
+ clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+ <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
<&clks IMX7D_USDHC2_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
@@ -958,8 +1064,8 @@
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>,
+ clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+ <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
<&clks IMX7D_USDHC3_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
@@ -980,9 +1086,11 @@
fec1: ethernet@30be0000 {
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ interrupt-names = "int0", "int1", "int2", "pps";
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
@@ -995,5 +1103,36 @@
status = "disabled";
};
};
+
+ dma_apbh: dma-apbh@33000000 {
+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x33000000 0x2000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+ };
+
+ gpmi: gpmi-nand@33002000{
+ compatible = "fsl,imx7d-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
+ <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+ clock-names = "gpmi_io", "gpmi_bch_apb";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
+ };
};
};
diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index 11f90ed8a2..82257f3280 100644
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -9,6 +9,34 @@
#include <asm/io.h>
#include <asm/mach-imx/sys_proto.h>
+static void enable_ca7_smp(void)
+{
+ u32 val;
+
+ /* Read MIDR */
+ asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val));
+ val = (val >> 4);
+ val &= 0xf;
+
+ /* Only set the SMP for Cortex A7 */
+ if (val == 0x7) {
+ /* Read auxiliary control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
+
+ if (val & (1 << 6))
+ return;
+
+ /* Enable SMP */
+ val |= (1 << 6);
+
+ /* Write auxiliary control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
+
+ DSB;
+ ISB;
+ }
+}
+
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
@@ -20,6 +48,9 @@ void enable_caches(void)
/* Avoid random hang when download by usb */
invalidate_dcache_all();
+ /* Set ACTLR.SMP bit for Cortex-A7 */
+ enable_ca7_smp();
+
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
@@ -31,6 +62,17 @@ void enable_caches(void)
IRAM_SIZE,
option);
}
+#else
+void enable_caches(void)
+{
+ /*
+ * Set ACTLR.SMP bit for Cortex-A7, even if the caches are
+ * disabled by u-boot
+ */
+ enable_ca7_smp();
+
+ puts("WARNING: Caches not enabled\n");
+}
#endif
#ifndef CONFIG_SYS_L2CACHE_OFF
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index f1dea66d60..2aca24bbb0 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -280,13 +280,6 @@ const struct boot_mode soc_boot_modes[] = {
void s_init(void)
{
-#if !defined CONFIG_SPL_BUILD
- /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #1 << 6\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
-#endif
/* clock configuration. */
clock_init();
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index db36553d05..6aefa12a7c 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -193,7 +193,7 @@ void show_boot_progress(int val)
outb(val, POST_PORT);
}
-#ifndef CONFIG_SYS_COREBOOT
+#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
/*
* Implement a weak default function for boards that optionally
* need to clean up the system before jumping to the kernel.
diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c
index 9fd9f57776..4649bfe86e 100644
--- a/arch/x86/cpu/efi/payload.c
+++ b/arch/x86/cpu/efi/payload.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <efi.h>
#include <errno.h>
+#include <usb.h>
#include <asm/post.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -108,11 +109,10 @@ int dram_init_banksize(void)
desc < end && num_banks < CONFIG_NR_DRAM_BANKS;
desc = efi_get_next_mem_desc(map, desc)) {
/*
- * We only use conventional memory below 4GB, and ignore
+ * We only use conventional memory and ignore
* anything less than 1MB.
*/
if (desc->type != EFI_CONVENTIONAL_MEMORY ||
- desc->physical_start >= 1ULL << 32 ||
(desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20)
continue;
gd->bd->bi_dram[num_banks].start = desc->physical_start;
@@ -160,3 +160,11 @@ int reserve_arch(void)
return 0;
}
+
+int last_stage_init(void)
+{
+ /* start usb so that usb keyboard can be used as input device */
+ usb_init();
+
+ return 0;
+}
diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 1761244178..b7dd5bd46c 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -2,6 +2,9 @@
#
# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
-obj-y += car.o dram.o
+ifndef CONFIG_$(SPL_)X86_64
+obj-y += car.o
+endif
+obj-y += dram.o
obj-y += qemu.o
obj-$(CONFIG_QFW) += cpu.o e820.o
diff --git a/arch/x86/cpu/x86_64/setjmp.S b/arch/x86/cpu/x86_64/setjmp.S
new file mode 100644
index 0000000000..97b812854c
--- /dev/null
+++ b/arch/x86/cpu/x86_64/setjmp.S
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Intel Corporation
+ *
+ * See arch/x86/include/asm/setjmp.h for jmp_buf format
+ */
+
+#include <linux/linkage.h>
+
+.text
+.align 8
+
+ENTRY(setjmp)
+
+ pop %rcx
+ movq %rcx, (%rdi) /* Return address */
+ movq %rsp, 8(%rdi)
+ movq %rbp, 16(%rdi)
+ movq %rbx, 24(%rdi)
+ movq %r12, 32(%rdi)
+ movq %r13, 40(%rdi)
+ movq %r14, 48(%rdi)
+ movq %r15, 56(%rdi)
+ xorq %rax, %rax /* Direct invocation returns 0 */
+ jmpq *%rcx
+
+ENDPROC(setjmp)
+
+.align 8
+
+ENTRY(longjmp)
+
+ movq (%rdi), %rcx /* Return address */
+ movq 8(%rdi), %rsp
+ movq 16(%rdi), %rbp
+ movq 24(%rdi), %rbx
+ movq 32(%rdi), %r12
+ movq 40(%rdi), %r13
+ movq 48(%rdi), %r14
+ movq 56(%rdi), %r15
+
+ movq %rsi, %rax /* Value to be returned by setjmp() */
+ testq %rax, %rax /* cannot be 0 in this case */
+ jnz 1f
+ incq %rax /* Return 1 instead */
+1:
+ jmpq *%rcx
+
+ENDPROC(longjmp)
diff --git a/arch/x86/cpu/x86_64/setjmp.c b/arch/x86/cpu/x86_64/setjmp.c
deleted file mode 100644
index 5d4a74a571..0000000000
--- a/arch/x86/cpu/x86_64/setjmp.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016 Google, Inc
- */
-
-#include <common.h>
-#include <asm/setjmp.h>
-
-int setjmp(struct jmp_buf_data *jmp_buf)
-{
- printf("WARNING: setjmp() is not supported\n");
-
- return 0;
-}
-
-void longjmp(struct jmp_buf_data *jmp_buf, int val)
-{
- printf("WARNING: longjmp() is not supported\n");
-}
diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h
index 717f6cb8e0..dbcea7f47f 100644
--- a/arch/x86/include/asm/posix_types.h
+++ b/arch/x86/include/asm/posix_types.h
@@ -16,7 +16,8 @@ typedef int __kernel_pid_t;
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
-#if CONFIG_IS_ENABLED(X86_64)
+/* checking against __x86_64__ covers both 64-bit EFI stub and 64-bit U-Boot */
+#if defined(__x86_64__)
typedef unsigned long __kernel_size_t;
typedef long __kernel_ssize_t;
#else
diff --git a/arch/x86/include/asm/setjmp.h b/arch/x86/include/asm/setjmp.h
index f25975fe1d..49c36c1cc8 100644
--- a/arch/x86/include/asm/setjmp.h
+++ b/arch/x86/include/asm/setjmp.h
@@ -8,6 +8,21 @@
#ifndef __setjmp_h
#define __setjmp_h
+#ifdef CONFIG_X86_64
+
+struct jmp_buf_data {
+ unsigned long __rip;
+ unsigned long __rsp;
+ unsigned long __rbp;
+ unsigned long __rbx;
+ unsigned long __r12;
+ unsigned long __r13;
+ unsigned long __r14;
+ unsigned long __r15;
+};
+
+#else
+
struct jmp_buf_data {
unsigned int __ebx;
unsigned int __esp;
@@ -17,6 +32,8 @@ struct jmp_buf_data {
unsigned int __eip;
};
+#endif
+
int setjmp(struct jmp_buf_data *jmp_buf);
void longjmp(struct jmp_buf_data *jmp_buf, int val);
generated by cgit (git 2.34.1) at 2025-01-20 22:41:31 +0000