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-rw-r--r--board/atmel/common/video_display.c2
-rw-r--r--board/atmel/sam9x60ek/Kconfig12
-rw-r--r--board/atmel/sam9x60ek/MAINTAINERS9
-rw-r--r--board/atmel/sam9x60ek/Makefile7
-rw-r--r--board/atmel/sam9x60ek/sam9x60ek.c125
-rw-r--r--board/atmel/sama5d27_wlsom1_ek/Kconfig15
-rw-r--r--board/atmel/sama5d27_wlsom1_ek/MAINTAINERS8
-rw-r--r--board/atmel/sama5d27_wlsom1_ek/Makefile7
-rw-r--r--board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c252
9 files changed, 436 insertions, 1 deletions
diff --git a/board/atmel/common/video_display.c b/board/atmel/common/video_display.c
index c7d3f8addc..cc051d2e0c 100644
--- a/board/atmel/common/video_display.c
+++ b/board/atmel/common/video_display.c
@@ -23,7 +23,7 @@ int at91_video_show_board_info(void)
int i;
u32 len = 0;
char buf[255];
- char *corp = "2017 Microchip Technology Inc.\n";
+ char *corp = "Microchip Technology Inc.\n";
char temp[32];
struct udevice *dev, *con;
const char *s;
diff --git a/board/atmel/sam9x60ek/Kconfig b/board/atmel/sam9x60ek/Kconfig
new file mode 100644
index 0000000000..32fae2108e
--- /dev/null
+++ b/board/atmel/sam9x60ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAM9X60EK
+
+config SYS_BOARD
+ default "sam9x60ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_CONFIG_NAME
+ default "sam9x60ek"
+
+endif
diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS
new file mode 100644
index 0000000000..d209249c2e
--- /dev/null
+++ b/board/atmel/sam9x60ek/MAINTAINERS
@@ -0,0 +1,9 @@
+SAM9X60EK BOARD
+M: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
+S: Maintained
+F: board/atmel/sam9x60ek/
+F: include/configs/sam9x60ek.h
+F: configs/sam9x60ek_mmc_defconfig
+F: configs/sam9x60ek_nandflash_defconfig
+F: configs/sam9x60ek_qspiflash_defconfig
diff --git a/board/atmel/sam9x60ek/Makefile b/board/atmel/sam9x60ek/Makefile
new file mode 100644
index 0000000000..12a406a3bb
--- /dev/null
+++ b/board/atmel/sam9x60ek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+#
+# Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
+
+obj-y += sam9x60ek.o
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c
new file mode 100644
index 0000000000..182b3aeed7
--- /dev/null
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_sfr.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <debug_uart.h>
+#include <asm/mach-types.h>
+
+extern void at91_pda_detect(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void at91_prepare_cpu_var(void);
+
+#ifdef CONFIG_CMD_NAND
+static void sam9x60ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+ unsigned int csa;
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
+
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+ /* Enable CS3 */
+ csa = readl(&sfr->ebicsa);
+ csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
+
+ /* Configure IO drive */
+ csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
+
+ writel(csa, &sfr->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
+ AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
+ &smc->cs[3].mode);
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ at91_prepare_cpu_var();
+
+ at91_pda_detect();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ sam9x60ek_nand_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
diff --git a/board/atmel/sama5d27_wlsom1_ek/Kconfig b/board/atmel/sama5d27_wlsom1_ek/Kconfig
new file mode 100644
index 0000000000..4b192b0849
--- /dev/null
+++ b/board/atmel/sama5d27_wlsom1_ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D27_WLSOM1_EK
+
+config SYS_BOARD
+ default "sama5d27_wlsom1_ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d27_wlsom1_ek"
+
+endif
diff --git a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS
new file mode 100644
index 0000000000..ff68cf01a3
--- /dev/null
+++ b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS
@@ -0,0 +1,8 @@
+SAMA5D27 WLSOM1 EK BOARD
+M: Nicolas Ferre <nicolas.ferre@microchip.com>
+M: Eugen Hristev <eugen.hristev@microchip.com>
+S: Maintained
+F: board/atmel/sama5d27_wlsom1_ek/
+F: include/configs/sama5d27_wlsom1_ek.h
+F: configs/sama5d27_wlsom1_ek_mmc_defconfig
+F: configs/sama5d27_wlsom1_ek_qspiflash_defconfig
diff --git a/board/atmel/sama5d27_wlsom1_ek/Makefile b/board/atmel/sama5d27_wlsom1_ek/Makefile
new file mode 100644
index 0000000000..cf827ae5e3
--- /dev/null
+++ b/board/atmel/sama5d27_wlsom1_ek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+#
+# Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
+
+obj-y += sama5d27_wlsom1_ek.o
diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
new file mode 100644
index 0000000000..fda06c824d
--- /dev/null
+++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+extern void at91_pda_detect(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_DM_VIDEO
+ at91_video_show_board_info();
+#endif
+ at91_pda_detect();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart0_hw_init(void)
+{
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
+
+ at91_periph_clk_enable(ATMEL_ID_UART0);
+}
+
+void board_debug_uart_init(void)
+{
+ board_uart0_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+
+static void board_leds_init(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 6, 0); /* RED */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 7, 1); /* GREEN */
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 8, 0); /* BLUE */
+}
+
+#ifdef CONFIG_SD_BOOT
+void spl_mmc_init(void)
+{
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */
+
+ at91_periph_clk_enable(ATMEL_ID_SDMMC0);
+}
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+void spl_qspi_init(void)
+{
+ atmel_pio4_set_d_periph(AT91_PIO_PORTB, 5, 0); /* SCK */
+ atmel_pio4_set_d_periph(AT91_PIO_PORTB, 6, 0); /* CS */
+ atmel_pio4_set_d_periph(AT91_PIO_PORTB, 7, 0); /* IO0 */
+ atmel_pio4_set_d_periph(AT91_PIO_PORTB, 8, 0); /* IO1 */
+ atmel_pio4_set_d_periph(AT91_PIO_PORTB, 9, 0); /* IO2 */
+ atmel_pio4_set_d_periph(AT91_PIO_PORTB, 10, 0); /* IO3 */
+
+ at91_periph_clk_enable(ATMEL_ID_QSPI1);
+}
+#endif
+
+void spl_board_init(void)
+{
+ board_leds_init();
+#ifdef CONFIG_SD_BOOT
+ spl_mmc_init();
+#endif
+#ifdef CONFIG_QSPI_BOOT
+ spl_qspi_init();
+#endif
+}
+
+void spl_display_print(void)
+{
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+ ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM);
+
+ ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
+ ATMEL_MPDDRC_CR_NR_ROW_14 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_ZQ_SHORT |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+ ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3);
+
+ /*
+ * The AD220032D average time between REFRESH commands (Trefi): 3.9us
+ * 3.9us * 164MHz = 639.6 = 0x27F.
+ */
+ ddrc->rtr = 0x27f;
+ /* Enable Adjust Refresh Rate */
+ ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF;
+
+ ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+ (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+ (11 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+ (2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+ (2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+ (5 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+ ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+ (0 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+ (23 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+ (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+ ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+ (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+ (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+ (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+ (10 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+
+ ddrc->tim_cal = ATMEL_MPDDRC_CALR_ZQCS(15);
+
+ /*
+ * According to the sama5d2 datasheet and the following values:
+ * T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s
+ * Warning: note that the values T driftrate and V driftrate are dependent on
+ * the application environment.
+ * ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s
+ * If Trefi is 3.9us, we have: 400000 / 3.9 = 102564: we can maximize
+ * this timer to 0xFFFE.
+ */
+ ddrc->cal_mr4 = ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(0xFFFE);
+
+ /*
+ * MR4 Read interval is dependent on the application environment.
+ * Here, we want to maximize this value as temperature is supposed
+ * to vary slowly in the application chosen.
+ * If Trefi is 3.9us, we have:
+ * (0xFFFE) 65534 x 3.9 = 0.25s between MR4 reads.
+ */
+ ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ struct atmel_mpddrc_config ddrc_config;
+ u32 reg;
+
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ writel(AT91_PMC_DDR, &pmc->scer);
+
+ ddrc_conf(&ddrc_config);
+
+ reg = readl(&mpddrc->io_calibr);
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48;
+ reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+ reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+ writel(reg, &mpddrc->io_calibr);
+
+ writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
+ &mpddrc->rd_data_path);
+
+ lpddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+}
+
+void at91_pmc_init(void)
+{
+ u32 tmp;
+
+ /*
+ * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
+ * so we need to slow down and configure MCKR accordingly.
+ * This is why we have a special flavor of the switching function.
+ */
+ tmp = AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_MAIN;
+ at91_mck_init_down(tmp);
+
+ tmp = AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(40) |
+ AT91_PMC_PLLXR_DIV(1);
+ at91_plla_init(tmp);
+
+ tmp = AT91_PMC_MCKR_H32MXDIV |
+ AT91_PMC_MCKR_PLLADIV_2 |
+ AT91_PMC_MCKR_MDIV_3 |
+ AT91_PMC_MCKR_CSS_PLLA;
+ at91_mck_init(tmp);
+}
+#endif
generated by cgit (git 2.34.1) at 2025-01-07 18:23:45 +0000