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-rw-r--r--board/compulab/cm_t335/Makefile10
-rw-r--r--board/compulab/cm_t335/cm_t335.c162
-rw-r--r--board/compulab/cm_t335/mux.c117
-rw-r--r--board/compulab/cm_t335/spl.c114
-rw-r--r--board/compulab/cm_t335/u-boot.lds101
-rw-r--r--board/compulab/cm_t35/cm_t35.c32
-rw-r--r--board/compulab/common/Makefile2
-rw-r--r--board/compulab/common/eeprom.h2
-rw-r--r--board/compulab/common/omap3_display.c46
-rw-r--r--board/compulab/trimslice/Makefile2
10 files changed, 580 insertions, 8 deletions
diff --git a/board/compulab/cm_t335/Makefile b/board/compulab/cm_t335/Makefile
new file mode 100644
index 0000000000..0e6e96e039
--- /dev/null
+++ b/board/compulab/cm_t335/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/
+#
+# Author: Ilya Ledvich <ilya@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += $(BOARD).o
+obj-$(CONFIG_SPL_BUILD) += mux.o spl.o
diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c
new file mode 100644
index 0000000000..01019e8eb2
--- /dev/null
+++ b/board/compulab/cm_t335/cm_t335.c
@@ -0,0 +1,162 @@
+/*
+ * Board functions for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <cpsw.h>
+
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware_am33xx.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ gpmc_init();
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+#endif
+ return 0;
+}
+
+#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slave = {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ .phy_if = PHY_INTERFACE_MODE_RGMII,
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = &cpsw_slave,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+/* PHY reset GPIO */
+#define GPIO_PHY_RST GPIO_PIN(3, 7)
+
+static void board_phy_init(void)
+{
+ gpio_request(GPIO_PHY_RST, "phy_rst");
+ gpio_direction_output(GPIO_PHY_RST, 0);
+ mdelay(2);
+ gpio_set_value(GPIO_PHY_RST, 1);
+ mdelay(2);
+}
+
+static void get_efuse_mac_addr(uchar *enetaddr)
+{
+ uint32_t mac_hi, mac_lo;
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ enetaddr[0] = mac_hi & 0xFF;
+ enetaddr[1] = (mac_hi & 0xFF00) >> 8;
+ enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
+ enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
+ enetaddr[4] = mac_lo & 0xFF;
+ enetaddr[5] = (mac_lo & 0xFF00) >> 8;
+}
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int handle_mac_address(void)
+{
+ uchar enetaddr[6];
+ int rv;
+
+ rv = eth_getenv_enetaddr("ethaddr", enetaddr);
+ if (rv)
+ return 0;
+
+ rv = cl_eeprom_read_mac_addr(enetaddr);
+ if (rv)
+ get_efuse_mac_addr(enetaddr);
+
+ if (!is_valid_ether_addr(enetaddr))
+ return -1;
+
+ return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
+#define AR8051_PHY_DEBUG_DATA_REG 0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
+#define AR8051_RGMII_TX_CLK_DLY 0x100
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+ const char *devname;
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+ rv = handle_mac_address();
+ if (rv)
+ printf("No MAC address found!\n");
+
+ writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
+
+ board_phy_init();
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+
+ /*
+ * CPSW RGMII Internal Delay Mode is not supported in all PVT
+ * operating points. So we must set the TX clock delay feature
+ * in the AR8051 PHY. Since we only support a single ethernet
+ * device, we only do this for the first instance.
+ */
+ devname = miiphy_get_current_dev();
+
+ miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
+ AR8051_DEBUG_RGMII_CLK_DLY_REG);
+ miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
+ AR8051_RGMII_TX_CLK_DLY);
+ return n;
+}
+#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */
diff --git a/board/compulab/cm_t335/mux.c b/board/compulab/cm_t335/mux.c
new file mode 100644
index 0000000000..7d2beb01e5
--- /dev/null
+++ b/board/compulab/cm_t335/mux.c
@@ -0,0 +1,117 @@
+/*
+ * Pinmux configuration for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
+ {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ /* I2C_DATA */
+ {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+ /* I2C_SCLK */
+ {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
+static struct module_pin_mux eth_phy_rst_pin_mux[] = {
+ {OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */
+ {-1},
+};
+
+static struct module_pin_mux status_led_pin_mux[] = {
+ {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */
+ {-1},
+};
+
+void set_uart_mux_conf(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void set_mux_conf_regs(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(rgmii1_pin_mux);
+ configure_module_pin_mux(eth_phy_rst_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(nand_pin_mux);
+ configure_module_pin_mux(status_led_pin_mux);
+}
diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c
new file mode 100644
index 0000000000..b3b150a577
--- /dev/null
+++ b/board/compulab/cm_t335/spl.c
@@ -0,0 +1,114 @@
+/*
+ * SPL specific code for Compulab CM-T335 board
+ *
+ * Board functions for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clocks_am33xx.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware_am33xx.h>
+#include <asm/sizes.h>
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41J128MJT125_RD_DQS,
+ .datawdsratio0 = MT41J128MJT125_WR_DQS,
+ .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
+ .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41J128MJT125_RATIO,
+ .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41J128MJT125_RATIO,
+ .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41J128MJT125_RATIO,
+ .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41J128MJT125_EMIF_SDCFG,
+ .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
+ .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
+ .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
+ .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
+ .zq_config = MT41J128MJT125_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
+
+const struct dpll_params dpll_ddr = {
+/* M N M2 M3 M4 M5 M6 */
+ 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+ /* Get the frequency */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr;
+}
+
+static void probe_sdram_size(long size)
+{
+ switch (size) {
+ case SZ_512M:
+ ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
+ break;
+ case SZ_256M:
+ ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
+ break;
+ case SZ_128M:
+ ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
+ break;
+ default:
+ puts("Failed configuring DRAM, resetting...\n\n");
+ reset_cpu(0);
+ }
+ debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
+ config_ddr(303, &ioregs, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+
+void sdram_init(void)
+{
+ long size = SZ_1G;
+
+ do {
+ size = size / 2;
+ probe_sdram_size(size);
+ } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
+
+ return;
+}
diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds
new file mode 100644
index 0000000000..1b609a249a
--- /dev/null
+++ b/board/compulab/cm_t335/u-boot.lds
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ CPUDIR/start.o (.text*)
+ board/compulab/cm_t335/built-in.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ _end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index b9a996594f..00bcf41bb3 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -105,6 +105,22 @@ static inline int splash_load_from_nand(void)
}
#endif /* CONFIG_CMD_NAND */
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->mr = MICRON_V_MR_165;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+}
+#endif
+
int splash_screen_prepare(void)
{
char *env_splashimage_value;
@@ -268,6 +284,9 @@ static void cm_t3x_set_common_muxconf(void)
/* DVI enable */
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
+ /* DataImage backlight */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
+
/* CM-T3x Ethernet */
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
@@ -374,6 +393,15 @@ static void cm_t3x_set_common_muxconf(void)
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
+
+ /* SPI */
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
+
+ /* display controls */
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
}
static void cm_t35_set_muxconf(void)
@@ -428,7 +456,7 @@ void set_muxconf_regs(void)
cm_t3730_set_muxconf();
}
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_getcd(struct mmc *mmc)
{
u8 val;
@@ -470,7 +498,7 @@ static void setup_net_chip_gmpc(void)
&ctrl_base->gpmc_nadv_ale);
}
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
/*
* Routine: reset_net_chip
* Description: reset the Ethernet controller via TPS65930 GPIO
diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile
index 831be2e0e7..6d7d06815c 100644
--- a/board/compulab/common/Makefile
+++ b/board/compulab/common/Makefile
@@ -6,5 +6,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
+obj-$(CONFIG_SYS_I2C_OMAP34XX) += eeprom.o
obj-$(CONFIG_LCD) += omap3_display.o
diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h
index cf8c302b2e..e87162930d 100644
--- a/board/compulab/common/eeprom.h
+++ b/board/compulab/common/eeprom.h
@@ -10,7 +10,7 @@
#ifndef _EEPROM_
#define _EEPROM_
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
int cl_eeprom_read_mac_addr(uchar *buf);
u32 cl_eeprom_get_board_rev(void);
#else
diff --git a/board/compulab/common/omap3_display.c b/board/compulab/common/omap3_display.c
index ead821eeb7..61707f5b90 100644
--- a/board/compulab/common/omap3_display.c
+++ b/board/compulab/common/omap3_display.c
@@ -14,6 +14,7 @@
#include <stdio_dev.h>
#include <asm/arch/dss.h>
#include <lcd.h>
+#include <scf0403_lcd.h>
#include <asm/arch-omap3/dss.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -22,6 +23,7 @@ enum display_type {
NONE,
DVI,
DVI_CUSTOM,
+ DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */
};
#define CMAP_ADDR 0x80100000
@@ -119,6 +121,18 @@ static const struct panel_config preset_dvi_1280X1024 = {
.gfx_format = GFXFORMAT_RGB16,
};
+static const struct panel_config preset_dataimage_480X800 = {
+ .lcd_size = PANEL_LCD_SIZE(480, 800),
+ .timing_h = DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2),
+ .timing_v = DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3),
+ .pol_freq = DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF,
+ .divisor = 10 | (1 << 10),
+ .data_lines = LCD_INTERFACE_18_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
/*
* set_resolution_params()
*
@@ -146,6 +160,13 @@ static enum display_type set_dvi_preset(const struct panel_config preset,
return DVI;
}
+static enum display_type set_dataimage_preset(const struct panel_config preset,
+ int x_res, int y_res)
+{
+ set_preset(preset, x_res, y_res);
+ return DATA_IMAGE;
+}
+
/*
* parse_mode() - parse the mode parameter of custom lcd settings
*
@@ -369,6 +390,8 @@ static enum display_type env_parse_displaytype(char *displaytype)
return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
else if (!strncmp(displaytype, "dvi1280x1024", 12))
return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
+ else if (!strncmp(displaytype, "dataimage480x800", 16))
+ return set_dataimage_preset(preset_dataimage_480X800, 480, 800);
return NONE;
}
@@ -401,12 +424,31 @@ void lcd_ctrl_init(void *lcdbase)
clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
}
+#ifdef CONFIG_SCF0403_LCD
+static void scf0403_enable(void)
+{
+ gpio_direction_output(58, 1);
+ scf0403_init(157);
+}
+#else
+static inline void scf0403_enable(void) {}
+#endif
+
void lcd_enable(void)
{
- if (lcd_def == DVI || lcd_def == DVI_CUSTOM) {
+ switch (lcd_def) {
+ case NONE:
+ return;
+ case DVI:
+ case DVI_CUSTOM:
gpio_direction_output(54, 0); /* Turn on DVI */
- omap3_dss_enable();
+ break;
+ case DATA_IMAGE:
+ scf0403_enable();
+ break;
}
+
+ omap3_dss_enable();
}
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}
diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile
index 0818673cbd..f3bd00dbf1 100644
--- a/board/compulab/trimslice/Makefile
+++ b/board/compulab/trimslice/Makefile
@@ -5,8 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../../nvidia/common)
-
obj-y := trimslice.o
include ../../nvidia/common/common.mk
generated by cgit (git 2.34.1) at 2025-01-08 17:01:27 +0000