diff options
Diffstat (limited to 'board/fads')
| -rw-r--r-- | board/fads/Makefile | 8 | ||||
| -rw-r--r-- | board/fads/README | 73 | ||||
| -rw-r--r-- | board/fads/fads.c | 870 | ||||
| -rw-r--r-- | board/fads/fads.h | 468 | ||||
| -rw-r--r-- | board/fads/flash.c | 544 | ||||
| -rw-r--r-- | board/fads/lamp.c | 43 | ||||
| -rw-r--r-- | board/fads/pcmcia.c | 71 | ||||
| -rw-r--r-- | board/fads/u-boot.lds | 85 |
8 files changed, 0 insertions, 2162 deletions
diff --git a/board/fads/Makefile b/board/fads/Makefile deleted file mode 100644 index ea8b5c0d81..0000000000 --- a/board/fads/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = fads.o flash.o lamp.o pcmcia.o diff --git a/board/fads/README b/board/fads/README deleted file mode 100644 index 0873682787..0000000000 --- a/board/fads/README +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2000 - * Dave Ellis, SIXNET, dge@sixnetio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -Using the Motorola MPC8XXFADS development board -=============================================== - -CONFIGURATIONS --------------- - -There are ready-to-use default configurations available for the -FADS823, FADS850SAR and FADS860T. The FADS860T configuration also -works for the 855T processor. - -LOADING U-Boot INTO FADS FLASH MEMORY --------------------------------------- - -MPC8BUG can load U-Boot into the FLASH memory using LOADF. - - loadf u-boot.srec 100000 - - -STARTING U-Boot FROM MPC8BUG ------------------------------ - -To start U-Boot from MPC8BUG: - -1. Reset the board: - reset :h - -2. Change BR0 and OR0 back to their values at reset: - rms memc br0 00000001 - rms memc or0 00000d34 - -3. Modify DER so MPC8BUG gets control only when it should: - rms der 2002000f - -4. Start as if from reset: - go 100 - -This is NOT exactly the same as starting U-Boot without -MPC8BUG. MPC8BUG turns off the watchdog as part of the hard reset. -After it does the reset it writes SYPCR (to disable the watchdog) -and sets BR0 and OR0 to map the FLASH at 0x02800000 (and does lots -of other initialization). That is why it is necessary to set BR0 -and OR0 to map the FLASH everywhere. U-Boot can't turn on the -watchdog after that, since MPC8BUG has used the only chance to write -to SYPCR. - -Here is a bizarre sequence of MPC8BUG and U-Boot commands that lets -U-Boot write to SYPCR. It works with MPC8BUG 1.5 and an 855T -processor (your mileage may vary). It is probably better (and a lot -easier) just to accept having the watchdog disabled when the debug -cable is connected. - -in MPC8BUG: - reset :h - rms memc br0 00000001 - rms memc or0 00000d34 - rms der 2000f - go 100 - -Now U-Boot is running with the MPC8BUG value for SYPCR. Use the -U-Boot 'reset' command to reset the board. - =>reset -Next, in MPC8BUG: - rms der 2000f - go - -Now U-Boot is running with the U-Boot value for SYPCR. diff --git a/board/fads/fads.c b/board/fads/fads.c deleted file mode 100644 index fdb46b1f35..0000000000 --- a/board/fads/fads.c +++ /dev/null @@ -1,870 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <mpc8xx.h> -#include <pcmcia.h> - -#define _NOT_USED_ 0xFFFFFFFF - -/* ========================================================================= */ - -#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ - -#if defined(CONFIG_DRAM_50MHZ) -/* 50MHz tables */ -static const uint dram_60ns[] = -{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04, - 0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_, - 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c, - 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44, - 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00, - 0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, - 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint dram_70ns[] = -{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, - 0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, - 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00, - 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04, - 0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, - 0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_60ns[] = -{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04, - 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_, - 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c, - 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c, - 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, - 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_70ns[] = -{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04, - 0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c, - 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00, - 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00, - 0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, - 0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -#elif defined(CONFIG_DRAM_25MHZ) - -/* 25MHz tables */ - -static const uint dram_60ns[] = -{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint dram_70ns[] = -{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, - 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, - 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_60ns[] = -{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c, - 0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48, - 0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -static const uint edo_70ns[] = -{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00, - 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00, - 0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00, - 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00, - 0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; -#else -#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ -#endif - -/* ------------------------------------------------------------------------- */ -static int _draminit (uint base, uint noMbytes, uint edo, uint delay) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* init upm */ - - switch (delay) { - case 70: - if (edo) { - upmconfig (UPMA, (uint *) edo_70ns, - sizeof (edo_70ns) / sizeof (uint)); - } else { - upmconfig (UPMA, (uint *) dram_70ns, - sizeof (dram_70ns) / sizeof (uint)); - } - - break; - - case 60: - if (edo) { - upmconfig (UPMA, (uint *) edo_60ns, - sizeof (edo_60ns) / sizeof (uint)); - } else { - upmconfig (UPMA, (uint *) dram_60ns, - sizeof (dram_60ns) / sizeof (uint)); - } - - break; - - default: - return -1; - } - - memctl->memc_mptpr = 0x0400; /* divide by 16 */ - - switch (noMbytes) { - case 4: /* 4 Mbyte uses only CS2 */ - memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ - memctl->memc_or2 = 0xffc00800; /* 4M */ - break; - - case 8: /* 8 Mbyte uses both CS3 and CS2 */ - memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ - memctl->memc_or3 = 0xffc00800; /* 4M */ - memctl->memc_br3 = 0x00400081 + base; - memctl->memc_or2 = 0xffc00800; /* 4M */ - break; - - case 16: /* 16 Mbyte uses only CS2 */ - memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ - memctl->memc_or2 = 0xff000800; /* 16M */ - break; - - case 32: /* 32 Mbyte uses both CS3 and CS2 */ - memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ - memctl->memc_or3 = 0xff000800; /* 16M */ - memctl->memc_br3 = 0x01000081 + base; - memctl->memc_or2 = 0xff000800; /* 16M */ - break; - - default: - return -1; - } - - memctl->memc_br2 = 0x81 + base; /* use upma */ - - *((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */ - - /* if no dimm is inserted, noMbytes is still detected as 8m, so - * sanity check top and bottom of memory */ - - /* check bytes / 2 because get_ram_size tests at base+bytes, which - * is not mapped */ - if (noMbytes == 8) - if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) { - *((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */ - return -1; - } - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static void _dramdisable(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_br2 = 0x00000000; - memctl->memc_br3 = 0x00000000; - - /* maybe we should turn off upma here or something */ -} -#endif /* !CONFIG_MPC885ADS */ - -/* ========================================================================= */ - -#ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */ - -#if defined(CONFIG_SDRAM_100MHZ) - -/* ------------------------------------------------------------------------- */ -/* sdram table by Dan Malek */ - -/* This has the stretched early timing so the 50 MHz - * processor can make the 100 MHz timing. This will - * work at all processor speeds. - */ - -#ifdef SDRAM_ALT_INIT_SEQENCE -# define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */ -#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0 -# define SDRAM_MCRVALUE0 0x80808111 /* run upmb cs4 loop 1 addr 0x11 MRS */ -# define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0 /* ??? why not 0x80808130? */ -#else -# define SDRAM_MxMR_PTx 195 -# define UPM_MRS_ADDR 0x11 -# define UPM_REFRESH_ADDR 0x30 /* or 0x11 if we want to be like above? */ -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -static const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04, - 0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_, - - /* burst read. (offset 8 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04, - 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00, - 0x1ff77c45, - - /* precharge + MRS. (offset 11 in upm RAM) */ - 0xeffbbc04, 0x1ff77c34, 0xefeabc34, - 0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write. (offset 18 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04, - 0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst write. (offset 20 in upm RAM) */ - 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, - 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* refresh. (offset 30 in upm RAM) */ - 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* exception. (offset 3c in upm RAM) */ - 0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ }; - -#elif defined(CONFIG_SDRAM_50MHZ) - -/* ------------------------------------------------------------------------- */ -/* sdram table stolen from the fads manual */ -/* for chip MB811171622A-100 */ - -/* this table is for 32-50MHz operation */ -#ifdef SDRAM_ALT_INIT_SEQENCE -# define SDRAM_MBMRVALUE0 0x80802114 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */ -# define SDRAM_MBMRVALUE1 0x80802118 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */ -# define SDRAM_MCRVALUE0 0x80808105 /* run upmb cs4 loop 1 addr 0x5 MRS */ -# define SDRAM_MCRVALUE1 0x80808130 /* run upmb cs4 loop 1 addr 0x30 REFRESH */ -# define SDRAM_MPTRVALUE 0x400 -#define SDRAM_MARVALUE 0x88 -#else -# define SDRAM_MxMR_PTx 128 -# define UPM_MRS_ADDR 0x5 -# define UPM_REFRESH_ADDR 0x30 -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -static const uint sdram_table[] = -{ - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* precharge + MRS. (offset 5 in upm RAM) */ - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -/* ------------------------------------------------------------------------- */ -#else -#error SDRAM not correctly configured -#endif -/* ------------------------------------------------------------------------- */ - -/* - * Memory Periodic Timer Prescaler - */ - -#define SDRAM_OR4VALUE 0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */ -#define SDRAM_BR4VALUE 0x000000c1 /* UPMB,base addr or'ed on later */ - -/* ------------------------------------------------------------------------- */ -#ifdef SDRAM_ALT_INIT_SEQENCE -/* ------------------------------------------------------------------------- */ - -static int _initsdram(uint base, uint noMbytes) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = SDRAM_MPTPRVALUE; - - /* Configure the refresh (mostly). This needs to be - * based upon processor clock speed and optimized to provide - * the highest level of performance. For multiple banks, - * this time has to be divided by the number of banks. - * Although it is not clear anywhere, it appears the - * refresh steps through the chip selects for this UPM - * on each refresh cycle. - * We have to be careful changing - * UPM registers after we ask it to run these commands. - */ - - memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */ - memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */ - - udelay(200); - - /* Now run the precharge/nop/mrs commands. - */ - - memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */ - /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */ - udelay(200); - - /* Run 8 refresh cycles */ - - memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 MHz)*/ - /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */ - - udelay(200); - - memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 MHz) or TLF 8 (50MHz) */ - memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 MHz) */ - /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */ - - udelay(200); - - memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */ - - memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1); - memctl->memc_br4 = SDRAM_BR4VALUE | base; - - return 0; -} - -/* ------------------------------------------------------------------------- */ -#else /* !SDRAM_ALT_INIT_SEQUENCE */ -/* ------------------------------------------------------------------------- */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -# define MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -# define MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -# define MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -# define MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MxMR settings for SDRAM - */ - -/* 8 column SDRAM */ -# define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTBE | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) -/* 9 column SDRAM */ -# define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTAE | \ - MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) - -static int _initsdram(uint base, uint noMbytes) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); - - memctl->memc_mptpr = MPTPR_2BK_4K; - memctl->memc_mbmr = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */ - - /* map CS 4 */ - memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1); - memctl->memc_br4 = SDRAM_BR4VALUE | base; - - /* Perform SDRAM initilization */ -# ifdef UPM_NOP_ADDR /* not currently in UPM table */ - /* step 1: nop */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(0) | UPM_NOP_ADDR; -# endif - - /* step 2: delay */ - udelay(200); - -# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */ - /* step 3: precharge */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(4) | UPM_PRECHARGE_ADDR; -# endif - - /* step 4: refresh */ - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(2) | UPM_REFRESH_ADDR; - - /* - * note: for some reason, the UPM values we are using include - * precharge with MRS - */ - - /* step 5: mrs */ - memctl->memc_mar = 0x00000088; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(1) | UPM_MRS_ADDR; - -# ifdef UPM_NOP_ADDR - memctl->memc_mar = 0x00000000; - memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 | - MCR_MLCF(0) | UPM_NOP_ADDR; -# endif - /* - * Enable refresh - */ - - memctl->memc_mbmr |= MBMR_PTBE; - return 0; -} -#endif /* !SDRAM_ALT_INIT_SEQUENCE */ - -/* ------------------------------------------------------------------------- */ - -static void _sdramdisable(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_br4 = 0x00000000; - - /* maybe we should turn off upmb here or something */ -} - -/* ------------------------------------------------------------------------- */ - -static int initsdram(uint base, uint *noMbytes) -{ - uint m = CONFIG_SYS_SDRAM_SIZE>>20; - - /* _initsdram needs access to sdram */ - *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */ - - if(!_initsdram(base, m)) - { - *noMbytes += m; - return 0; - } - else - { - *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */ - - _sdramdisable(); - - return -1; - } -} - -#endif /* CONFIG_FADS */ - -/* ========================================================================= */ - -phys_size_t initdram (int board_type) -{ - uint sdramsz = 0; /* size of sdram in Mbytes */ - uint m = 0; /* size of dram in Mbytes */ -#ifndef CONFIG_MPC885ADS - uint base = 0; /* base of dram in bytes */ - uint k, s; -#endif - -#ifdef CONFIG_FADS - if (!initsdram (0x00000000, &sdramsz)) { -#ifndef CONFIG_MPC885ADS - base = sdramsz << 20; -#endif - printf ("(%u MB SDRAM) ", sdramsz); - } -#endif -#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ - k = (*((uint *) BCSR2) >> 23) & 0x0f; - - switch (k & 0x3) { - /* "MCM36100 / MT8D132X" */ - case 0x00: - m = 4; - break; - - /* "MCM36800 / MT16D832X" */ - case 0x01: - m = 32; - break; - /* "MCM36400 / MT8D432X" */ - case 0x02: - m = 16; - break; - /* "MCM36200 / MT16D832X ?" */ - case 0x03: - m = 8; - break; - - } - - switch (k >> 2) { - case 0x02: - k = 70; - break; - - case 0x03: - k = 60; - break; - - default: - printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k); - k = 70; - } - -#ifdef CONFIG_FADS - /* the FADS is missing this bit, all rams treated as non-edo */ - s = 0; -#else - s = (*((uint *) BCSR2) >> 27) & 0x01; -#endif - - if (!_draminit (base, m, s, k)) { - printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : ""); - } else { - _dramdisable (); - m = 0; - } -#endif /* !CONFIG_MPC885ADS */ - m += sdramsz; /* add sdram size to total */ - - return (m << 20); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ========================================================================= */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ -#if defined(CONFIG_MPC86xADS) - puts ("Board: MPC86xADS\n"); -#elif defined(CONFIG_MPC885ADS) - puts ("Board: MPC885ADS\n"); -#else /* Only old ADS/FADS have got revision ID in BCSR3 */ - uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3) - | (((*((uint *) BCSR3) >> 19) & 1) << 2) - | (((*((uint *) BCSR3) >> 16) & 3)); - - puts ("Board: "); -#if defined(CONFIG_FADS) - puts ("FADS"); - checkdboard (); -#else - puts ("ADS"); -#endif - - puts (" rev "); - - switch (r) { - case 0x00: - puts ("ENG\n"); - break; - case 0x01: - puts ("PILOT\n"); - break; - default: - printf ("unknown (0x%x)\n", r); - return -1; - } -#endif /* CONFIG_MPC86xADS */ - - return 0; -} - -/* ========================================================================= */ - -#if defined(CONFIG_CMD_PCMCIA) - -#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR; -#endif - -int pcmcia_init(void) -{ - volatile pcmconf8xx_t *pcmp; - uint v, slota = 0, slotb = 0; - - /* - ** Enable the PCMCIA for a Flash card. - */ - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - -#if 0 - pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR; - pcmp->pcmc_por0 = 0xc00ff05d; -#endif - - /* Set all slots to zero by default. */ - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; -#ifdef CONFIG_PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0x40; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0x40; -#endif - - /* enable PCMCIA buffers */ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - - /* Check if any PCMCIA card is plugged in. */ - -#ifdef CONFIG_PCMCIA_SLOT_A - slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ; -#endif - - if (!(slota || slotb)) { - printf("No card present\n"); - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; - return -1; - } - else - printf("Card present ("); - - v = 0; - - /* both the ADS and the FADS have a 5V keyed pcmcia connector (?) - ** - ** Paolo - Yes, but i have to insert some 3.3V card in that slot on - ** my FADS... :-) - */ - -#if defined(CONFIG_MPC86x) - switch ((pcmp->pcmc_pipr >> 30) & 3) -#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850) - switch ((pcmp->pcmc_pipr >> 14) & 3) -#endif - { - case 0x03 : - printf("5V"); - v = 5; - break; - case 0x01 : - printf("5V and 3V"); -#ifdef CONFIG_FADS - v = 3; /* User lower voltage if supported! */ -#else - v = 5; -#endif - break; - case 0x00 : - printf("5V, 3V and x.xV"); -#ifdef CONFIG_FADS - v = 3; /* User lower voltage if supported! */ -#else - v = 5; -#endif - break; - } - - switch (v) { -#ifdef CONFIG_FADS - case 3: - printf("; using 3V"); - /* - ** Enable 3 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCC1; - *((uint *)BCSR1) |= BCSR1_PCCVCC0; - break; -#endif - case 5: - printf("; using 5V"); -#ifdef CONFIG_FADS - /* - ** Enable 5 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCC0; - *((uint *)BCSR1) |= BCSR1_PCCVCC1; -#endif - break; - - default: - *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */ - - printf("; unknown voltage"); - return -1; - } - printf(")\n"); - /* disable pcmcia reset after a while */ - - udelay(20); - -#ifdef CONFIG_PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0; -#endif -#ifdef CONFIG_PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0; -#endif - - /* If you using a real hd you should give a short - * spin-up time. */ -#ifdef CONFIG_DISK_SPINUP_TIME - udelay(CONFIG_DISK_SPINUP_TIME); -#endif - - return 0; -} - -#endif - -/* ========================================================================= */ - -#ifdef CONFIG_SYS_PC_IDE_RESET - -void ide_set_reset(int on) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - /* - * Configure PC for IDE Reset Pin - */ - if (on) { /* assert RESET */ - immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET); - } else { /* release RESET */ - immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET; - } - - /* program port pin as GPIO output */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET; -} - -#endif /* CONFIG_SYS_PC_IDE_RESET */ diff --git a/board/fads/fads.h b/board/fads/fads.h deleted file mode 100644 index 1be00b9048..0000000000 --- a/board/fads/fads.h +++ /dev/null @@ -1,468 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum, - * and Dan Malek - * - * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com - * - * This header file contains values common to all FADS family boards. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * Flash Memory Map as used by U-Boot: - * - * Start Address Length - * +-----------------------+ 0xFE00_0000 Start of Flash ----------------- - * | | 0xFE00_0100 Reset Vector - * + + 0xFE0?_???? - * | U-Boot code | - * | | - * +-----------------------+ 0xFE04_0000 (sector border) - * | | - * | | - * | U-Boot environment | - * | | ^ - * | | | U-Boot - * +=======================+ 0xFE08_0000 (sector border) ----------------- - * | Available | | Applications - * | ... | v - * - *****************************************************************************/ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NFSBOOTCOMMAND \ - "dhcp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm" - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ - "bootm fe080000" - -#undef CONFIG_BOOTARGS - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if !defined(CONFIG_MPC885ADS) -#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#endif - -/* - * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options: - * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on - * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have - * got FEC so FEC is the default. - */ -#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */ -#define CONFIG_FEC_ENET /* Use FEC ethernet */ - -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - -#ifdef CONFIG_FEC_ENET -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII_INIT 1 -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -#if !defined(FADS_COMMANDS_ALREADY_DEFINED) -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_PING - -#endif - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* #undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ -#define CONFIG_SYS_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ -/* - * 2048 SDRAM rows - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) -#elif defined(CONFIG_FADS) /* Old/new FADS */ -#define CONFIG_SYS_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ -#else /* Old ADS */ -#define CONFIG_SYS_SDRAM_SIZE 0x00000000 /* No SDRAM */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#if (CONFIG_SYS_SDRAM_SIZE) -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ -#else -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#endif /* CONFIG_SYS_SDRAM_SIZE */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ - -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * Flash organization - */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CONFIG_ENV_OFFSET CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -#if defined(CONFIG_CMD_JFFS2) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3" -#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)" -*/ - -#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ - -/*----------------------------------------------------------------------- - * I2C configuration - */ -#if defined(CONFIG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address defaults */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR SCCR_TBS - -/*----------------------------------------------------------------------- - * DER - Debug Enable Register - *----------------------------------------------------------------------- - * Set to zero to prevent the processor from entering debug mode - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the entire - * address space, we have to set the memory controller differently. - * Normally, you write the option register first, and then enable the - * chip select by writing the base register. For CS0, you must write - * the base register first, followed by the option register. - */ - -/* - * Init Memory Controller: - * - * BR0/OR0 (Flash) - * BR1/OR1 (BCSR) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define BCSR_ADDR ((uint) 0xFF080000) - -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 8 Mbyte until detected */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V ) - -/* BCSRx - Board Control and Status Registers */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V) - -/* values according to the manual */ - -#define BCSR0 ((uint) (BCSR_ADDR + 0x00)) -#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) -#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) -#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) - -/* - * (F)ADS bitvalues by Helmut Buchsbaum - * - * See User's Manual for a proper - * description of the following structures - */ - -#define BCSR0_ERB ((uint)0x80000000) -#define BCSR0_IP ((uint)0x40000000) -#define BCSR0_BDIS ((uint)0x10000000) -#define BCSR0_BPS_MASK ((uint)0x0C000000) -#define BCSR0_ISB_MASK ((uint)0x01800000) -#define BCSR0_DBGC_MASK ((uint)0x00600000) -#define BCSR0_DBPC_MASK ((uint)0x00180000) -#define BCSR0_EBDF_MASK ((uint)0x00060000) - -#define BCSR1_FLASH_EN ((uint)0x80000000) -#define BCSR1_DRAM_EN ((uint)0x40000000) -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_IRDEN ((uint)0x10000000) -#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) -#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) -#define BCSR1_BCSR_EN ((uint)0x02000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_PCCEN ((uint)0x00800000) -#define BCSR1_PCCVCC0 ((uint)0x00400000) -#define BCSR1_PCCVPP_MASK ((uint)0x00300000) -#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR1_SDRAM_EN ((uint)0x00020000) -#define BCSR1_PCCVCC1 ((uint)0x00010000) - -#define BCSR1_PCCVCCON BCSR1_PCCVCC0 - -#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) -#define BCSR2_FLASH_PD_SHIFT 28 -#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) -#define BCSR2_DRAM_PD_SHIFT 23 -#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) -#define BCSR2_DBREVNR_MASK ((uint)0x00030000) - -#define BCSR3_DBID_MASK ((ushort)0x3800) -#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) -#define BCSR3_BREVNR0 ((ushort)0x0080) -#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) -#define BCSR3_BREVN1 ((ushort)0x0008) -#define BCSR3_BREVN2_MASK ((ushort)0x0003) - -#define BCSR4_ETHLOOP ((uint)0x80000000) -#define BCSR4_TFPLDL ((uint)0x40000000) -#define BCSR4_TPSQEL ((uint)0x20000000) -#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) -#if defined(CONFIG_MPC823) -#define BCSR4_USB_EN ((uint)0x08000000) -#define BCSR4_USB_SPEED ((uint)0x04000000) -#define BCSR4_VCCO ((uint)0x02000000) -#define BCSR4_VIDEO_ON ((uint)0x00800000) -#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) -#define BCSR4_VIDEO_RST ((uint)0x00200000) -#define BCSR4_MODEM_EN ((uint)0x00100000) -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#elif defined(CONFIG_MPC850) -#define BCSR4_DATA_VOICE ((uint)0x00080000) -#elif defined(CONFIG_MPC860SAR) -#define BCSR4_UTOPIA_EN ((uint)0x08000000) -#else /* MPC860T and other chips with FEC */ -#define BCSR4_FETH_EN ((uint)0x08000000) -#define BCSR4_FETHCFG0 ((uint)0x04000000) -#define BCSR4_FETHFDE ((uint)0x02000000) -#define BCSR4_FETHCFG1 ((uint)0x00400000) -#define BCSR4_FETHRST ((uint)0x00200000) -#endif - -/* BSCR5 exists on MPC86xADS and MPC885ADS only */ - -#define CONFIG_SYS_PHYDEV_ADDR (BCSR_ADDR + 0x20000) - -#define BCSR5 (CONFIG_SYS_PHYDEV_ADDR + 0x300) - -#define BCSR5_MII2_EN 0x40 -#define BCSR5_MII2_RST 0x20 -#define BCSR5_T1_RST 0x10 -#define BCSR5_ATM155_RST 0x08 -#define BCSR5_ATM25_RST 0x04 -#define BCSR5_MII1_EN 0x02 -#define BCSR5_MII1_RST 0x01 - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_ISO_PARTITION 1 - -#undef CONFIG_ATAPI -#if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ -#endif -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 - -#define CONFIG_DISK_SPINUP_TIME 1000000 -/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */ diff --git a/board/fads/flash.c b/board/fads/flash.c deleted file mode 100644 index ea2f713ca6..0000000000 --- a/board/fads/flash.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#define QUAD_ID(id) ((((ulong)(id) & 0xFF) << 24) | \ - (((ulong)(id) & 0xFF) << 16) | \ - (((ulong)(id) & 0xFF) << 8) | \ - (((ulong)(id) & 0xFF) << 0) \ - ) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - vu_long *bcsr = (vu_long *)BCSR_ADDR; - unsigned long pd_size, total_size, bsize, or_am; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = 0; - flash_info[i].sector_count = 0; - flash_info[i].start[0] = 0xFFFFFFFF; /* For TFTP */ - } - - switch ((bcsr[2] & BCSR2_FLASH_PD_MASK) >> BCSR2_FLASH_PD_SHIFT) { - case 2: - case 4: - case 6: - pd_size = 0x800000; - or_am = 0xFF800000; - break; - - case 5: - case 7: - pd_size = 0x400000; - or_am = 0xFFC00000; - break; - - case 8: - pd_size = 0x200000; - or_am = 0xFFE00000; - break; - - default: - pd_size = 0; - or_am = 0xFFE00000; - printf("## Unsupported flash detected by BCSR: 0x%08lX\n", bcsr[2]); - } - - total_size = 0; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && total_size < pd_size; ++i) { - bsize = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + total_size), - &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, bsize, bsize >> 20); - } - - total_size += bsize; - } - - if (total_size != pd_size) { - printf("## Detected flash size %lu conflicts with PD data %lu\n", - total_size, pd_size); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = or_am | CONFIG_SYS_OR_TIMING_FLASH; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) { -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - if (CONFIG_SYS_MONITOR_BASE >= flash_info[i].start[0]) - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[i]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - if (CONFIG_ENV_ADDR >= flash_info[i].start[0]) - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[i]); -#endif - } - - return total_size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_BM: - printf ("BRIGHT MICRO "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM080: - printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - * The following code can not run from flash! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - - switch (addr[0]) { - case QUAD_ID(AMD_MANUFACT): - info->flash_id = FLASH_MAN_AMD; - break; - - case QUAD_ID(FUJ_MANUFACT): - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - switch (addr[1]) { /* device ID */ - case QUAD_ID(AMD_ID_F040B): - case QUAD_ID(AMD_ID_LV040B): - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00200000; - break; /* => 2 MB */ - - case QUAD_ID(AMD_ID_F080B): - info->flash_id += FLASH_AM080; - info->sector_count = 16; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif /* 0 */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - -#if 0 - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = (ulong)addr + (i * 0x00040000); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *) (info->start[i]); - info->protect[i] = addr[2] & 1; - } - - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *) info->start[0]; - *addr = 0xF0F0F0F0; /* reset bank */ - } - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - vu_long *addr = (vu_long *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return ERR_INVAL; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); - return ERR_UNKNOWN_FLASH_TYPE; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *) (info->start[l_sect]); - while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) - { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *) info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) (info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & data) != data) { - return ERR_NOT_ERASED; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *) dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080)) - { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return ERR_TIMOUT; - } - } - return (0); -} diff --git a/board/fads/lamp.c b/board/fads/lamp.c deleted file mode 100644 index ffcc2b3c41..0000000000 --- a/board/fads/lamp.c +++ /dev/null @@ -1,43 +0,0 @@ -#include <config.h> - -#include <common.h> - -void -signal_delay(unsigned int n) -{ - while (n--); -} - -void -signal_on(void) -{ - *((volatile uint *)BCSR4) &= ~(1<<(31-3)); /* led on */ -} - -void -signal_off(void) -{ - *((volatile uint *)BCSR4) |= (1<<(31-3)); /* led off */ -} - -void -slow_blink(unsigned int n) -{ - while (n--) { - signal_on(); - signal_delay(0x00400000); - signal_off(); - signal_delay(0x00400000); - } -} - -void -fast_blink(unsigned int n) -{ - while (n--) { - signal_on(); - signal_delay(0x00100000); - signal_off(); - signal_delay(0x00100000); - } -} diff --git a/board/fads/pcmcia.c b/board/fads/pcmcia.c deleted file mode 100644 index 996f032f64..0000000000 --- a/board/fads/pcmcia.c +++ /dev/null @@ -1,71 +0,0 @@ -#include <common.h> -#include <mpc8xx.h> -#include <pcmcia.h> - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -#define PCMCIA_BOARD_MSG "FADS" - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - u_long reg = 0; - - switch(vpp) { - case 0: reg = 0; break; - case 50: reg = 1; break; - case 120: reg = 2; break; - default: return 1; - } - - switch(vcc) { - case 0: reg = 0; break; -#ifdef CONFIG_FADS - case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break; - case 50: reg = BCSR1_PCCVCC1; break; -#endif - default: return 1; - } - - /* first, turn off all power */ - -#ifdef CONFIG_FADS - *((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1); -#endif - *((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK; - - /* enable new powersettings */ - -#ifdef CONFIG_FADS - *((uint *)BCSR1) |= reg; -#endif - - *((uint *)BCSR1) |= reg << 20; - - return 0; -} - -int pcmcia_hardware_enable(int slot) -{ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - return 0; -} - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - *((uint *)BCSR1) &= ~BCSR1_PCCEN; - return 0; -} -#endif - -#endif /* CONFIG_PCMCIA */ diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds deleted file mode 100644 index 3123a888f1..0000000000 --- a/board/fads/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - /*. = DEFINED(env_offset) ? env_offset : .;*/ - common/env_embedded.o (.ppcenv*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} -ENTRY(_start) |