diff options
Diffstat (limited to 'board/freescale/m54455evb')
| -rw-r--r-- | board/freescale/m54455evb/m54455evb.c | 42 | ||||
| -rw-r--r-- | board/freescale/m54455evb/mii.c | 12 |
2 files changed, 27 insertions, 27 deletions
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 100682a261..293b5b0e41 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -45,13 +45,13 @@ phys_size_t initdram(int board_type) * Serial Boot: The dram is already initialized in start.S * only require to return DRAM size */ - dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; #else volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); u32 i; - dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -59,33 +59,33 @@ phys_size_t initdram(int board_type) } i--; - gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH; + gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH; - sdram->sdcs0 = (CFG_SDRAM_BASE | i); - sdram->sdcs1 = (CFG_SDRAM_BASE1 | i); + sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i); + sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i); - sdram->sdcfg1 = CFG_SDRAM_CFG1; - sdram->sdcfg2 = CFG_SDRAM_CFG2; + sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1; + sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2; /* Issue PALL */ - sdram->sdcr = CFG_SDRAM_CTRL | 2; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; /* Issue LEMR */ - sdram->sdmr = CFG_SDRAM_EMOD | 0x408; - sdram->sdmr = CFG_SDRAM_MODE | 0x300; + sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408; + sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300; udelay(500); /* Issue PALL */ - sdram->sdcr = CFG_SDRAM_CTRL | 2; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; /* Perform two refresh cycles */ - sdram->sdcr = CFG_SDRAM_CTRL | 4; - sdram->sdcr = CFG_SDRAM_CTRL | 4; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->sdmr = CFG_SDRAM_MODE | 0x200; + sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200; - sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00; udelay(100); #endif @@ -175,11 +175,11 @@ void pci_init_board(void) #include <flash.h> ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) { - int sect[] = CFG_ATMEL_SECT; - int sectsz[] = CFG_ATMEL_SECTSZ; + int sect[] = CONFIG_SYS_ATMEL_SECT; + int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ; int i, j, k; - if (base != CFG_ATMEL_BASE) + if (base != CONFIG_SYS_ATMEL_BASE) return 0; info->flash_id = 0x01000000; @@ -205,9 +205,9 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) info->name = "CFI conformant"; info->size = 0; - info->sector_count = CFG_ATMEL_TOTALSECT; + info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT; info->start[0] = base; - for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) { + for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) { info->size += sect[i] * sectsz[i]; for (j = 0; j < sect[i]; j++, k++) { @@ -218,4 +218,4 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) return 1; } -#endif /* CFG_FLASH_CFI */ +#endif /* CONFIG_SYS_FLASH_CFI */ diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c index 0be5439ef9..c19519144c 100644 --- a/board/freescale/m54455evb/mii.c +++ b/board/freescale/m54455evb/mii.c @@ -43,7 +43,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) gpio->par_feci2c |= (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); - if (info->iobase == CFG_FEC0_IOBASE) + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; else gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; @@ -51,7 +51,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); - if (info->iobase == CFG_FEC0_IOBASE) + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; else gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; @@ -59,7 +59,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) return 0; } -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII) #include <miiphy.h> /* Make MII read/write commands for the FEC. */ @@ -152,9 +152,9 @@ uint mii_send(uint mii_cmd) return (mii_reply & 0xffff); /* data read from phy */ } -#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ +#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */ -#if defined(CFG_DISCOVER_PHY) +#if defined(CONFIG_SYS_DISCOVER_PHY) int mii_discover_phy(struct eth_device *dev) { #define MAX_PHY_PASSES 11 @@ -219,7 +219,7 @@ int mii_discover_phy(struct eth_device *dev) return phyaddr; } -#endif /* CFG_DISCOVER_PHY */ +#endif /* CONFIG_SYS_DISCOVER_PHY */ void mii_init(void) __attribute__((weak,alias("__mii_init"))); |