diff options
Diffstat (limited to 'board/freescale/p1010rdb')
| -rw-r--r-- | board/freescale/p1010rdb/p1010rdb.c | 176 |
1 files changed, 170 insertions, 6 deletions
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index ae8ba45e69..e940d2275e 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -38,12 +38,23 @@ DECLARE_GLOBAL_DATA_PTR; enum { MUX_TYPE_IFC, MUX_TYPE_SDHC, + MUX_TYPE_SPIFLASH, + MUX_TYPE_TDM, + MUX_TYPE_CAN, + MUX_TYPE_CS0_NOR, + MUX_TYPE_CS0_NAND, +}; + +enum { + I2C_READ_BANK, + I2C_READ_PCB_VER, }; static uint sd_ifc_mux; struct cpld_data { u8 cpld_ver; /* cpld revision */ +#if defined(CONFIG_P1010RDB_PA) u8 pcba_ver; /* pcb revision number */ u8 twindie_ddr3; u8 res1[6]; @@ -58,6 +69,9 @@ struct cpld_data { u8 por1; /* POR Options */ u8 por2; /* POR Options */ u8 por3; /* POR Options */ +#elif defined(CONFIG_P1010RDB_PB) + u8 rom_loc; +#endif }; int board_early_init_f(void) @@ -116,6 +130,9 @@ int config_board_mux(int ctrl_type) ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u8 tmp; +#if defined(CONFIG_P1010RDB_PA) + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + switch (ctrl_type) { case MUX_TYPE_IFC: i2c_set_bus_num(I2C_PCA9557_BUS_NUM); @@ -136,25 +153,171 @@ int config_board_mux(int ctrl_type) clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, PMUXCR1_SDHC_ENABLE); break; + case MUX_TYPE_SPIFLASH: + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + break; + case MUX_TYPE_TDM: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + break; + case MUX_TYPE_CAN: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + break; default: break; } +#elif defined(CONFIG_P1010RDB_PB) + uint orig_bus = i2c_get_bus_num(); + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + switch (ctrl_type) { + case MUX_TYPE_IFC: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x80); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x80); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_TDM: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x82); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x82); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CAN: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x02); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x02); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CS0_NOR: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CS0_NAND: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + default: + break; + } + i2c_set_bus_num(orig_bus); +#endif return 0; } +#ifdef CONFIG_P1010RDB_PB +int i2c_pca9557_read(int type) +{ + u8 val; + + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); + + switch (type) { + case I2C_READ_BANK: + val = (val & 0x10) >> 4; + break; + case I2C_READ_PCB_VER: + val = ((val & 0x60) >> 5) + 1; + break; + default: + break; + } + + return val; +} +#endif + int checkboard(void) { struct cpu_type *cpu; + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + u8 val; cpu = gd->arch.cpu; - printf("Board: %sRDB\n", cpu->name); +#if defined(CONFIG_P1010RDB_PA) + printf("Board: %sRDB-PA, ", cpu->name); +#elif defined(CONFIG_P1010RDB_PB) + printf("Board: %sRDB-PB, ", cpu->name); + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); + val = 0x0; /* no polarity inversion */ + i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); +#endif #ifdef CONFIG_SDCARD /* switch to IFC to read info from CPLD */ config_board_mux(MUX_TYPE_IFC); #endif +#if defined(CONFIG_P1010RDB_PA) + val = (in_8(&cpld_data->pcba_ver) & 0xf); + printf("PCB: v%x.0\n", val); +#elif defined(CONFIG_P1010RDB_PB) + val = in_8(&cpld_data->cpld_ver); + printf("CPLD: v%x.%x, ", val >> 4, val & 0xf); + printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER)); + val = in_8(&cpld_data->rom_loc) & 0xf; + puts("Boot from: "); + switch (val) { + case 0xf: + config_board_mux(MUX_TYPE_CS0_NOR); + printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK)); + break; + case 0xe: + puts("SDHC\n"); + val = 0x60; /* set pca9557 pin input/output */ + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); + break; + case 0x5: + config_board_mux(MUX_TYPE_IFC); + config_board_mux(MUX_TYPE_CS0_NAND); + puts("NAND\n"); + break; + case 0x6: + config_board_mux(MUX_TYPE_IFC); + puts("SPI\n"); + break; + default: + puts("unknown\n"); + break; + } +#endif return 0; } @@ -348,7 +511,6 @@ void board_reset(void) int misc_init_r(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { @@ -356,7 +518,7 @@ int misc_init_r(void) MPC85xx_PMUXCR_CAN1_UART | MPC85xx_PMUXCR_CAN2_TDM | MPC85xx_PMUXCR_CAN2_UART); - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + config_board_mux(MUX_TYPE_CAN); } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | MPC85xx_PMUXCR_CAN1_UART); @@ -364,11 +526,10 @@ int misc_init_r(void) MPC85xx_PMUXCR_CAN1_TDM); clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + config_board_mux(MUX_TYPE_TDM); } else { /* defaultly spi_cs_sel to flash */ - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + config_board_mux(MUX_TYPE_SPIFLASH); } if (hwconfig("esdhc")) @@ -376,6 +537,9 @@ int misc_init_r(void) else if (hwconfig("ifc")) config_board_mux(MUX_TYPE_IFC); +#ifdef CONFIG_P1010RDB_PB + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); +#endif return 0; } |