diff options
Diffstat (limited to 'board/freescale/p1_p2_rdb_pc/ddr.c')
| -rw-r--r-- | board/freescale/p1_p2_rdb_pc/ddr.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 9355536b35..c0b72e035e 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -80,7 +80,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tFAW_ps = 30000, }; -#elif defined(CONFIG_P1020MBG) +#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) /* Micron MT41J512M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 2, @@ -111,7 +111,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tFAW_ps = 37500, }; -#elif defined(CONFIG_P1020RDB) +#elif defined(CONFIG_P1020RDB_PC) /* * Samsung K4B2G0846C-HCF8 * The following timing are for "downshift" @@ -247,11 +247,11 @@ phys_size_t fixed_sdram(void) get_sys_info(&sysinfo); printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, sysinfo.freqDDRBus)); + strmhz(buf, sysinfo.freq_ddrbus)); ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { |