diff options
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mx25pdk/mx25pdk.c | 114 | ||||
| -rw-r--r-- | board/freescale/mx31ads/u-boot.lds | 2 | ||||
| -rw-r--r-- | board/freescale/mx35pdk/lowlevel_init.S | 4 | ||||
| -rw-r--r-- | board/freescale/mx35pdk/mx35pdk.c | 21 |
4 files changed, 141 insertions, 0 deletions
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c index 4a8352fb3d..72fa6bc826 100644 --- a/board/freescale/mx25pdk/mx25pdk.c +++ b/board/freescale/mx25pdk/mx25pdk.c @@ -19,12 +19,71 @@ #include <common.h> #include <asm/io.h> +#include <asm/gpio.h> #include <asm/arch/imx-regs.h> #include <asm/arch/imx25-pinmux.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include <pmic.h> +#include <fsl_pmic.h> +#include <mc34704.h> + +#define FEC_RESET_B IMX_GPIO_NR(2, 3) +#define FEC_ENABLE_B IMX_GPIO_NR(4, 8) +#define CARD_DETECT IMX_GPIO_NR(2, 1) DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {IMX_MMC_SDHC1_BASE}, +}; +#endif + +static void mx25pdk_fec_init(void) +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); + u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; + + /* FEC pin init is generic */ + mx25_fec_init_pins(); + + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + /* + * Set up FEC_RESET_B and FEC_ENABLE_B + * + * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12 + * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17 + */ + writel(gpio_mux_mode, &muxctl->pad_d12); + writel(gpio_mux_mode, &muxctl->pad_a17); + + writel(0x0, &padctl->pad_d12); + writel(0x0, &padctl->pad_a17); + + /* Assert RESET and ENABLE low */ + gpio_direction_output(FEC_RESET_B, 0); + gpio_direction_output(FEC_ENABLE_B, 0); + + udelay(10); + + /* Deassert RESET and ENABLE */ + gpio_set_value(FEC_RESET_B, 1); + gpio_set_value(FEC_ENABLE_B, 1); + + /* Setup I2C pins so that PMIC can turn on PHY supply */ + writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk); + writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat); + writel(0x1E8, &padctl->pad_i2c1_clk); + writel(0x1E8, &padctl->pad_i2c1_dat); +} + int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -48,6 +107,61 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + struct pmic *p; + + mx25pdk_fec_init(); + + pmic_init(); + p = get_pmic(); + /* Turn on Ethernet PHY supply */ + pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE); + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_getcd(struct mmc *mmc) +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); + + /* + * Set up the Card Detect pin. + * + * SD1_GPIO_CD: gpio2_1 is ALT 5 mode of pin A15 + * + */ + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + + writel(gpio_mux_mode, &muxctl->pad_a15); + writel(0x0, &padctl->pad_a15); + + gpio_direction_input(CARD_DETECT); + return !gpio_get_value(CARD_DETECT); +} + +int board_mmc_init(bd_t *bis) +{ + struct iomuxc_mux_ctl *muxctl; + u32 sdhc1_mux_mode = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; + + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + writel(sdhc1_mux_mode, &muxctl->pad_sd1_cmd); + writel(sdhc1_mux_mode, &muxctl->pad_sd1_clk); + writel(sdhc1_mux_mode, &muxctl->pad_sd1_data0); + writel(sdhc1_mux_mode, &muxctl->pad_sd1_data1); + writel(sdhc1_mux_mode, &muxctl->pad_sd1_data2); + writel(sdhc1_mux_mode, &muxctl->pad_sd1_data3); + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + int checkboard(void) { puts("Board: MX25PDK\n"); diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 29ad0e6e79..52677299e8 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -65,6 +65,8 @@ SECTIONS . = ALIGN(4); + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S index 75bb958619..da8b6f3a4e 100644 --- a/board/freescale/mx35pdk/lowlevel_init.S +++ b/board/freescale/mx35pdk/lowlevel_init.S @@ -94,6 +94,10 @@ orr r1, r1, #0x00000C00 orr r1, r1, #0x00000003 str r1, [r0, #CLKCTL_CGR1] + + ldr r1, [r0, #CLKCTL_CGR2] + orr r1, r1, #0x00C00000 + str r1, [r0, #CLKCTL_CGR2] .endm .macro setup_sdram diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index c835b0edeb..2aa000f238 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -98,6 +98,26 @@ static void setup_iomux_spi(void) mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); } +static void setup_iomux_usbotg(void) +{ + int in_pad, out_pad; + + /* Set up pins for USBOTG. */ + mxc_request_iomux(MX35_PIN_USBOTG_PWR, + MUX_CONFIG_SION | MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_USBOTG_OC, + MUX_CONFIG_SION | MUX_CONFIG_FUNC); + + in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS | + PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW; + out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE | + PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW; + + mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad); + mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad); +} + static void setup_iomux_fec(void) { int pad; @@ -189,6 +209,7 @@ int board_early_init_f(void) __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); setup_iomux_i2c(); + setup_iomux_usbotg(); setup_iomux_fec(); setup_iomux_spi(); |