2 files changed, 22 insertions, 6 deletions
diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c
index 4dd1e63a83..c66883793c 100644
--- a/board/freescale/mx31ads/mx31ads.c
+++ b/board/freescale/mx31ads/mx31ads.c
@@ -25,6 +25,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -48,9 +49,16 @@ int board_early_init_f(void)
 	 * the only non-zero field "Wait State Control" is set to half the
 	 * default value.
 	 */
-	__REG(CSCR_U(0)) = 0x00000f00;
-	__REG(CSCR_L(0)) = 0x10000D03;
-	__REG(CSCR_A(0)) = 0x00720900;
+	static const struct mxc_weimcs cs0 = {
+		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  0, 15, 0,  0,  0),
+		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+		CSCR_L(1,  0,   0,   0,  0,  1,  5,  0,  0,  0,   1,   1),
+		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+		CSCR_A(0,   0,  7,  2,  0,  0,  2,  1,  0,  0,  0,  0,   0,   0)
+	};
+
+	mxc_setup_weimcs(0, &cs0);
 
 	/* setup pins for UART1 */
 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
index 276d45153a..0e7e0ce347 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -28,6 +28,7 @@
 #include <netdev.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
 #include <watchdog.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -50,9 +51,16 @@ int dram_init(void)
 int board_early_init_f(void)
 {
 	/* CS5: CPLD incl. network controller */
-	__REG(CSCR_U(5)) = 0x0000d843;
-	__REG(CSCR_L(5)) = 0x22252521;
-	__REG(CSCR_A(5)) = 0x22220a00;
+	static const struct mxc_weimcs cs5 = {
+		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 24, 0,  4,  3),
+		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+		CSCR_L(2,  2,   2,   5,  2,  0,  5,  2,  0,  0,   0,   1),
+		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+		CSCR_A(2,   2,  2,  2,  0,  0,  2,  2,  0,  0,  0,  0,   0,  0)
+	};
+
+	mxc_setup_weimcs(5, &cs5);
 
 	/* Setup UART1 and SPI2 pins */
 	mx31_uart1_hw_init();