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-rw-r--r--board/gateworks/gw_ventana/MAINTAINERS4
-rw-r--r--board/gateworks/gw_ventana/common.c490
-rw-r--r--board/gateworks/gw_ventana/common.h2
-rw-r--r--board/gateworks/gw_ventana/eeprom.c15
-rw-r--r--board/gateworks/gw_ventana/gsc.c4
-rw-r--r--board/gateworks/gw_ventana/gw_ventana.c52
-rw-r--r--board/gateworks/gw_ventana/gw_ventana_spl.c56
-rw-r--r--board/gateworks/gw_ventana/ventana_eeprom.h3
8 files changed, 587 insertions, 39 deletions
diff --git a/board/gateworks/gw_ventana/MAINTAINERS b/board/gateworks/gw_ventana/MAINTAINERS
index b44fb4dc4b..265ddac1c0 100644
--- a/board/gateworks/gw_ventana/MAINTAINERS
+++ b/board/gateworks/gw_ventana/MAINTAINERS
@@ -3,4 +3,6 @@ M: Tim Harvey <tharvey@gateworks.com>
S: Maintained
F: board/gateworks/gw_ventana/
F: include/configs/gw_ventana.h
-F: configs/gwventana_defconfig
+F: configs/gwventana_nand_defconfig
+F: configs/gwventana_emmc_defconfig
+F: configs/gwventana_gw5904_defconfig
diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 3dc5f88102..56a7b3e7fd 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -38,6 +38,44 @@ void setup_iomux_uart(void)
}
/* MMC */
+static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+/* 4-bit microSD on SD2 */
+static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ /* CD */
+ IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+/* 8-bit eMMC on SD2/NAND */
+static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -352,6 +390,107 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
+static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
+ /* RS232_EN# */
+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+ /* CAN_STBY */
+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+ /* USB_HUBRST# */
+ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* MX6_LOCLED# */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* IOEXP_PWREN# */
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+ /* IOEXP_IRQ# */
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+ /* DIOI2C_DIS# */
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+ /* VID_EN */
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+ /* PCI_RST# */
+ IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG),
+ /* RS485_EN */
+ IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+ /* USBH2_PEN (OTG) */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* 12V0_PWR_EN */
+ IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
+ /* BKLT_12VEN */
+ IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
+ /* EMMY_PDN# */
+ IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
+ /* EMMY_CFG1# */
+ IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
+ /* EMMY_CFG1# */
+ IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
+ /* USBH1_PEN (EHCI) */
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+ /* USBH2_PEN (OTG) */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* USBDPC_PEN */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* TOUCH_RST */
+ IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
+ /* AUDIO_RST# */
+ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
+ /* UART1_TEN# */
+ IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
+ /* MX6_LOCLED# */
+ IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+ /* LVDS_BKLEN # */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+ /* RGMII_PDWN# */
+ IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
+ /* TOUCH_IRQ# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* TOUCH_RST# */
+ IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
+ /* USB_HUBRST# */
+ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* MX6_LOCLED# */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* IOEXP_PWREN# */
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+ /* IOEXP_IRQ# */
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+ /* DIOI2C_DIS# */
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+ /* UART_RS485 */
+ IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
+ /* UART_HALF */
+ IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
+ /* SKT1_WDIS# */
+ IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
+ /* SKT1_RST# */
+ IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
+ /* SKT2_WDIS# */
+ IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
+ /* SKT2_RST# */
+ IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+ /* M2_OFF# */
+ IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
+ /* M2_WDIS# */
+ IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
+ /* M2_RST# */
+ IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
+};
+
/* Digital I/O */
struct dio_cfg gw51xx_dio[] = {
{
@@ -566,6 +705,111 @@ struct dio_cfg gw553x_dio[] = {
},
};
+struct dio_cfg gw560x_dio[] = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+ IMX_GPIO_NR(1, 20),
+ { 0, 0 },
+ 0
+ },
+};
+
+struct dio_cfg gw5903_dio[] = {
+};
+
+struct dio_cfg gw5904_dio[] = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+ IMX_GPIO_NR(1, 20),
+ { 0, 0 },
+ 0
+ },
+ {
+ {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
+ IMX_GPIO_NR(2, 0),
+ { 0, 0 },
+ 0
+ },
+ {
+ {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
+ IMX_GPIO_NR(2, 1),
+ { 0, 0 },
+ 0
+ },
+ {
+ {IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) },
+ IMX_GPIO_NR(2, 2),
+ { 0, 0 },
+ 0
+ },
+ {
+ {IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) },
+ IMX_GPIO_NR(2, 3),
+ { 0, 0 },
+ 0
+ },
+ {
+ {IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) },
+ IMX_GPIO_NR(2, 4),
+ { 0, 0 },
+ 0
+ },
+ {
+ {IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) },
+ IMX_GPIO_NR(2, 5),
+ { 0, 0 },
+ 0
+ },
+ {
+ {IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) },
+ IMX_GPIO_NR(2, 6),
+ { 0, 0 },
+ 0
+ },
+ {
+ {IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) },
+ IMX_GPIO_NR(2, 7),
+ { 0, 0 },
+ 0
+ },
+};
+
/*
* Board Specific GPIO
*/
@@ -588,6 +832,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.dioi2c_en = IMX_GPIO_NR(4, 5),
.pcie_sson = IMX_GPIO_NR(1, 20),
.otgpwr_en = IMX_GPIO_NR(3, 22),
+ .mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW51xx */
@@ -631,6 +876,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.rs232_en = GP_RS232_EN,
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
+ .mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW53xx */
@@ -654,6 +900,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.rs232_en = GP_RS232_EN,
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
+ .mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW54xx */
@@ -679,6 +926,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.rs232_en = GP_RS232_EN,
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
+ .mmc_cd = IMX_GPIO_NR(7, 0),
},
/* GW551x */
@@ -726,6 +974,58 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.wdis = IMX_GPIO_NR(7, 12),
.otgpwr_en = IMX_GPIO_NR(3, 22),
.vsel_pin = IMX_GPIO_NR(6, 14),
+ .mmc_cd = IMX_GPIO_NR(7, 0),
+ },
+
+ /* GW560x */
+ {
+ .gpio_pads = gw560x_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
+ .dio_cfg = gw560x_dio,
+ .dio_num = ARRAY_SIZE(gw560x_dio),
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 7),
+ IMX_GPIO_NR(4, 15),
+ },
+ .pcie_rst = IMX_GPIO_NR(4, 31),
+ .mezz_pwren = IMX_GPIO_NR(2, 19),
+ .mezz_irq = IMX_GPIO_NR(2, 18),
+ .rs232_en = GP_RS232_EN,
+ .vidin_en = IMX_GPIO_NR(3, 31),
+ .wdis = IMX_GPIO_NR(7, 12),
+ .otgpwr_en = IMX_GPIO_NR(4, 15),
+ .mmc_cd = IMX_GPIO_NR(7, 0),
+ },
+
+ /* GW5903 */
+ {
+ .gpio_pads = gw5903_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
+ .dio_cfg = gw5903_dio,
+ .dio_num = ARRAY_SIZE(gw5903_dio),
+ .leds = {
+ IMX_GPIO_NR(6, 14),
+ },
+ .otgpwr_en = IMX_GPIO_NR(4, 15),
+ .mmc_cd = IMX_GPIO_NR(6, 11),
+ },
+
+ /* GW5904 */
+ {
+ .gpio_pads = gw5904_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
+ .dio_cfg = gw5904_dio,
+ .dio_num = ARRAY_SIZE(gw5904_dio),
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 7),
+ IMX_GPIO_NR(4, 15),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 0),
+ .mezz_pwren = IMX_GPIO_NR(2, 19),
+ .mezz_irq = IMX_GPIO_NR(2, 18),
+ .otgpwr_en = IMX_GPIO_NR(3, 22),
},
};
@@ -834,6 +1134,50 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_direction_input(gpio_cfg[board].vsel_pin);
gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin);
}
+
+ /* microSD CD */
+ if (gpio_cfg[board].mmc_cd) {
+ gpio_request(gpio_cfg[board].mmc_cd, "sd_cd");
+ gpio_direction_input(gpio_cfg[board].mmc_cd);
+ }
+
+ /* Anything else board specific */
+ switch(board) {
+ case GW560x:
+ gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
+ gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
+ break;
+ case GW5903:
+ gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
+ gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
+ gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
+ gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
+ gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
+ gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
+ gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
+ gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
+ gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#");
+ gpio_direction_input(IMX_GPIO_NR(4, 6));
+ gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst");
+ gpio_direction_output(IMX_GPIO_NR(4, 8), 1);
+ gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
+ gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
+ break;
+ case GW5904:
+ gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
+ gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
+ gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
+ gpio_direction_output(IMX_GPIO_NR(5, 12), 1);
+ gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#");
+ gpio_direction_output(IMX_GPIO_NR(5, 13), 1);
+ gpio_request(IMX_GPIO_NR(1, 15), "m2_off#");
+ gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+ gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#");
+ gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
+ gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
+ gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
+ break;
+ }
}
/* setup GPIO pinmux and default configuration per baseboard and env */
@@ -926,6 +1270,8 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
void setup_pmic(void)
{
struct pmic *p;
+ struct ventana_board_info ventana_info;
+ int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
u32 reg;
i2c_set_bus_num(CONFIG_I2C_PMIC);
@@ -958,23 +1304,40 @@ void setup_pmic(void)
debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
power_ltc3676_init(CONFIG_I2C_PMIC);
p = pmic_get("LTC3676_PMIC");
- if (p && !pmic_probe(p)) {
- puts("PMIC: LTC3676\n");
- /*
- * set board-specific scalar for max CPU frequency
- * per CPU based on the LDO enabled Operating Ranges
- * defined in the respective IMX6DQ and IMX6SDL
- * datasheets. The voltage resulting from the R1/R2
- * feedback inputs on Ventana is 1308mV. Note that this
- * is a bit shy of the Vmin of 1350mV in the datasheet
- * for LDO enabled mode but is as high as we can go.
- *
- * We will rely on an OS kernel driver to properly
- * regulate these per CPU operating point and use LDO
- * bypass mode when using the higher frequency
- * operating points to compensate as LDO bypass mode
- * allows the rails be 125mV lower.
- */
+ if (!p || pmic_probe(p))
+ return;
+ puts("PMIC: LTC3676\n");
+ /*
+ * set board-specific scalar for max CPU frequency
+ * per CPU based on the LDO enabled Operating Ranges
+ * defined in the respective IMX6DQ and IMX6SDL
+ * datasheets. The voltage resulting from the R1/R2
+ * feedback inputs on Ventana is 1308mV. Note that this
+ * is a bit shy of the Vmin of 1350mV in the datasheet
+ * for LDO enabled mode but is as high as we can go.
+ */
+ switch (board) {
+ case GW560x:
+ /* mask PGOOD during SW3 transition */
+ pmic_reg_write(p, LTC3676_DVB3B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW3 (VDD_ARM) */
+ pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+ break;
+ case GW5903:
+ /* mask PGOOD during SW1 transition */
+ pmic_reg_write(p, LTC3676_DVB3B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW3 (VDD_ARM) */
+ pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+
+ /* mask PGOOD during SW4 transition */
+ pmic_reg_write(p, LTC3676_DVB4B,
+ 0x1f | LTC3676_PGOOD_MASK);
+ /* set SW4 (VDD_SOC) */
+ pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
+ break;
+ default:
/* mask PGOOD during SW1 transition */
pmic_reg_write(p, LTC3676_DVB1B,
0x1f | LTC3676_PGOOD_MASK);
@@ -991,23 +1354,96 @@ void setup_pmic(void)
}
#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
+static struct fsl_esdhc_cfg usdhc_cfg[2];
int board_mmc_init(bd_t *bis)
{
- /* Only one USDHC controller on Ventana */
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg.max_bus_width = 4;
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg);
+ struct ventana_board_info ventana_info;
+ int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+ int ret;
+
+ switch (board_type) {
+ case GW52xx:
+ case GW53xx:
+ case GW54xx:
+ case GW553x:
+ /* usdhc3: 4bit microSD */
+ SETUP_IOMUX_PADS(usdhc3_pads);
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ case GW560x:
+ /* usdhc2: 8-bit eMMC */
+ SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads);
+ usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[0].max_bus_width = 8;
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ if (ret)
+ return ret;
+ /* usdhc3: 4-bit microSD */
+ SETUP_IOMUX_PADS(usdhc3_pads);
+ usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+ case GW5903:
+ /* usdhc3: 8-bit eMMC */
+ SETUP_IOMUX_PADS(gw5904_emmc_pads);
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 8;
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ if (ret)
+ return ret;
+ /* usdhc2: 4-bit microSD */
+ SETUP_IOMUX_PADS(gw5904_mmc_pads);
+ usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+ case GW5904:
+ /* usdhc3: 8bit eMMC */
+ SETUP_IOMUX_PADS(gw5904_emmc_pads);
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 8;
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ default:
+ /* doesn't have MMC */
+ return -1;
+ }
}
int board_mmc_getcd(struct mmc *mmc)
{
+ struct ventana_board_info ventana_info;
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+ int gpio = gpio_cfg[board].mmc_cd;
+
/* Card Detect */
- gpio_request(GP_SD3_CD, "sd_cd");
- gpio_direction_input(GP_SD3_CD);
- return !gpio_get_value(GP_SD3_CD);
+ switch (board) {
+ case GW560x:
+ /* emmc is always present */
+ if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+ return 1;
+ break;
+ case GW5903:
+ case GW5904:
+ /* emmc is always present */
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ return 1;
+ break;
+ }
+
+ if (gpio) {
+ debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio));
+ return !gpio_get_value(gpio);
+ }
+
+ return -1;
}
+
#endif /* CONFIG_FSL_ESDHC */
diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h
index 18909a02b5..3eb4c59400 100644
--- a/board/gateworks/gw_ventana/common.h
+++ b/board/gateworks/gw_ventana/common.h
@@ -13,7 +13,6 @@
/* GPIO's common to all baseboards */
#define GP_PHY_RST IMX_GPIO_NR(1, 30)
-#define GP_SD3_CD IMX_GPIO_NR(7, 0)
#define GP_RS232_EN IMX_GPIO_NR(2, 11)
#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
@@ -79,6 +78,7 @@ struct ventana {
int rs232_en;
int otgpwr_en;
int vsel_pin;
+ int mmc_cd;
/* various features */
bool usd_vsel;
};
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
index 1382e5debe..2c07a84fff 100644
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -64,6 +64,7 @@ read_eeprom(int bus, struct ventana_board_info *info)
if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
baseboard = '0';
+ type = GW_UNKNOWN;
switch (baseboard) {
case '0': /* original GW5400-A prototype */
type = GW54proto;
@@ -91,10 +92,16 @@ read_eeprom(int bus, struct ventana_board_info *info)
type = GW553x;
break;
}
- /* fall through */
- default:
- printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
- type = GW_UNKNOWN;
+ break;
+ case '6':
+ if (info->model[4] == '0')
+ type = GW560x;
+ break;
+ case '9':
+ if (info->model[4] == '0' && info->model[5] == '3')
+ type = GW5903;
+ if (info->model[4] == '0' && info->model[5] == '4')
+ type = GW5904;
break;
}
return type;
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 613a275a8f..68b1ddb532 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -137,6 +137,10 @@ int gsc_info(int verbose)
break;
case '5': /* GW55xx */
break;
+ case '6': /* GW560x */
+ read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3);
+ read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
+ break;
}
return 0;
}
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 3f9d2f7010..dc8cd883e9 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -132,8 +132,9 @@ static void setup_iomux_enet(int gpio)
/* toggle PHY_RST# */
gpio_request(gpio, "phy_rst#");
gpio_direction_output(gpio, 0);
- mdelay(2);
+ mdelay(10);
gpio_set_value(gpio, 1);
+ mdelay(100);
}
#ifdef CONFIG_USB_EHCI_MX6
@@ -226,12 +227,56 @@ int board_phy_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
}
+ /* TI DP83867 */
+ else if (phydev->phy_id == 0x2000a231) {
+ /* configure register 0x170 for ref CLKOUT */
+ phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
+ phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
+ val &= ~0x1f00;
+ val |= 0x0b00; /* chD tx clock*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
+ }
+
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+ struct mii_dev *bus = phydev->bus;
+
+ /* GPIO[0] output, CLK125 */
+ debug("enabling RGMII_REFCLK\n");
+ bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
+ 0x1a /*MV_SCRATCH_MISC*/,
+ (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
+ bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
+ 0x1a /*MV_SCRATCH_MISC*/,
+ (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
+
+ /* RGMII delay - Physical Control register bit[15:14] */
+ debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
+ /* forced 1000mbps full-duplex link */
+ bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
+ phydev->autoneg = AUTONEG_DISABLE;
+ phydev->speed = SPEED_1000;
+ phydev->duplex = DUPLEX_FULL;
+
+ /* LED configuration: 7:4-green (8=Activity) 3:0 amber (9=10Link) */
+ bus->write(bus, 0x10, 0, 0x16, 0x8089);
+ bus->write(bus, 0x11, 0, 0x16, 0x8089);
+ bus->write(bus, 0x12, 0, 0x16, 0x8089);
+ bus->write(bus, 0x13, 0, 0x16, 0x8089);
+
+ return 0;
+}
+#endif // CONFIG_MV88E61XX_SWITCH
+
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FEC_MXC
@@ -661,6 +706,8 @@ int checkboard(void)
static const struct boot_mode board_boot_modes[] = {
/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+ { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
+ { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/GW5904 */
{ NULL, 0 },
};
#endif
@@ -712,7 +759,8 @@ int misc_init_r(void)
setenv("fdt_file1", fdt);
if (board_type != GW551x &&
board_type != GW552x &&
- board_type != GW553x)
+ board_type != GW553x &&
+ board_type != GW560x)
str[4] = 'x';
str[5] = 'x';
str[6] = 0;
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index 8cc2a571d3..6060b44216 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -374,6 +374,25 @@ static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
.p1_mpwrdlctl = 0x383A3930,
};
+static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x001F003F,
+ .p0_mpwldectrl1 = 0x001F001F,
+ .p1_mpwldectrl0 = 0x001F004E,
+ .p1_mpwldectrl1 = 0x0059001F,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x42220225,
+ .p0_mpdgctrl1 = 0x0213021F,
+ .p1_mpdgctrl0 = 0x022C0242,
+ .p1_mpdgctrl1 = 0x022C0244,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x474A4C4A,
+ .p1_mprddlctl = 0x48494C45,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x3F3F3F36,
+ .p1_mpwrdlctl = 0x3F36363F,
+};
+
static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x002A0025,
@@ -510,10 +529,25 @@ static void spl_dram_init(int width, int size_mb, int board_model)
calib = &mx6sdl_256x64_mmdc_calib;
debug("4gB density\n");
} else if (width == 64 && size_mb == 4096) {
- mem = &mt41k512m16ha_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &mx6dq_512x64_mmdc_calib;
- debug("8gB density\n");
+ switch(board_model) {
+ case GW5903:
+ /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
+ mem = &mt41k256m16ha_125;
+ debug("4gB density\n");
+ if (!is_cpu_type(MXC_CPU_MX6Q)) {
+ calib = &mx6sdl_256x64x2_mmdc_calib;
+ sysinfo.ncs = 2;
+ sysinfo.cs_density = 18; /* CS0_END=71 */
+ sysinfo.cs1_mirror = 1; /* mirror enabled */
+ }
+ break;
+ default:
+ mem = &mt41k512m16ha_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_512x64_mmdc_calib;
+ debug("8gB density\n");
+ break;
+ }
}
if (!(mem && calib)) {
@@ -608,6 +642,20 @@ void board_init_f(ulong dummy)
memset(__bss_start, 0, __bss_end - __bss_start);
}
+void board_boot_order(u32 *spl_boot_list)
+{
+ spl_boot_list[0] = spl_boot_device();
+ switch (spl_boot_list[0]) {
+ case BOOT_DEVICE_NAND:
+ spl_boot_list[1] = BOOT_DEVICE_MMC1;
+ spl_boot_list[2] = BOOT_DEVICE_UART;
+ break;
+ case BOOT_DEVICE_MMC1:
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ break;
+ }
+}
+
/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
/* its our chance to print info about boot device */
void spl_board_init(void)
diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
index 9ffad58e03..8a42d67ba1 100644
--- a/board/gateworks/gw_ventana/ventana_eeprom.h
+++ b/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -112,6 +112,9 @@ enum {
GW551x,
GW552x,
GW553x,
+ GW560x,
+ GW5903,
+ GW5904,
GW_UNKNOWN,
GW_BADCRC,
};
generated by cgit (git 2.34.1) at 2025-01-17 16:36:47 +0000