diff options
Diffstat (limited to 'board/intel')
| -rw-r--r-- | board/intel/Kconfig | 51 | ||||
| -rw-r--r-- | board/intel/crownbay/Kconfig | 3 | ||||
| -rw-r--r-- | board/intel/crownbay/crownbay.c | 2 | ||||
| -rw-r--r-- | board/intel/galileo/Kconfig | 3 | ||||
| -rw-r--r-- | board/intel/minnowmax/Kconfig | 3 | ||||
| -rw-r--r-- | board/intel/minnowmax/minnowmax.c | 2 |
6 files changed, 62 insertions, 2 deletions
diff --git a/board/intel/Kconfig b/board/intel/Kconfig new file mode 100644 index 0000000000..7fe21b983a --- /dev/null +++ b/board/intel/Kconfig @@ -0,0 +1,51 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_INTEL + +choice + prompt "Mainboard model" + +config TARGET_CROWNBAY + bool "Crown Bay" + help + This is the Intel Crown Bay Customer Reference Board. It contains + the Intel Atom Processor E6xx populated on the COM Express module + with 1GB DDR2 soldered down memory and a carrier board with the + Intel Platform Controller Hub EG20T, other system components and + peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. + +config TARGET_GALILEO + bool "Galileo" + help + This is the Intel Galileo board, which is the first in a family of + Arduino-certified development and prototyping boards based on Intel + architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit + single-core, single-thread, Intel Pentium processor instrunction set + architecture (ISA) compatible, operating at speeds up to 400Mhz, + along with 256MB DDR3 memory. It supports a wide range of industry + standard I/O interfaces, including a full-sized mini-PCIe slot, + one 100Mb Ethernet port, a microSD card slot, a USB host port and + a USB client port. + +config TARGET_MINNOWMAX + bool "Minnowboard MAX" + help + This is the Intel Minnowboard MAX. It contains an Atom E3800 + processor in a small form factor with Ethernet, micro-SD, USB 2, + USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. + It requires some binary blobs - see README.x86 for details. + + Note that PCIE_ECAM_BASE is set up by the FSP so the value used + by U-Boot matches that value. + +endchoice + +source "board/intel/crownbay/Kconfig" +source "board/intel/galileo/Kconfig" +source "board/intel/minnowmax/Kconfig" + +endif diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig index 762663a001..b30701afc8 100644 --- a/board/intel/crownbay/Kconfig +++ b/board/intel/crownbay/Kconfig @@ -12,6 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "crownbay" +config SYS_TEXT_BASE + default 0xfff00000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 2a254efe3d..31bb320213 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { - lpc47m_enable_serial(SERIAL_DEV, UART0_BASE); + lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ); return 0; } diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig index 85afbbc8c5..6515bacd76 100644 --- a/board/intel/galileo/Kconfig +++ b/board/intel/galileo/Kconfig @@ -12,6 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "galileo" +config SYS_TEXT_BASE + default 0xfff10000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig index 43c50a519b..f2a0b71c44 100644 --- a/board/intel/minnowmax/Kconfig +++ b/board/intel/minnowmax/Kconfig @@ -12,6 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "minnowmax" +config SYS_TEXT_BASE + default 0xfff00000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select X86_RESET_VECTOR diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c index 6e82b16335..fd2070afb2 100644 --- a/board/intel/minnowmax/minnowmax.c +++ b/board/intel/minnowmax/minnowmax.c @@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { - lpc47m_enable_serial(SERIAL_DEV, UART0_BASE); + lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ); return 0; } |