diff options
Diffstat (limited to 'board/isee/igep00x0')
| -rw-r--r-- | board/isee/igep00x0/MAINTAINERS | 3 | ||||
| -rw-r--r-- | board/isee/igep00x0/Makefile | 6 | ||||
| -rw-r--r-- | board/isee/igep00x0/common.c | 68 | ||||
| -rw-r--r-- | board/isee/igep00x0/igep00x0.c | 198 | ||||
| -rw-r--r-- | board/isee/igep00x0/igep00x0.h | 13 | ||||
| -rw-r--r-- | board/isee/igep00x0/spl.c | 64 |
6 files changed, 216 insertions, 136 deletions
diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS index 720ef2aa69..d75d400eed 100644 --- a/board/isee/igep00x0/MAINTAINERS +++ b/board/isee/igep00x0/MAINTAINERS @@ -3,6 +3,5 @@ M: Enric Balletbo i Serra <eballetbo@gmail.com> S: Maintained F: board/isee/igep00x0/ F: include/configs/omap3_igep00x0.h -F: configs/igep0020_defconfig -F: configs/igep0030_defconfig +F: configs/igep00x0_defconfig F: configs/igep0032_defconfig diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile index 68b151c3c5..74594da771 100644 --- a/board/isee/igep00x0/Makefile +++ b/board/isee/igep00x0/Makefile @@ -5,4 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := igep00x0.o +ifdef CONFIG_SPL_BUILD +obj-y := spl.o common.o +else +obj-y := igep00x0.o common.o +endif diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c new file mode 100644 index 0000000000..e59516f612 --- /dev/null +++ b/board/isee/igep00x0/common.c @@ -0,0 +1,68 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/omap_mmc.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <jffs2/load_kernel.h> +#include <linux/mtd/nand.h> +#include "igep00x0.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + int loops = 100; + + /* find out flash memory type, assume NAND first */ + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + gpmc_init(); + + /* Issue a RESET and then READID */ + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { + udelay(1); + if (--loops == 0) { + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; + gpmc_init(); /* reinitialize for OneNAND */ + break; + } + } + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +#if defined(CONFIG_MMC) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, -1, -1); +} + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index a7a75601dd..5c7f256711 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -17,18 +17,14 @@ #include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> -#include <asm/mach-types.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> -#include <linux/mtd/nand.h> #include <linux/mtd/onenand.h> #include <jffs2/load_kernel.h> #include <mtd_node.h> #include <fdt_support.h> #include "igep00x0.h" -DECLARE_GLOBAL_DATA_PTR; - static const struct ns16550_platdata igep_serial = { .base = OMAP34XX_UART3, .reg_shift = 2, @@ -42,96 +38,41 @@ U_BOOT_DEVICE(igep_uart) = { }; /* - * Routine: board_init - * Description: Early hardware init. + * Routine: get_board_revision + * Description: GPIO_28 and GPIO_129 are used to read board and revision from + * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from + * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because + * this functionality is shared by USB HOST. + * Once USB reset is applied, U-boot configures these pins as input pullup to + * detect board and revision: + * IGEP0020-RF = 0b00 + * IGEP0020-RC = 0b01 + * IGEP0030-RG = 0b10 + * IGEP0030-RE = 0b11 */ -int board_init(void) +static int get_board_revision(void) { - int loops = 100; - - /* find out flash memory type, assume NAND first */ - gpmc_cs0_flash = MTD_DEV_TYPE_NAND; - gpmc_init(); + int revision; - /* Issue a RESET and then READID */ - writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); - writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); - while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) - != NAND_STATUS_READY) { - udelay(1); - if (--loops == 0) { - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; - gpmc_init(); /* reinitialize for OneNAND */ - break; - } - } + gpio_request(IGEP0030_USB_TRANSCEIVER_RESET, + "igep0030_usb_transceiver_reset"); + gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0); - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection"); + gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION); + revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION); + gpio_free(GPIO_IGEP00X0_BOARD_DETECTION); -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON); -#endif - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on both banks. - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ - int mfr, id, err = identify_nand_chip(&mfr, &id); - - timings->mr = MICRON_V_MR_165; - if (!err) { - switch (mfr) { - case NAND_MFR_HYNIX: - timings->mcfg = HYNIX_V_MCFG_200(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_200; - timings->ctrlb = HYNIX_V_ACTIMB_200; - break; - case NAND_MFR_MICRON: - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - break; - default: - /* Should not happen... */ - break; - } - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - gpmc_cs0_flash = MTD_DEV_TYPE_NAND; - } else { - if (get_cpu_family() == CPU_OMAP34XX) { - timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_165; - timings->ctrlb = NUMONYX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - } else { - timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_200; - timings->ctrlb = NUMONYX_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - } - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; - } -} + gpio_request(GPIO_IGEP00X0_REVISION_DETECTION, + "igep00x0_revision_detection"); + gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION); + revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION); + gpio_free(GPIO_IGEP00X0_REVISION_DETECTION); -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - /* break into full u-boot on 'c' */ - if (serial_tstc() && serial_getc() == 'c') - return 1; + gpio_free(IGEP0030_USB_TRANSCEIVER_RESET); - return 0; + return revision; } -#endif -#endif int onenand_board_init(struct mtd_info *mtd) { @@ -199,20 +140,6 @@ int board_eth_init(bd_t *bis) static inline void setup_net_chip(void) {} #endif -#if defined(CONFIG_MMC) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#if defined(CONFIG_MMC) -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif - #ifdef CONFIG_OF_BOARD_SETUP static int ft_enable_by_compatible(void *blob, char *compat, int enable) { @@ -247,31 +174,69 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif -void set_fdt(void) +void set_led(void) { - switch (gd->bd->bi_arch_number) { - case MACH_TYPE_IGEP0020: - env_set("fdtfile", "omap3-igep0020.dtb"); + switch (get_board_revision()) { + case 0: + case 1: + gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led"); + gpio_direction_output(IGEP0020_GPIO_LED, 1); + break; + case 2: + case 3: + gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led"); + gpio_direction_output(IGEP0030_GPIO_LED, 0); break; - case MACH_TYPE_IGEP0030: - env_set("fdtfile", "omap3-igep0030.dtb"); + default: + /* Should not happen... */ break; } } +void set_boardname(void) +{ + char rev[5] = { 'F','C','G','E', }; + int i = get_board_revision(); + + rev[i+1] = 0; + env_set("board_rev", rev + i); + env_set("board_name", i < 2 ? "igep0020" : "igep0030"); +} + /* * Routine: misc_init_r * Description: Configure board specific parts */ int misc_init_r(void) { + t2_t *t2_base = (t2_t *)T2_BASE; + u32 pbias_lite; + twl4030_power_init(); + /* set VSIM to 1.8V */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED, + TWL4030_PM_RECEIVER_VSIM_VSEL_18, + TWL4030_PM_RECEIVER_VSIM_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + + /* set up dual-voltage GPIOs to 1.8V */ + pbias_lite = readl(&t2_base->pbias_lite); + pbias_lite &= ~PBIASLITEVMODE1; + pbias_lite |= PBIASLITEPWRDNZ1; + writel(pbias_lite, &t2_base->pbias_lite); + if (get_cpu_family() == CPU_OMAP36XX) + writel(readl(OMAP34XX_CTRL_WKUP_CTRL) | + OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, + OMAP34XX_CTRL_WKUP_CTRL); + setup_net_chip(); omap_die_id_display(); - set_fdt(); + set_led(); + + set_boardname(); return 0; } @@ -292,22 +257,3 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) *mtdparts = parts; } } - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); - -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) - MUX_IGEP0020(); -#endif - -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) - MUX_IGEP0030(); -#endif -} diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index 5698efab5d..1cbe7c94d9 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -103,6 +103,8 @@ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ @@ -117,13 +119,10 @@ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\ + MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ #endif - -#define MUX_IGEP0020() \ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\ - -#define MUX_IGEP0030() \ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */ diff --git a/board/isee/igep00x0/spl.c b/board/isee/igep00x0/spl.c new file mode 100644 index 0000000000..eb705cbe88 --- /dev/null +++ b/board/isee/igep00x0/spl.c @@ -0,0 +1,64 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <jffs2/load_kernel.h> +#include <linux/mtd/nand.h> +#include "igep00x0.h" + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + int mfr, id, err = identify_nand_chip(&mfr, &id); + + timings->mr = MICRON_V_MR_165; + if (!err) { + switch (mfr) { + case NAND_MFR_HYNIX: + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + break; + case NAND_MFR_MICRON: + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + break; + default: + /* Should not happen... */ + break; + } + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + } else { + if (get_cpu_family() == CPU_OMAP34XX) { + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; + } +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif |