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-rw-r--r--board/mpc8641hpcn/Makefile52
-rw-r--r--board/mpc8641hpcn/config.mk31
-rw-r--r--board/mpc8641hpcn/init.S179
-rw-r--r--board/mpc8641hpcn/mpc8641hpcn.c426
-rw-r--r--board/mpc8641hpcn/pixis.c321
-rw-r--r--board/mpc8641hpcn/pixis.h33
-rw-r--r--board/mpc8641hpcn/sys_eeprom.c256
-rw-r--r--board/mpc8641hpcn/u-boot.lds148
8 files changed, 1446 insertions, 0 deletions
diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile
new file mode 100644
index 0000000000..46214ed214
--- /dev/null
+++ b/board/mpc8641hpcn/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o pixis.o sys_eeprom.o
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+.PHONY: distclean
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude ($obj).depend
+
+#########################################################################
diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk
new file mode 100644
index 0000000000..989a40b015
--- /dev/null
+++ b/board/mpc8641hpcn/config.mk
@@ -0,0 +1,31 @@
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Jeff Brown
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8641hpcn board
+# default CCSRBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff01000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S
new file mode 100644
index 0000000000..6b3e2d275d
--- /dev/null
+++ b/board/mpc8641hpcn/init.S
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc86xx.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xf800_0000 0xf80f_ffff CCSRBAR 1M
+ * 0xf810_0000 0xf81f_ffff PIXIS 1M
+ * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
+ *
+ * Notes:
+ * CCSRBAR don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#else
+#define LAWBAR1 0
+#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
+#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR4 ((0xf8100000>>12) & 0xffffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
+
+#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
+#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
+
+#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
+#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#else
+#define LAWBAR8 0
+#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ lis r7,CFG_CCSRBAR@h
+ ori r7,r7,CFG_CCSRBAR@l
+
+ addi r4,r7,0
+ addi r5,r7,0
+
+ /* Skip LAWAR0, start at LAWAR1 */
+ lis r6,LAWBAR1@h
+ ori r6,r6,LAWBAR1@l
+ stwu r6, 0xc28(r4)
+
+ lis r6,LAWAR1@h
+ ori r6,r6,LAWAR1@l
+ stwu r6, 0xc30(r5)
+
+ /* LAWBAR2, LAWAR2 */
+ lis r6,LAWBAR2@h
+ ori r6,r6,LAWBAR2@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR2@h
+ ori r6,r6,LAWAR2@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR3, LAWAR3 */
+ lis r6,LAWBAR3@h
+ ori r6,r6,LAWBAR3@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR3@h
+ ori r6,r6,LAWAR3@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR4, LAWAR4 */
+ lis r6,LAWBAR4@h
+ ori r6,r6,LAWBAR4@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR4@h
+ ori r6,r6,LAWAR4@l
+ stwu r6, 0x20(r5)
+ /* LAWBAR5, LAWAR5 */
+ lis r6,LAWBAR5@h
+ ori r6,r6,LAWBAR5@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR5@h
+ ori r6,r6,LAWAR5@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR6, LAWAR6 */
+ lis r6,LAWBAR6@h
+ ori r6,r6,LAWBAR6@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR6@h
+ ori r6,r6,LAWAR6@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR7, LAWAR7 */
+ lis r6,LAWBAR7@h
+ ori r6,r6,LAWBAR7@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR7@h
+ ori r6,r6,LAWAR7@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR8, LAWAR8 */
+ lis r6,LAWBAR8@h
+ ori r6,r6,LAWBAR8@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR8@h
+ ori r6,r6,LAWAR8@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR9, LAWAR9 */
+ lis r6,LAWBAR9@h
+ ori r6,r6,LAWBAR9@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR9@h
+ ori r6,r6,LAWAR9@l
+ stwu r6, 0x20(r5)
+
+ blr
diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c
new file mode 100644
index 0000000000..b2cf4a9566
--- /dev/null
+++ b/board/mpc8641hpcn/mpc8641hpcn.c
@@ -0,0 +1,426 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <spd.h>
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+#endif
+
+#include "pixis.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+#include "spd_sdram.h"
+#endif
+
+void sdram_init(void);
+long int fixed_sdram(void);
+
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MPC8641HPCN\n");
+
+#ifdef CONFIG_PCI
+
+ volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_pex_t *pex1 = &immap->im_pex1;
+
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+ uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+ uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
+
+ if ((io_sel == 2 || io_sel == 3 || io_sel == 5
+ || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
+ && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+ debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
+ debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
+ if (pex1->pme_msg_det) {
+ pex1->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pex1->pme_msg_det);
+ }
+ debug("\n");
+ } else {
+ puts("PCI-EXPRESS 1: Disabled\n");
+ }
+
+#else
+ puts("PCI-EXPRESS1: Disabled\n");
+#endif
+
+ return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+
+#if defined(CFG_RAMBOOT)
+ puts(" DDR: ");
+ return dram_size;
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ puts("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+long int
+fixed_sdram(void)
+{
+#if !defined(CFG_RAMBOOT)
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
+ ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode_1 = CFG_DDR_MODE_1;
+ ddr->sdram_mode_2 = CFG_DDR_MODE_2;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ ddr->sdram_data_init = CFG_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
+ ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
+ ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
+
+#if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000008D;
+ ddr->err_sbe = 0x00ff0000;
+#endif
+ asm("sync;isync");
+
+ udelay(500);
+
+#if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
+#else
+ ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
+ ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
+#endif
+ asm("sync; isync");
+
+ udelay(500);
+#endif
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_fsl86xxads_config_table[] = {
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
+ {}
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc86xxcts_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+void pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ extern void pci_mpc86xx_init(struct pci_controller *hose);
+
+ pci_mpc86xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+}
+#endif
+
+
+void
+mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ char cmd;
+ ulong val;
+ ulong corepll;
+
+ /*
+ * No args is a simple reset request.
+ */
+ if (argc <= 1) {
+ out8(PIXIS_BASE + PIXIS_RST, 0);
+ /* not reached */
+ }
+
+ cmd = argv[1][1];
+ switch (cmd) {
+ case 'f': /* reset with frequency changed */
+ if (argc < 5)
+ goto my_usage;
+ read_from_px_regs(0);
+
+ val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
+
+ corepll = strfractoint(argv[3]);
+ val = val + set_px_corepll(corepll);
+ val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
+ if (val == 3) {
+ puts("Setting registers VCFGEN0 and VCTL\n");
+ read_from_px_regs(1);
+ puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
+ set_px_go();
+ } else
+ goto my_usage;
+
+ while (1) ; /* Not reached */
+
+ case 'l':
+ if (argv[2][1] == 'f') {
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ /* reset with frequency changed */
+ val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
+
+ corepll = strfractoint(argv[4]);
+ val = val + set_px_corepll(corepll);
+ val = val + set_px_mpxpll(simple_strtoul(argv[5],
+ NULL, 10));
+ if (val == 3) {
+ puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs(1);
+ read_from_px_regs_altbank(1);
+ puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
+ set_px_go_with_watchdog();
+ } else
+ goto my_usage;
+
+ while (1) ; /* Not reached */
+
+ } else if (argv[2][1] == 'd') {
+ /*
+ * Reset from alternate bank without changing
+ * frequencies but with watchdog timer enabled.
+ */
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs_altbank(1);
+ puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
+ set_px_go_with_watchdog();
+ while (1) ; /* Not reached */
+
+ } else {
+ /*
+ * Reset from next bank without changing
+ * frequency and without watchdog timer enabled.
+ */
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ if (argc > 2)
+ goto my_usage;
+ puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs_altbank(1);
+ puts("Resetting board to boot from the other bank....\n");
+ set_px_go();
+ }
+
+ default:
+ goto my_usage;
+ }
+
+my_usage:
+ puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
+ puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
+ puts(" reset altbank [wd]\n");
+ puts("For example: reset cf 40 2.5 10\n");
+ puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
+}
+
+
+/*
+ * get_board_sys_clk
+ * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+ u8 i, go_bit, rd_clks;
+ ulong val = 0;
+
+ go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+ go_bit &= 0x01;
+
+ rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+ rd_clks &= 0x1C;
+
+ /*
+ * Only if both go bit and the SCLK bit in VCFGEN0 are set
+ * should we be using the AUX register. Remember, we also set the
+ * GO bit to boot from the alternate bank on the on-board flash
+ */
+
+ if (go_bit) {
+ if (rd_clks == 0x1c)
+ i = in8(PIXIS_BASE + PIXIS_AUX);
+ else
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ } else {
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ }
+
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33000000;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66000000;
+ break;
+ case 4:
+ val = 83000000;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 134000000;
+ break;
+ case 7:
+ val = 166000000;
+ break;
+ }
+
+ return val;
+}
diff --git a/board/mpc8641hpcn/pixis.c b/board/mpc8641hpcn/pixis.c
new file mode 100644
index 0000000000..964a17ca08
--- /dev/null
+++ b/board/mpc8641hpcn/pixis.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/cache.h>
+#include <mpc86xx.h>
+
+#include "pixis.h"
+
+
+/*
+ * Per table 27, page 58 of MPC8641HPCN spec.
+ */
+int set_px_sysclk(ulong sysclk)
+{
+ u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
+
+ switch (sysclk) {
+ case 33:
+ sysclk_s = 0x04;
+ sysclk_r = 0x04;
+ sysclk_v = 0x07;
+ sysclk_aux = 0x00;
+ break;
+ case 40:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x20;
+ sysclk_aux = 0x01;
+ break;
+ case 50:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x2A;
+ sysclk_aux = 0x02;
+ break;
+ case 66:
+ sysclk_s = 0x01;
+ sysclk_r = 0x04;
+ sysclk_v = 0x04;
+ sysclk_aux = 0x03;
+ break;
+ case 83:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x4B;
+ sysclk_aux = 0x04;
+ break;
+ case 100:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x5C;
+ sysclk_aux = 0x05;
+ break;
+ case 134:
+ sysclk_s = 0x06;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x3B;
+ sysclk_aux = 0x06;
+ break;
+ case 166:
+ sysclk_s = 0x06;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x4B;
+ sysclk_aux = 0x07;
+ break;
+ default:
+ printf("Unsupported SYSCLK frequency.\n");
+ return 0;
+ }
+
+ vclkh = (sysclk_s << 5) | sysclk_r;
+ vclkl = sysclk_v;
+
+ out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
+ out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
+
+ out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
+
+ return 1;
+}
+
+
+int set_px_mpxpll(ulong mpxpll)
+{
+ u8 tmp;
+ u8 val;
+
+ switch (mpxpll) {
+ case 2:
+ case 4:
+ case 6:
+ case 8:
+ case 10:
+ case 12:
+ case 14:
+ case 16:
+ val = (u8) mpxpll;
+ break;
+ default:
+ printf("Unsupported MPXPLL ratio.\n");
+ return 0;
+ }
+
+ tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
+ tmp = (tmp & 0xF0) | (val & 0x0F);
+ out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
+
+ return 1;
+}
+
+
+int set_px_corepll(ulong corepll)
+{
+ u8 tmp;
+ u8 val;
+
+ switch ((int)corepll) {
+ case 20:
+ val = 0x08;
+ break;
+ case 25:
+ val = 0x0C;
+ break;
+ case 30:
+ val = 0x10;
+ break;
+ case 35:
+ val = 0x1C;
+ break;
+ case 40:
+ val = 0x14;
+ break;
+ case 45:
+ val = 0x0E;
+ break;
+ default:
+ printf("Unsupported COREPLL ratio.\n");
+ return 0;
+ }
+
+ tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
+ tmp = (tmp & 0xE0) | (val & 0x1F);
+ out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
+
+ return 1;
+}
+
+
+void read_from_px_regs(int set)
+{
+ u8 mask = 0x1C;
+ u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+
+ if (set)
+ tmp = tmp | mask;
+ else
+ tmp = tmp & ~mask;
+ out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
+}
+
+
+void read_from_px_regs_altbank(int set)
+{
+ u8 mask = 0x04;
+ u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
+
+ if (set)
+ tmp = tmp | mask;
+ else
+ tmp = tmp & ~mask;
+ out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
+}
+
+
+void set_altbank(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
+ tmp ^= 0x40;
+
+ out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
+}
+
+
+void set_px_go(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp | 0x01;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+void set_px_go_with_watchdog(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp | 0x09;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ /* setting VCTL[WDEN] to 0 to disable watch dog */
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp &= ~0x08;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ diswd, 1, 0, disable_watchdog,
+ "diswd - Disable watchdog timer \n",
+ NULL);
+
+/*
+ * This function takes the non-integral cpu:mpx pll ratio
+ * and converts it to an integer that can be used to assign
+ * FPGA register values.
+ * input: strptr i.e. argv[2]
+ */
+
+ulong strfractoint(uchar *strptr)
+{
+ int i, j, retval;
+ int mulconst;
+ int intarr_len = 0, decarr_len = 0, no_dec = 0;
+ ulong intval = 0, decval = 0;
+ uchar intarr[3], decarr[3];
+
+ /* Assign the integer part to intarr[]
+ * If there is no decimal point i.e.
+ * if the ratio is an integral value
+ * simply create the intarr.
+ */
+ i = 0;
+ while (strptr[i] != 46) {
+ if (strptr[i] == 0) {
+ no_dec = 1;
+ break;
+ }
+ intarr[i] = strptr[i];
+ i++;
+ }
+
+ /* Assign length of integer part to intarr_len. */
+ intarr_len = i;
+ intarr[i] = '\0';
+
+ if (no_dec) {
+ /* Currently needed only for single digit corepll ratios */
+ mulconst = 10;
+ decval = 0;
+ } else {
+ j = 0;
+ i++; /* Skipping the decimal point */
+ while ((strptr[i] > 47) && (strptr[i] < 58)) {
+ decarr[j] = strptr[i];
+ i++;
+ j++;
+ }
+
+ decarr_len = j;
+ decarr[j] = '\0';
+
+ mulconst = 1;
+ for (i = 0; i < decarr_len; i++)
+ mulconst *= 10;
+ decval = simple_strtoul(decarr, NULL, 10);
+ }
+
+ intval = simple_strtoul(intarr, NULL, 10);
+ intval = intval * mulconst;
+
+ retval = intval + decval;
+
+ return retval;
+}
diff --git a/board/mpc8641hpcn/pixis.h b/board/mpc8641hpcn/pixis.h
new file mode 100644
index 0000000000..cd9a45db87
--- /dev/null
+++ b/board/mpc8641hpcn/pixis.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2006 Freescale Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+extern int set_px_sysclk(ulong sysclk);
+extern int set_px_mpxpll(ulong mpxpll);
+extern int set_px_corepll(ulong corepll);
+extern void read_from_px_regs(int set);
+extern void read_from_px_regs_altbank(int set);
+extern void set_altbank(void);
+extern void set_px_go(void);
+extern void set_px_go_with_watchdog(void);
+extern int disable_watchdog(cmd_tbl_t *cmdtp,
+ int flag, int argc, char *argv[]);
+extern ulong strfractoint(uchar *strptr);
diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/mpc8641hpcn/sys_eeprom.c
new file mode 100644
index 0000000000..74e2a3d46f
--- /dev/null
+++ b/board/mpc8641hpcn/sys_eeprom.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ * Haiying Wang (haiying.wang@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#ifdef CFG_ID_EEPROM
+typedef struct {
+ unsigned char id[4]; /* 0x0000 - 0x0003 */
+ unsigned char sn[12]; /* 0x0004 - 0x000F */
+ unsigned char errata[5]; /* 0x0010 - 0x0014 */
+ unsigned char date[7]; /* 0x0015 - 0x001a */
+ unsigned char res_1[37]; /* 0x001b - 0x003f */
+ unsigned char tab_size; /* 0x0040 */
+ unsigned char tab_flag; /* 0x0041 */
+ unsigned char mac[8][6]; /* 0x0042 - 0x0071 */
+ unsigned char res_2[126]; /* 0x0072 - 0x00ef */
+ unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */
+} EEPROM_data;
+
+static EEPROM_data mac_data;
+
+int mac_show(void)
+{
+ int i;
+ unsigned char ethaddr[8][18];
+
+ printf("ID %c%c%c%c\n",
+ mac_data.id[0],
+ mac_data.id[1],
+ mac_data.id[2],
+ mac_data.id[3]);
+ printf("Errata %c%c%c%c%c\n",
+ mac_data.errata[0],
+ mac_data.errata[1],
+ mac_data.errata[2],
+ mac_data.errata[3],
+ mac_data.errata[4]);
+ printf("Date %c%c%c%c%c%c%c\n",
+ mac_data.date[0],
+ mac_data.date[1],
+ mac_data.date[2],
+ mac_data.date[3],
+ mac_data.date[4],
+ mac_data.date[5],
+ mac_data.date[6]);
+ for (i = 0; i < 8; i++) {
+ sprintf(ethaddr[i],
+ "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac_data.mac[i][0],
+ mac_data.mac[i][1],
+ mac_data.mac[i][2],
+ mac_data.mac[i][3],
+ mac_data.mac[i][4],
+ mac_data.mac[i][5]);
+ printf("MAC %d %s\n", i, ethaddr[i]);
+ }
+
+ setenv("ethaddr", ethaddr[0]);
+ setenv("eth1addr", ethaddr[1]);
+ setenv("eth2addr", ethaddr[2]);
+ setenv("eth3addr", ethaddr[3]);
+
+ return 0;
+}
+
+int mac_read(void)
+{
+ int ret, length;
+ unsigned int crc = 0;
+ unsigned char dev = ID_EEPROM_ADDR, *data;
+
+ length = sizeof(EEPROM_data);
+ ret = i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length);
+ if (ret) {
+ printf("Read failed.\n");
+ return -1;
+ }
+
+ data = (unsigned char *)(&mac_data);
+ printf("Check CRC on reading ...");
+ crc = crc32(crc, data, length - 4);
+ if (crc != mac_data.crc) {
+ printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n",
+ mac_data.crc, crc);
+ return -1;
+ } else {
+ printf("CRC OK\n");
+ mac_show();
+ }
+ return 0;
+}
+
+int mac_prog(void)
+{
+ int ret, i, length;
+ unsigned int crc = 0;
+ unsigned char dev = ID_EEPROM_ADDR, *ptr;
+ unsigned char *eeprom_data = (unsigned char *)(&mac_data);
+
+ for (i = 0; i < sizeof(mac_data.res_1); i++)
+ mac_data.res_1[i] = 0;
+ for (i = 0; i < sizeof(mac_data.res_2); i++)
+ mac_data.res_2[i] = 0;
+ length = sizeof(EEPROM_data);
+ crc = crc32(crc, eeprom_data, length - 4);
+ mac_data.crc = crc;
+ for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) {
+ ret =
+ i2c_write(dev, i, 1, ptr,
+ (length - i) < 8 ? (length - i) : 8);
+ udelay(5000); /* 5ms write cycle timing */
+ if (ret)
+ break;
+ }
+ if (ret) {
+ printf("Programming failed.\n");
+ return -1;
+ } else {
+ printf("Programming %d bytes. Reading back ...\n", length);
+ mac_read();
+ }
+ return 0;
+}
+
+int do_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ int i;
+ char cmd = 's';
+ unsigned long long mac_val;
+
+ if (i2c_probe(ID_EEPROM_ADDR) != 0)
+ return -1;
+
+ if (argc > 1) {
+ cmd = argv[1][0];
+ switch (cmd) {
+ case 'r': /* display */
+ mac_read();
+ break;
+ case 's': /* save */
+ mac_prog();
+ break;
+ case 'i': /* id */
+ for (i = 0; i < 4; i++) {
+ mac_data.id[i] = argv[2][i];
+ }
+ break;
+ case 'n': /* serial number */
+ for (i = 0; i < 12; i++) {
+ mac_data.sn[i] = argv[2][i];
+ }
+ break;
+ case 'e': /* errata */
+ for (i = 0; i < 5; i++) {
+ mac_data.errata[i] = argv[2][i];
+ }
+ break;
+ case 'd': /* date */
+ for (i = 0; i < 7; i++) {
+ mac_data.date[i] = argv[2][i];
+ }
+ break;
+ case 'p': /* number of ports */
+ mac_data.tab_size =
+ (unsigned char)simple_strtoul(argv[2], NULL, 16);
+ break;
+ case '0': /* mac 0 */
+ case '1': /* mac 1 */
+ case '2': /* mac 2 */
+ case '3': /* mac 3 */
+ case '4': /* mac 4 */
+ case '5': /* mac 5 */
+ case '6': /* mac 6 */
+ case '7': /* mac 7 */
+ mac_val = simple_strtoull(argv[2], NULL, 16);
+ for (i = 0; i < 6; i++) {
+ mac_data.mac[cmd - '0'][i] =
+ *((unsigned char *)
+ (((unsigned int)(&mac_val)) + i + 2));
+ }
+ break;
+ case 'h': /* help */
+ default:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ break;
+ }
+ } else {
+ mac_show();
+ }
+ return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+ int length, i;
+ unsigned char dev = ID_EEPROM_ADDR;
+ unsigned char *data;
+ unsigned char ethaddr[4][18];
+ unsigned char enetvar[32];
+ unsigned int crc = 0;
+
+ length = sizeof(EEPROM_data);
+ if (i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length)) {
+ printf("Read failed.\n");
+ return -1;
+ }
+
+ data = (unsigned char *)(&mac_data);
+ crc = crc32(crc, data, length - 4);
+ if (crc != mac_data.crc) {
+ return -1;
+ } else {
+ for (i = 0; i < 4; i++) {
+ if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) {
+ sprintf(ethaddr[i],
+ "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac_data.mac[i][0],
+ mac_data.mac[i][1],
+ mac_data.mac[i][2],
+ mac_data.mac[i][3],
+ mac_data.mac[i][4],
+ mac_data.mac[i][5]);
+ sprintf(enetvar,
+ i ? "eth%daddr" : "ethaddr",
+ i);
+ setenv(enetvar, ethaddr[i]);
+ }
+ }
+ }
+ return 0;
+}
+#endif /* CFG_ID_EEPROM */
diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds
new file mode 100644
index 0000000000..b34de8e0ac
--- /dev/null
+++ b/board/mpc8641hpcn/u-boot.lds
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2004, Freescale, Inc.
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Jeff Brown
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFF00100 :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFF70000 :
+ {
+ cpu/mpc86xx/start.o (.bootpg)
+ board/mpc8641hpcn/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + 1024;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc86xx/start.o (.text)
+ board/mpc8641hpcn/init.o (.text)
+ cpu/mpc86xx/traps.o (.text)
+ cpu/mpc86xx/interrupts.o (.text)
+ cpu/mpc86xx/cpu_init.o (.text)
+ cpu/mpc86xx/cpu.o (.text)
+ cpu/mpc86xx/speed.o (.text)
+ cpu/mpc86xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
generated by cgit (git 2.34.1) at 2024-12-26 07:35:31 +0000