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-rw-r--r--board/netstar/Makefile55
-rw-r--r--board/netstar/crcek.S80
-rwxr-xr-xboard/netstar/crcitbin11370 -> 0 bytes
-rw-r--r--board/netstar/crcit.c2
-rw-r--r--board/netstar/netstar.c5
-rw-r--r--board/netstar/setup.S27
6 files changed, 118 insertions, 51 deletions
diff --git a/board/netstar/Makefile b/board/netstar/Makefile
index 3a205017f2..b7c092d24f 100644
--- a/board/netstar/Makefile
+++ b/board/netstar/Makefile
@@ -1,3 +1,6 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2005
# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
@@ -23,63 +26,71 @@
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := netstar.o flash.o nand.o
+COBJS := netstar.o flash.o nand.o
SOBJS := setup.o crcek.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c \
+ eeprom_start.S
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
LOAD_ADDR = 0x10400000
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
+lnk = $(if $(obj),$(obj),.)
HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
-all: $(LIB) eeprom.srec eeprom.bin crcek.srec crcek.bin crcit
+all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \
+ $(obj)crcek.srec $(obj)crcek.bin $(obj)crcit
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
-eeprom.srec: eeprom.o eeprom_start.o
- $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
- -o $(<:.o=) -e $(<:.o=) $^ \
- -L../../examples -lstubs \
- -L../../lib_generic -lgeneric \
+$(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o
+ cd $(lnk) && $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
+ -o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \
+ -L$(obj)../../examples -lstubs \
+ -L$(obj)../../lib_generic -lgeneric \
-L$(gcclibdir) -lgcc
$(OBJCOPY) -O srec $(<:.o=) $@
-eeprom.bin: eeprom.srec
+$(obj)eeprom.bin: $(obj)eeprom.srec
$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
-crcek.srec: crcek.o
+$(obj)crcek.srec: $(obj)crcek.o
$(LD) -g -Ttext 0x00000000 \
- -o $(<:.o=) -e $(<:.o=) $^
+ -o $(<:.o=) -e crcek $^
$(OBJCOPY) -O srec $(<:.o=) $@
-crcek.bin: crcek.srec
+$(obj)crcek.bin: $(obj)crcek.srec
$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
-crcit: crcit.o crc32.o
+$(obj)crcit: $(obj)crcit.o $(obj)crc32.o
$(HOSTCC) $(HOST_CFLAGS) -o $@ $^
-crcit.o: crcit.c
- $(HOSTCC) $(HOST_CFLAGS) -c $<
+$(obj)crcit.o: crcit.c
+ $(HOSTCC) $(HOST_CFLAGS) -o $@ -c $<
-crc32.o: $(TOPDIR)/tools/crc32.c
- $(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -c $<
+$(obj)crc32.o: $(OBJTREE)/tools/crc32.c
+ $(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -o $@ -c $<
clean:
- rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin \
- crcek crcek.srec crcek.bin
+ rm -f $(SOBJS) $(OBJS) $(obj)eeprom $(obj)eeprom.srec \
+ $(obj)eeprom.bin $(obj)crcek $(obj)crcek.srec \
+ $(obj)crcek.bin
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S
index 6ca4d11df8..a74abf9a09 100644
--- a/board/netstar/crcek.S
+++ b/board/netstar/crcek.S
@@ -13,6 +13,7 @@
* u32 - crc32
*/
+#include <config.h>
#include "crcek.h"
/**
@@ -39,7 +40,7 @@
.macro crcuj, offset, size
mov r0, #0
ldr r1, \offset
- ldr r2, [r1]
+ ldr r2, [r1], #4
cmp r2, r0 @ no data, no problem
beq 2f
tst r2, #3 @ unaligned size
@@ -47,7 +48,6 @@
ldr r3, \size
cmp r2, r3 @ bogus size
bhi 2f
- add r1, r1, #4
do_crc32
ldr r1, [r1]
2:
@@ -55,16 +55,71 @@
.endm
.macro wait, reg
- mov \reg, #0x1000
+ mov \reg, #0x100000
3:
subs \reg, \reg, #0x1
bne 3b
-
.endm
+
.text
.globl crcek
crcek:
- b crc2_bad
+ /* Enable I-cache */
+ mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
+ mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
+ mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
+ orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
+ mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
+ mov r1, #0x00
+ mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
+ nop
+ nop
+ nop
+ nop
+
+ /* Setup clocking mode */
+ ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
+ ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
+ bic r1, r1, #(7 << 11) @ clear clock select
+ orr r1, r1, #(2 << 11) @ set synchronous scalable
+ mov r2, #0
+loop:
+ cmp r2, #1 @ this loop will wait for at least 100 cycles
+ streqh r1, [r0, #0x18] @ before issuing next request from MPU
+ add r2, r2, #1 @ on the 1st run code is loaded into I-cache
+ cmp r2, #16 @ and second run will set clocking mode
+ bne loop
+ nop
+
+ /* Setup clock dividers */
+ ldr r1, CKCTL_VAL
+ orr r1, r1, #0x2000 @ enable DSP clock
+ strh r1, [r0] @ setup clock divisors
+
+ /* Setup DPLL to generate requested freq */
+ ldr r0, DPLL1_BASE @ base of DPLL1 register
+ mov r1, #0x0010 @ set PLL_ENABLE
+ orr r1, r1, #0x2000 @ set IOB to new locking
+ orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
+ orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
+ strh r1, [r0] @ write
+
+locking:
+ ldrh r1, [r0] @ get DPLL value
+ tst r1, #0x01
+ beq locking @ while LOCK not set
+
+ /* Enable clock */
+ ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
+ mov r1, #(1 << 10) @ disable idle mode do not check
+ @ nWAKEUP pin, other remain active
+ strh r1, [r0, #0x04]
+ ldr r1, EN_CLK_VAL
+ strh r1, [r0, #0x08]
+ mov r1, #0x003f @ FLASH.RP not enabled in idle and
+ strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
+
+
mov r6, #0
crcuj _LOADER1_OFFSET, _LOADER_SIZE
bne crc1_bad
@@ -76,9 +131,8 @@ crc1_bad:
crc2_bad:
ldr r3, _LOADER1_OFFSET
ldr r4, _LOADER2_OFFSET
- b boot_2nd
- tst r6, #3
- beq one_is_bad @ one of them (or both) has bad crc
+ teq r6, #3
+ bne one_is_bad @ one of them (or both) has bad crc
ldr r1, [r3, #4]
ldr r2, [r4, #4]
cmp r1, r2 @ boot 2nd loader if versions differ
@@ -90,6 +144,7 @@ one_is_bad:
tst r6, #2
bne boot_2nd
@ We are doomed, so let user know.
+hell:
ldr r0, GPIO_BASE @ configure GPIO pins
ldr r1, GPIO_DIRECTION
strh r1, [r0, #0x08]
@@ -171,6 +226,15 @@ CRC32_TABLE:
GPIO_BASE:
.word 0xfffce000
+MPU_CLKM_BASE:
+ .word 0xfffece00
+DPLL1_BASE:
+ .word 0xfffecf00
+
+CKCTL_VAL:
+ .word OMAP5910_ARM_CKCTL
+EN_CLK_VAL:
+ .word OMAP5910_ARM_EN_CLK
GPIO_DIRECTION:
.word 0x0000ffe7
diff --git a/board/netstar/crcit b/board/netstar/crcit
deleted file mode 100755
index 98ae42e03b..0000000000
--- a/board/netstar/crcit
+++ /dev/null
Binary files differ
diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c
index f6d3066c15..ce98e20267 100644
--- a/board/netstar/crcit.c
+++ b/board/netstar/crcit.c
@@ -77,7 +77,7 @@ int main(int argc, char **argv)
} else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) {
char *endptr, *nptr = argv[2];
unsigned ver = strtoul(nptr, &endptr, 0);
- if (nptr != '\0' && endptr == '\0')
+ if (*nptr != '\0' && *endptr == '\0')
return doit(argv[3], ver);
}
fprintf(stderr, "Usage: crcit [-v version] <image>\n");
diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c
index 4b7eba125e..d6b620c8ce 100644
--- a/board/netstar/netstar.c
+++ b/board/netstar/netstar.c
@@ -27,7 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* arch number of NetStar board */
- /* TODO: use define from asm/mach-types.h */
gd->bd->bi_arch_number = 692;
/* adress of boot parameters */
@@ -51,15 +50,11 @@ int dram_init(void)
return 0;
}
-extern void partition_flash(void);
-
int misc_init_r(void)
{
return 0;
}
-extern void nand_init(void);
-
int board_late_init(void)
{
return 0;
diff --git a/board/netstar/setup.S b/board/netstar/setup.S
index f67786d182..5dacc9cc45 100644
--- a/board/netstar/setup.S
+++ b/board/netstar/setup.S
@@ -145,25 +145,23 @@ lowlevel_init:
nop
/* Setup clocking mode */
- ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit
- ldrh r1, [r0, #0x18] @ get reset status
+ ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
+ ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
bic r1, r1, #(7 << 11) @ clear clock select
orr r1, r1, #(2 << 11) @ set synchronous scalable
- mov r2, #0 @ set wait counter to 100 clock cycles
-
-icache_loop:
- cmp r2, #0x01
- streqh r1, [r0, #0x18]
- add r2, r2, #0x01
- cmp r2, #0x10
- bne icache_loop
+ mov r2, #0
+loop:
+ cmp r2, #1 @ this loop will wait for at least 100 cycles
+ streqh r1, [r0, #0x18] @ before issuing next request from MPU
+ add r2, r2, #1 @ on the 1st run code is loaded into I-cache
+ cmp r2, #16 @ and second run will set clocking mode
+ bne loop
nop
- /* Setup clock divisors */
- ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
+ /* Setup clock dividers */
ldr r1, _OMAP5910_ARM_CKCTL
orr r1, r1, #0x2000 @ enable DSP clock
- strh r1, [r0, #0x00] @ setup clock divisors
+ strh r1, [r0] @ setup clock divisors
/* Setup DPLL to generate requested freq */
ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
@@ -186,8 +184,7 @@ locking:
ldr r1, _OMAP5910_ARM_EN_CLK
strh r1, [r0, #0x08]
mov r1, #0x003f @ FLASH.RP not enabled in idle and
- @ max delayed ( 32 x CLKIN )
- strh r1, [r0, #0x0c]
+ strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
/* Configure 5910 pins functions to match our board. */
ldr r0, MUX_CONFIG_BASE
generated by cgit (git 2.34.1) at 2025-02-23 07:14:13 +0000