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-rw-r--r--board/renesas/ap325rxa/Kconfig12
-rw-r--r--board/renesas/ap325rxa/MAINTAINERS7
-rw-r--r--board/renesas/ap325rxa/Makefile10
-rw-r--r--board/renesas/ap325rxa/ap325rxa.c148
-rw-r--r--board/renesas/ap325rxa/cpld-ap325rxa.c204
-rw-r--r--board/renesas/ap325rxa/lowlevel_init.S170
-rw-r--r--board/renesas/r0p7734/Kconfig12
-rw-r--r--board/renesas/r0p7734/MAINTAINERS7
-rw-r--r--board/renesas/r0p7734/Makefile7
-rw-r--r--board/renesas/r0p7734/lowlevel_init.S591
-rw-r--r--board/renesas/r0p7734/r0p7734.c58
11 files changed, 0 insertions, 1226 deletions
diff --git a/board/renesas/ap325rxa/Kconfig b/board/renesas/ap325rxa/Kconfig
deleted file mode 100644
index c8f2de2959..0000000000
--- a/board/renesas/ap325rxa/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_AP325RXA
-
-config SYS_BOARD
- default "ap325rxa"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "ap325rxa"
-
-endif
diff --git a/board/renesas/ap325rxa/MAINTAINERS b/board/renesas/ap325rxa/MAINTAINERS
deleted file mode 100644
index bdc49c5ec9..0000000000
--- a/board/renesas/ap325rxa/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-AP325RXA BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/renesas/ap325rxa/
-F: include/configs/ap325rxa.h
-F: configs/ap325rxa_defconfig
diff --git a/board/renesas/ap325rxa/Makefile b/board/renesas/ap325rxa/Makefile
deleted file mode 100644
index 6551b940d3..0000000000
--- a/board/renesas/ap325rxa/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-######################################################################### Copyright (C) 2008 Renesas Solutions Corp.
-# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-#
-# board/ap325rxa/Makefile
-#
-#
-
-obj-y := ap325rxa.o cpld-ap325rxa.o
-extra-y += lowlevel_init.o
diff --git a/board/renesas/ap325rxa/ap325rxa.c b/board/renesas/ap325rxa/ap325rxa.c
deleted file mode 100644
index 700a48687d..0000000000
--- a/board/renesas/ap325rxa/ap325rxa.c
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-/* PRI control register */
-#define PRPRICR5 0xFF800048 /* LMB */
-#define PRPRICR5_D 0x2a
-
-/* FPGA control */
-#define FPGA_NAND_CTL 0xB410020C
-#define FPGA_NAND_RST 0x0008
-#define FPGA_NAND_INIT 0x0000
-#define FPGA_NAND_RST_WAIT 10000
-
-/* I/O port data */
-#define PACR_D 0x0000
-#define PBCR_D 0x0000
-#define PCCR_D 0x1000
-#define PDCR_D 0x0000
-#define PECR_D 0x0410
-#define PFCR_D 0xffff
-#define PGCR_D 0x0000
-#define PHCR_D 0x5011
-#define PJCR_D 0x4400
-#define PKCR_D 0x7c00
-#define PLCR_D 0x0000
-#define PMCR_D 0x0000
-#define PNCR_D 0x0000
-#define PQCR_D 0x0000
-#define PRCR_D 0x0000
-#define PSCR_D 0x0000
-#define PTCR_D 0x0010
-#define PUCR_D 0x0fff
-#define PVCR_D 0xffff
-#define PWCR_D 0x0000
-#define PXCR_D 0x7500
-#define PYCR_D 0x0000
-#define PZCR_D 0x5540
-
-/* Pin Function Controler data */
-#define PSELA_D 0x1410
-#define PSELB_D 0x0140
-#define PSELC_D 0x0000
-#define PSELD_D 0x0400
-
-/* I/O Buffer Hi-Z data */
-#define HIZCRA_D 0x0000
-#define HIZCRB_D 0x1000
-#define HIZCRC_D 0x0000
-#define HIZCRD_D 0x0000
-
-/* Module select reg data */
-#define MSELCRA_D 0x0014
-#define MSELCRB_D 0x0018
-
-/* Module Stop reg Data */
-#define MSTPCR2_D 0xFFD9F280
-
-/* CPLD loader */
-extern void init_cpld(void);
-
-int checkboard(void)
-{
- puts("BOARD: AP325RXA\n");
- return 0;
-}
-
-int board_init(void)
-{
- /* Pin Function Controler Init */
- outw(PSELA_D, PSELA);
- outw(PSELB_D, PSELB);
- outw(PSELC_D, PSELC);
- outw(PSELD_D, PSELD);
-
- /* I/O Buffer Hi-Z Init */
- outw(HIZCRA_D, HIZCRA);
- outw(HIZCRB_D, HIZCRB);
- outw(HIZCRC_D, HIZCRC);
- outw(HIZCRD_D, HIZCRD);
-
- /* Module select reg Init */
- outw(MSELCRA_D, MSELCRA);
- outw(MSELCRB_D, MSELCRB);
-
- /* Module Stop reg Init */
- outl(MSTPCR2_D, MSTPCR2);
-
- /* I/O ports */
- outw(PACR_D, PACR);
- outw(PBCR_D, PBCR);
- outw(PCCR_D, PCCR);
- outw(PDCR_D, PDCR);
- outw(PECR_D, PECR);
- outw(PFCR_D, PFCR);
- outw(PGCR_D, PGCR);
- outw(PHCR_D, PHCR);
- outw(PJCR_D, PJCR);
- outw(PKCR_D, PKCR);
- outw(PLCR_D, PLCR);
- outw(PMCR_D, PMCR);
- outw(PNCR_D, PNCR);
- outw(PQCR_D, PQCR);
- outw(PRCR_D, PRCR);
- outw(PSCR_D, PSCR);
- outw(PTCR_D, PTCR);
- outw(PUCR_D, PUCR);
- outw(PVCR_D, PVCR);
- outw(PWCR_D, PWCR);
- outw(PXCR_D, PXCR);
- outw(PYCR_D, PYCR);
- outw(PZCR_D, PZCR);
-
- /* PRI control register Init */
- outl(PRPRICR5_D, PRPRICR5);
-
- /* cpld init */
- init_cpld();
-
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-}
-
-void ide_set_reset(int idereset)
-{
- outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */
- udelay(FPGA_NAND_RST_WAIT);
- outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
diff --git a/board/renesas/ap325rxa/cpld-ap325rxa.c b/board/renesas/ap325rxa/cpld-ap325rxa.c
deleted file mode 100644
index 5d9dc9387e..0000000000
--- a/board/renesas/ap325rxa/cpld-ap325rxa.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/***************************************************************
- * Project:
- * CPLD SlaveSerial Configuration via embedded microprocessor.
- *
- * Copyright info:
- *
- * This is free software; you can redistribute it and/or modify
- * it as you like.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Description:
- *
- * This is the main source file that will allow a microprocessor
- * to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II,
- * and Spartan-II devices via the SlaveSerial Configuration Mode.
- * This code is discussed in Xilinx Application Note, XAPP502.
- *
- * History:
- * 3-October-2001 MN/MP - Created
- * 20-August-2008 Renesas Solutions - Modified to SH7723
- ****************************************************************/
-
-#include <common.h>
-
-/* Serial */
-#define SCIF_BASE 0xffe00000 /* SCIF0 */
-#define SCSMR (vu_short *)(SCIF_BASE + 0x00)
-#define SCBRR (vu_char *)(SCIF_BASE + 0x04)
-#define SCSCR (vu_short *)(SCIF_BASE + 0x08)
-#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C)
-#define SC_SR (vu_short *)(SCIF_BASE + 0x10)
-#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
-#define RFCR (vu_long *)0xFE400020
-
-#define SCSCR_INIT 0x0038
-#define SCSCR_CLR 0x0000
-#define SCFCR_INIT 0x0006
-#define SCSMR_INIT 0x0080
-#define RFCR_CLR 0xA400
-#define SCI_TD_E 0x0020
-#define SCI_TDRE_CLEAR 0x00df
-
-#define BPS_SETTING_VALUE 1 /* 12.5MHz */
-#define WAIT_RFCR_COUNTER 500
-
-/* CPLD data size */
-#define CPLD_DATA_SIZE 169216
-
-/* out */
-#define CPLD_PFC_ADR ((vu_short *)0xA4050112)
-
-#define CPLD_PROG_ADR ((vu_char *)0xA4050132)
-#define CPLD_PROG_DAT 0x80
-
-/* in */
-#define CPLD_INIT_ADR ((vu_char *)0xA4050132)
-#define CPLD_INIT_DAT 0x40
-#define CPLD_DONE_ADR ((vu_char *)0xA4050132)
-#define CPLD_DONE_DAT 0x20
-
-/* data */
-#define CPLD_NOMAL_START 0xA0A80000
-#define CPLD_SAFE_START 0xA0AC0000
-#define MODE_SW (vu_char *)0xA405012A
-
-static void init_cpld_loader(void)
-{
-
- *SCSCR = SCSCR_CLR;
- *SCFCR = SCFCR_INIT;
- *SCSMR = SCSMR_INIT;
-
- *SCBRR = BPS_SETTING_VALUE;
-
- *RFCR = RFCR_CLR; /* Refresh counter clear */
-
- while (*RFCR < WAIT_RFCR_COUNTER)
- ;
-
- *SCFCR = 0x0; /* RTRG=00, TTRG=00 */
- /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */
- *SCSCR = SCSCR_INIT;
-}
-
-static int check_write_ready(void)
-{
- u16 status = *SC_SR;
- return status & SCI_TD_E;
-}
-
-static void write_cpld_data(char ch)
-{
- while (!check_write_ready())
- ;
-
- *SC_TDR = ch;
- *SC_SR;
- *SC_SR = SCI_TDRE_CLEAR;
-}
-
-static int delay(void)
-{
- int i;
- int c = 0;
- for (i = 0; i < 200; i++) {
- c = *(volatile int *)0xa0000000;
- }
- return c;
-}
-
-/***********************************************************************
- *
- * Function: slave_serial
- *
- * Description: Initiates SlaveSerial Configuration.
- * Calls ShiftDataOut() to output serial data
- *
- ***********************************************************************/
-static void slave_serial(void)
-{
- int i;
- unsigned char *flash;
-
- *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
- delay();
-
- /*
- * Toggle Program Pin by Toggling Program_OE bit
- * This is accomplished by writing to the Program Register in the CPLD
- *
- * NOTE: The Program_OE bit should be driven high to bring the Virtex
- * Program Pin low. Likewise, it should be driven low
- * to bring the Virtex Program Pin to High-Z
- */
-
- *CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */
- delay();
-
- /*
- * Bring Program High-Z
- * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z
- */
-
- /* Program_OE bit Low brings the Virtex Program Pin to High Z: */
- *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
-
- while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0)
- delay();
-
- /* Begin Slave-Serial Configuration */
- flash = (unsigned char *)CPLD_NOMAL_START;
-
- for (i = 0; i < CPLD_DATA_SIZE; i++)
- write_cpld_data(*flash++);
-}
-
-/***********************************************************************
- *
- * Function: check_done_bit
- *
- * Description: This function takes monitors the CPLD Input Register
- * by checking the status of the DONE bit in that Register.
- * By doing so, it monitors the Xilinx Virtex device's DONE
- * Pin to see if configuration bitstream has been properly
- * loaded
- *
- ***********************************************************************/
-static void check_done_bit(void)
-{
- while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT))
- ;
-}
-
-/***********************************************************************
- *
- * Function: init_cpld
- *
- * Description: Begins Slave Serial configuration of Xilinx FPGA
- *
- ***********************************************************************/
-void init_cpld(void)
-{
- /* Init serial device */
- init_cpld_loader();
-
- if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */
- return;
-
- *((vu_short *)HIZCRB) = 0x0000;
- *CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */
-
- /* write CPLD data from NOR flash to device */
- slave_serial();
-
- /*
- * Monitor the DONE bit in the CPLD Input Register to see if
- * configuration successful
- */
-
- check_done_bit();
-}
diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S
deleted file mode 100644
index 1a24581c32..0000000000
--- a/board/renesas/ap325rxa/lowlevel_init.S
+++ /dev/null
@@ -1,170 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
- *
- * board/ap325rxa/lowlevel_init.S
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-/*
- * Board specific low level init code, called _very_ early in the
- * startup sequence. Relocation to SDRAM has not happened yet, no
- * stack is available, bss section has not been initialised, etc.
- *
- * (Note: As no stack is available, no subroutines can be called...).
- */
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- write16 DRVCRA_A, DRVCRA_D
-
- write16 DRVCRB_A, DRVCRB_D
-
- write16 RWTCSR_A, RWTCSR_D1
-
- write16 RWTCNT_A, RWTCNT_D
-
- write16 RWTCSR_A, RWTCSR_D2
-
- write32 FRQCR_A, FRQCR_D
-
- write32 CMNCR_A, CMNCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS4BCR_A, CS4BCR_D
-
- write32 CS5ABCR_A, CS5ABCR_D
-
- write32 CS5BBCR_A, CS5BBCR_D
-
- write32 CS6ABCR_A, CS6ABCR_D
-
- write32 CS6BBCR_A, CS6BBCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
- write32 CS4WCR_A, CS4WCR_D
-
- write32 CS5AWCR_A, CS5AWCR_D
-
- write32 CS5BWCR_A, CS5BWCR_D
-
- write32 CS6AWCR_A, CS6AWCR_D
-
- write32 CS6BWCR_A, CS6BWCR_D
-
- write32 SBSC_SDCR_A, SBSC_SDCR_D1
-
- write32 SBSC_SDWCR_A, SBSC_SDWCR_D
-
- write32 SBSC_SDPCR_A, SBSC_SDPCR_D
-
- write32 SBSC_RTCSR_A, SBSC_RTCSR_D
-
- write32 SBSC_RTCNT_A, SBSC_RTCNT_D
-
- write32 SBSC_RTCOR_A, SBSC_RTCOR_D
-
- write8 SBSC_SDMR3_A1, SBSC_SDMR3_D
-
- write8 SBSC_SDMR3_A2, SBSC_SDMR3_D
-
- mov.l SLEEP_CNT, r1
-2: tst r1, r1
- nop
- bf/s 2b
- dt r1
-
- write8 SBSC_SDMR3_A3, SBSC_SDMR3_D
-
- write32 SBSC_SDCR_A, SBSC_SDCR_D2
-
- write32 CCR_A, CCR_D
-
- ! BL bit off (init = ON) (?!?)
-
- stc sr, r0 ! BL bit off(init=ON)
- mov.l SR_MASK_D, r1
- and r1, r0
- ldc r0, sr
-
- rts
- mov #0, r0
-
- .align 2
-
-DRVCRA_A: .long DRVCRA
-DRVCRB_A: .long DRVCRB
-DRVCRA_D: .word 0x4555
-DRVCRB_D: .word 0x0005
-
-RWTCSR_A: .long RWTCSR
-RWTCNT_A: .long RWTCNT
-FRQCR_A: .long FRQCR
-RWTCSR_D1: .word 0xa507
-RWTCSR_D2: .word 0xa504
-RWTCNT_D: .word 0x5a00
-.align 2
-FRQCR_D: .long 0x0b04474a
-
-SBSC_SDCR_A: .long SBSC_SDCR
-SBSC_SDWCR_A: .long SBSC_SDWCR
-SBSC_SDPCR_A: .long SBSC_SDPCR
-SBSC_RTCSR_A: .long SBSC_RTCSR
-SBSC_RTCNT_A: .long SBSC_RTCNT
-SBSC_RTCOR_A: .long SBSC_RTCOR
-SBSC_SDMR3_A1: .long 0xfe510000
-SBSC_SDMR3_A2: .long 0xfe500242
-SBSC_SDMR3_A3: .long 0xfe5c0042
-
-SBSC_SDCR_D1: .long 0x92810112
-SBSC_SDCR_D2: .long 0x92810912
-SBSC_SDWCR_D: .long 0x05162482
-SBSC_SDPCR_D: .long 0x00300087
-SBSC_RTCSR_D: .long 0xa55a0212
-SBSC_RTCNT_D: .long 0xa55a0000
-SBSC_RTCOR_D: .long 0xa55a0040
-SBSC_SDMR3_D: .long 0x00
-
-CMNCR_A: .long CMNCR
-CS0BCR_A: .long CS0BCR
-CS4BCR_A: .long CS4BCR
-CS5ABCR_A: .long CS5ABCR
-CS5BBCR_A: .long CS5BBCR
-CS6ABCR_A: .long CS6ABCR
-CS6BBCR_A: .long CS6BBCR
-CS0WCR_A: .long CS0WCR
-CS4WCR_A: .long CS4WCR
-CS5AWCR_A: .long CS5AWCR
-CS5BWCR_A: .long CS5BWCR
-CS6AWCR_A: .long CS6AWCR
-CS6BWCR_A: .long CS6BWCR
-
-CMNCR_D: .long 0x00000013
-CS0BCR_D: .long 0x24920400
-CS4BCR_D: .long 0x24920400
-CS5ABCR_D: .long 0x24920400
-CS5BBCR_D: .long 0x7fff0600
-CS6ABCR_D: .long 0x24920400
-CS6BBCR_D: .long 0x24920600
-CS0WCR_D: .long 0x00000480
-CS4WCR_D: .long 0x00000480
-CS5AWCR_D: .long 0x00000380
-CS5BWCR_D: .long 0x00000080
-CS6AWCR_D: .long 0x00000300
-CS6BWCR_D: .long 0x00000540
-
-CCR_A: .long 0xff00001c
-CCR_D: .long 0x0000090d
-
-SLEEP_CNT: .long 0x00000800
-SR_MASK_D: .long 0xEFFFFF0F
diff --git a/board/renesas/r0p7734/Kconfig b/board/renesas/r0p7734/Kconfig
deleted file mode 100644
index 7f24f41b8f..0000000000
--- a/board/renesas/r0p7734/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_R0P7734
-
-config SYS_BOARD
- default "r0p7734"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "r0p7734"
-
-endif
diff --git a/board/renesas/r0p7734/MAINTAINERS b/board/renesas/r0p7734/MAINTAINERS
deleted file mode 100644
index c169ad7ecc..0000000000
--- a/board/renesas/r0p7734/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-R0P7734 BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/renesas/r0p7734/
-F: include/configs/r0p7734.h
-F: configs/r0p7734_defconfig
diff --git a/board/renesas/r0p7734/Makefile b/board/renesas/r0p7734/Makefile
deleted file mode 100644
index 8d98016cbe..0000000000
--- a/board/renesas/r0p7734/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-#
-
-obj-y := r0p7734.o
-extra-y += lowlevel_init.o
diff --git a/board/renesas/r0p7734/lowlevel_init.S b/board/renesas/r0p7734/lowlevel_init.S
deleted file mode 100644
index feb92f0cf4..0000000000
--- a/board/renesas/r0p7734/lowlevel_init.S
+++ /dev/null
@@ -1,591 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * Copyright (C) 2011 Renesas Solutions Corp.
- */
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-#include <asm/processor.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
- /* WDT */
- write32 WDTCSR_A, WDTCSR_D
-
- /* MMU */
- write32 MMUCR_A, MMUCR_D
-
- write32 FRQCR2_A, FRQCR2_D
- write32 FRQCR0_A, FRQCR0_D
-
- write32 CS0CTRL_A, CS0CTRL_D
- write32 CS1CTRL_A, CS1CTRL_D
- write32 CS0CTRL2_A, CS0CTRL2_D
-
- write32 CSPWCR0_A, CSPWCR0_D
- write32 CSPWCR1_A, CSPWCR1_D
- write32 CS1GDST_A, CS1GDST_D
-
- # clock mode check
- mov.l MODEMR, r1
- mov.l @r1, r0
- and #6, r0 /* Check 1 and 2 bit.*/
- cmp/eq #2, r0 /* 0x02 is 533Mhz mode */
- bt init_lbsc_533
-
-init_lbsc_400:
-
- write32 CSWCR0_A, CSWCR0_D_400
- write32 CSWCR1_A, CSWCR1_D
-
- bra init_dbsc3_400_pad
- nop
-
- .align 2
-
-MODEMR: .long 0xFFCC0020
-WDTCSR_A: .long 0xFFCC0004
-WDTCSR_D: .long 0xA5000000
-MMUCR_A: .long 0xFF000010
-MMUCR_D: .long 0x00000004
-
-FRQCR2_A: .long 0xFFC80008
-FRQCR2_D: .long 0x00000000
-FRQCR0_A: .long 0xFFC80000
-FRQCR0_D: .long 0xCF000001
-
-CS0CTRL_A: .long 0xFF800200
-CS0CTRL_D: .long 0x00000020
-CS1CTRL_A: .long 0xFF800204
-CS1CTRL_D: .long 0x00000020
-
-CS0CTRL2_A: .long 0xFF800220
-CS0CTRL2_D: .long 0x00004000
-
-CSPWCR0_A: .long 0xFF800280
-CSPWCR0_D: .long 0x00000000
-CSPWCR1_A: .long 0xFF800284
-CSPWCR1_D: .long 0x00000000
-CS1GDST_A: .long 0xFF8002C0
-CS1GDST_D: .long 0x00000011
-
-init_lbsc_533:
-
- write32 CSWCR0_A, CSWCR0_D_533
- write32 CSWCR1_A, CSWCR1_D
-
- bra init_dbsc3_533_pad
- nop
-
- .align 2
-
-CSWCR0_A: .long 0xFF800230
-CSWCR0_D_533: .long 0x01120104
-CSWCR0_D_400: .long 0x02120114
-/* CSWCR0_D_400: .long 0x01160116 */
-CSWCR1_A: .long 0xFF800234
-CSWCR1_D: .long 0x077F077F
-/* CSWCR1_D_400: .long 0x00120012 */
-
-init_dbsc3_400_pad:
-
- write32 DBPDCNT3_A, DBPDCNT3_D
- wait_timer WAIT_200US_400
-
- write32 DBPDCNT0_A, DBPDCNT0_D_400
- write32 DBPDCNT3_A, DBPDCNT3_D0
- write32 DBPDCNT1_A, DBPDCNT1_D
-
- write32 DBPDCNT3_A, DBPDCNT3_D1
- wait_timer WAIT_32MCLK
-
- write32 DBPDCNT3_A, DBPDCNT3_D2
- wait_timer WAIT_100US_400
-
- write32 DBPDCNT3_A, DBPDCNT3_D3
- wait_timer WAIT_16MCLK
-
- write32 DBPDCNT3_A, DBPDCNT3_D4
- wait_timer WAIT_200US_400
-
- write32 DBPDCNT3_A, DBPDCNT3_D5
- wait_timer WAIT_1MCLK
-
- write32 DBPDCNT3_A, DBPDCNT3_D6
- wait_timer WAIT_10KMCLK
-
- bra init_dbsc3_ctrl_400
- nop
-
- .align 2
-
-init_dbsc3_533_pad:
-
- write32 DBPDCNT3_A, DBPDCNT3_D
- wait_timer WAIT_200US_533
-
- write32 DBPDCNT0_A, DBPDCNT0_D_533
- write32 DBPDCNT3_A, DBPDCNT3_D0
- write32 DBPDCNT1_A, DBPDCNT1_D
-
- write32 DBPDCNT3_A, DBPDCNT3_D1
- wait_timer WAIT_32MCLK
-
- write32 DBPDCNT3_A, DBPDCNT3_D2
- wait_timer WAIT_100US_533
-
- write32 DBPDCNT3_A, DBPDCNT3_D3
- wait_timer WAIT_16MCLK
-
- write32 DBPDCNT3_A, DBPDCNT3_D4
- wait_timer WAIT_200US_533
-
- write32 DBPDCNT3_A, DBPDCNT3_D5
- wait_timer WAIT_1MCLK
-
- write32 DBPDCNT3_A, DBPDCNT3_D6
- wait_timer WAIT_10KMCLK
-
- bra init_dbsc3_ctrl_533
- nop
-
- .align 2
-
-WAIT_200US_400: .long 40000
-WAIT_200US_533: .long 53300
-WAIT_100US_400: .long 20000
-WAIT_100US_533: .long 26650
-WAIT_32MCLK: .long 32
-WAIT_16MCLK: .long 16
-WAIT_1MCLK: .long 1
-WAIT_10KMCLK: .long 10000
-
-DBPDCNT0_A: .long 0xFE800200
-DBPDCNT0_D_533: .long 0x00010245
-DBPDCNT0_D_400: .long 0x00010235
-DBPDCNT1_A: .long 0xFE800204
-DBPDCNT1_D: .long 0x00000014
-DBPDCNT3_A: .long 0xFE80020C
-DBPDCNT3_D: .long 0x80000000
-DBPDCNT3_D0: .long 0x800F0000
-DBPDCNT3_D1: .long 0x800F1000
-DBPDCNT3_D2: .long 0x820F1000
-DBPDCNT3_D3: .long 0x860F1000
-DBPDCNT3_D4: .long 0x870F1000
-DBPDCNT3_D5: .long 0x870F3000
-DBPDCNT3_D6: .long 0x870F7000
-
-init_dbsc3_ctrl_400:
-
- write32 DBKIND_A, DBKIND_D
- write32 DBCONF_A, DBCONF_D
-
- write32 DBTR0_A, DBTR0_D_400
- write32 DBTR1_A, DBTR1_D_400
- write32 DBTR2_A, DBTR2_D
- write32 DBTR3_A, DBTR3_D_400
- write32 DBTR4_A, DBTR4_D_400
- write32 DBTR5_A, DBTR5_D_400
- write32 DBTR6_A, DBTR6_D_400
- write32 DBTR7_A, DBTR7_D
- write32 DBTR8_A, DBTR8_D_400
- write32 DBTR9_A, DBTR9_D
- write32 DBTR10_A, DBTR10_D_400
- write32 DBTR11_A, DBTR11_D
- write32 DBTR12_A, DBTR12_D_400
- write32 DBTR13_A, DBTR13_D_400
- write32 DBTR14_A, DBTR14_D
- write32 DBTR15_A, DBTR15_D
- write32 DBTR16_A, DBTR16_D_400
- write32 DBTR17_A, DBTR17_D_400
- write32 DBTR18_A, DBTR18_D_400
-
- write32 DBBL_A, DBBL_D
- write32 DBRNK0_A, DBRNK0_D
-
- write32 DBCMD_A, DBCMD_D0_400
- write32 DBCMD_A, DBCMD_D1
- write32 DBCMD_A, DBCMD_D2
- write32 DBCMD_A, DBCMD_D3
- write32 DBCMD_A, DBCMD_D4
- write32 DBCMD_A, DBCMD_D5_400
- write32 DBCMD_A, DBCMD_D6
- write32 DBCMD_A, DBCMD_D7
- write32 DBCMD_A, DBCMD_D8
- write32 DBCMD_A, DBCMD_D9_400
- write32 DBCMD_A, DBCMD_D10
- write32 DBCMD_A, DBCMD_D11
- write32 DBCMD_A, DBCMD_D12
-
- write32 DBBS0CNT1_A, DBBS0CNT1_D
- write32 DBPDNCNF_A, DBPDNCNF_D
-
- write32 DBRFCNF0_A, DBRFCNF0_D
- write32 DBRFCNF1_A, DBRFCNF1_D_400
- write32 DBRFCNF2_A, DBRFCNF2_D
- write32 DBRFEN_A, DBRFEN_D
- write32 DBACEN_A, DBACEN_D
- write32 DBACEN_A, DBACEN_D
-
- /* Dummy read */
- mov.l DBWAIT_A, r1
- synco
- mov.l @r1, r0
- synco
-
- /* Dummy read */
- mov.l SDRAM_A, r1
- synco
- mov.l @r1, r0
- synco
-
- /* need sleep 186A0 */
-
- bra init_pfc_sh7734
- nop
-
- .align 2
-
-init_dbsc3_ctrl_533:
-
- write32 DBKIND_A, DBKIND_D
- write32 DBCONF_A, DBCONF_D
-
- write32 DBTR0_A, DBTR0_D_533
- write32 DBTR1_A, DBTR1_D_533
- write32 DBTR2_A, DBTR2_D
- write32 DBTR3_A, DBTR3_D_533
- write32 DBTR4_A, DBTR4_D_533
- write32 DBTR5_A, DBTR5_D_533
- write32 DBTR6_A, DBTR6_D_533
- write32 DBTR7_A, DBTR7_D
- write32 DBTR8_A, DBTR8_D_533
- write32 DBTR9_A, DBTR9_D
- write32 DBTR10_A, DBTR10_D_533
- write32 DBTR11_A, DBTR11_D
- write32 DBTR12_A, DBTR12_D_533
- write32 DBTR13_A, DBTR13_D_533
- write32 DBTR14_A, DBTR14_D
- write32 DBTR15_A, DBTR15_D
- write32 DBTR16_A, DBTR16_D_533
- write32 DBTR17_A, DBTR17_D_533
- write32 DBTR18_A, DBTR18_D_533
-
- write32 DBBL_A, DBBL_D
- write32 DBRNK0_A, DBRNK0_D
-
- write32 DBCMD_A, DBCMD_D0_533
- write32 DBCMD_A, DBCMD_D1
- write32 DBCMD_A, DBCMD_D2
- write32 DBCMD_A, DBCMD_D3
- write32 DBCMD_A, DBCMD_D4
- write32 DBCMD_A, DBCMD_D5_533
- write32 DBCMD_A, DBCMD_D6
- write32 DBCMD_A, DBCMD_D7
- write32 DBCMD_A, DBCMD_D8
- write32 DBCMD_A, DBCMD_D9_533
- write32 DBCMD_A, DBCMD_D10
- write32 DBCMD_A, DBCMD_D11
- write32 DBCMD_A, DBCMD_D12
-
- write32 DBBS0CNT1_A, DBBS0CNT1_D
- write32 DBPDNCNF_A, DBPDNCNF_D
-
- write32 DBRFCNF0_A, DBRFCNF0_D
- write32 DBRFCNF1_A, DBRFCNF1_D_533
- write32 DBRFCNF2_A, DBRFCNF2_D
- write32 DBRFEN_A, DBRFEN_D
- write32 DBACEN_A, DBACEN_D
- write32 DBACEN_A, DBACEN_D
-
- /* Dummy read */
- mov.l DBWAIT_A, r1
- synco
- mov.l @r1, r0
- synco
-
- /* Dummy read */
- mov.l SDRAM_A, r1
- synco
- mov.l @r1, r0
- synco
-
- /* need sleep 186A0 */
-
- bra init_pfc_sh7734
- nop
-
- .align 2
-
-DBKIND_A: .long 0xFE800020
-DBKIND_D: .long 0x00000005
-DBCONF_A: .long 0xFE800024
-DBCONF_D: .long 0x0D030A01
-
-DBTR0_A: .long 0xFE800040
-DBTR0_D_533:.long 0x00000004
-DBTR0_D_400:.long 0x00000003
-DBTR1_A: .long 0xFE800044
-DBTR1_D_533:.long 0x00000003
-DBTR1_D_400:.long 0x00000002
-DBTR2_A: .long 0xFE800048
-DBTR2_D: .long 0x00000000
-DBTR3_A: .long 0xFE800050
-DBTR3_D_533:.long 0x00000004
-DBTR3_D_400:.long 0x00000003
-
-DBTR4_A: .long 0xFE800054
-DBTR4_D_533:.long 0x00050004
-DBTR4_D_400:.long 0x00050003
-
-DBTR5_A: .long 0xFE800058
-DBTR5_D_533:.long 0x0000000F
-DBTR5_D_400:.long 0x0000000B
-
-DBTR6_A: .long 0xFE80005C
-DBTR6_D_533:.long 0x0000000B
-DBTR6_D_400:.long 0x00000008
-
-DBTR7_A: .long 0xFE800060
-DBTR7_D: .long 0x00000002 /* common value */
-
-DBTR8_A: .long 0xFE800064
-DBTR8_D_533:.long 0x0000000D
-DBTR8_D_400:.long 0x0000000A
-
-DBTR9_A: .long 0xFE800068
-DBTR9_D: .long 0x00000002 /* common value */
-
-DBTR10_A: .long 0xFE80006C
-DBTR10_D_533:.long 0x00000004
-DBTR10_D_400:.long 0x00000003
-
-DBTR11_A: .long 0xFE800070
-DBTR11_D: .long 0x00000008 /* common value */
-
-DBTR12_A: .long 0xFE800074
-DBTR12_D_533:.long 0x00000009
-DBTR12_D_400:.long 0x00000008
-
-DBTR13_A: .long 0xFE800078
-DBTR13_D_533:.long 0x00000022
-DBTR13_D_400:.long 0x0000001A
-
-DBTR14_A: .long 0xFE80007C
-DBTR14_D: .long 0x00070002 /* common value */
-
-DBTR15_A: .long 0xFE800080
-DBTR15_D: .long 0x00000003 /* common value */
-
-DBTR16_A: .long 0xFE800084
-DBTR16_D_533:.long 0x120A1001
-DBTR16_D_400:.long 0x12091001
-
-DBTR17_A: .long 0xFE800088
-DBTR17_D_533:.long 0x00040000
-DBTR17_D_400:.long 0x00030000
-
-DBTR18_A: .long 0xFE80008C
-DBTR18_D_533:.long 0x02010200
-DBTR18_D_400:.long 0x02000207
-
-DBBL_A: .long 0xFE8000B0
-DBBL_D: .long 0x00000000
-
-DBRNK0_A: .long 0xFE800100
-DBRNK0_D: .long 0x00000001
-
-DBCMD_A: .long 0xFE800018
-DBCMD_D0_533: .long 0x1100006B
-DBCMD_D0_400: .long 0x11000050
-DBCMD_D1: .long 0x0B000000 /* common value */
-DBCMD_D2: .long 0x2A004000 /* common value */
-DBCMD_D3: .long 0x2B006000 /* common value */
-DBCMD_D4: .long 0x29002004 /* common value */
-DBCMD_D5_533: .long 0x28000743
-DBCMD_D5_400: .long 0x28000533
-DBCMD_D6: .long 0x0B000000 /* common value */
-DBCMD_D7: .long 0x0C000000 /* common value */
-DBCMD_D8: .long 0x0C000000 /* common value */
-DBCMD_D9_533: .long 0x28000643
-DBCMD_D9_400: .long 0x28000433
-DBCMD_D10: .long 0x000000C8 /* common value */
-DBCMD_D11: .long 0x29002384 /* common value */
-DBCMD_D12: .long 0x29002004 /* common value */
-
-DBBS0CNT1_A: .long 0xFE800304
-DBBS0CNT1_D: .long 0x00000000
-DBPDNCNF_A: .long 0xFE800180
-DBPDNCNF_D: .long 0x00000200
-
-DBRFCNF0_A: .long 0xFE8000E0
-DBRFCNF0_D: .long 0x000001FF
-DBRFCNF1_A: .long 0xFE8000E4
-DBRFCNF1_D_533: .long 0x00000805
-DBRFCNF1_D_400: .long 0x00000618
-
-DBRFCNF2_A: .long 0xFE8000E8
-DBRFCNF2_D: .long 0x00000000
-
-DBRFEN_A: .long 0xFE800014
-DBRFEN_D: .long 0x00000001
-
-DBACEN_A: .long 0xFE800010
-DBACEN_D: .long 0x00000001
-
-DBWAIT_A: .long 0xFE80001C
-SDRAM_A: .long 0x0C000000
-
-init_pfc_sh7734:
- write32 PFC_PMMR_A, PFC_PMMR_MODESEL1
- write32 PFC_MODESEL1_A, PFC_MODESEL1_D
-
- write32 PFC_PMMR_A, PFC_PMMR_MODESEL2
- write32 PFC_MODESEL2_A, PFC_MODESEL2_D
-
- write32 PFC_PMMR_A, PFC_PMMR_IPSR3
- write32 PFC_IPSR3_A, PFC_IPSR3_D
-
- write32 PFC_PMMR_A, PFC_PMMR_IPSR4
- write32 PFC_IPSR4_A, PFC_IPSR4_D
-
- write32 PFC_PMMR_A, PFC_PMMR_IPSR11
- write32 PFC_IPSR11_A, PFC_IPSR11_D
-
- write32 PFC_PMMR_A, PFC_PMMR_GPSR0
- write32 PFC_GPSR0_A, PFC_GPSR0_D
-
- write32 PFC_PMMR_A, PFC_PMMR_GPSR1
- write32 PFC_GPSR1_A, PFC_GPSR1_D
-
- write32 PFC_PMMR_A, PFC_PMMR_GPSR2
- write32 PFC_GPSR2_A, PFC_GPSR2_D
-
- write32 PFC_PMMR_A, PFC_PMMR_GPSR3
- write32 PFC_GPSR3_A, PFC_GPSR3_D
-
- write32 PFC_PMMR_A, PFC_PMMR_GPSR4
- write32 PFC_GPSR4_A, PFC_GPSR4_D
-
- write32 PFC_PMMR_A, PFC_PMMR_GPSR5
- write32 PFC_GPSR5_A, PFC_GPSR5_D
-
- /* sleep 186A0 */
-
- write32 GPIO2_INOUTSEL1_A, GPIO2_INOUTSEL1_D
- write32 GPIO1_OUTDT1_A, GPIO1_OUTDT1_D
- write32 GPIO2_INOUTSEL2_A, GPIO2_INOUTSEL2_D
- write32 GPIO2_OUTDT2_A, GPIO2_OUTDT2_D
- write32 GPIO4_INOUTSEL4_A, GPIO4_INOUTSEL4_D
- write32 GPIO4_OUTDT4_A, GPIO4_OUTDT4_D
-
- write32 CCR_A, CCR_D
-
- stc sr, r0
- mov.l SR_MASK_D, r1
- and r1, r0
- ldc r0, sr
-
- rts
- nop
-
- .align 2
-
-PFC_PMMR_A: .long 0xFFFC0000
-
-/* MODESEL
- * 28: Select IEBUS Group B
- */
-PFC_MODESEL1_A: .long 0xFFFC004C
-PFC_MODESEL1_D: .long 0x10000000
-PFC_PMMR_MODESEL1: .long 0xEFFFFFFF
-
-/* MODESEL
- * 9: Select SCIF3 Group B
- * 7: Select SCIF2 Group B
- * 4: Select SCIF1 Group B
- */
-PFC_MODESEL2_A: .long 0xFFFC0050
-PFC_MODESEL2_D: .long 0x00000290
-PFC_PMMR_MODESEL2: .long 0xFFFFFD6F
-
-# Enable functios
-# SD1_DAT2_A SD1_DAT1_A, SD1_DAT0_A,
-# EXWAIT0, RDW/RW, SD1_CMD_A, SD1_WP_A,
-# SD1_CD_A, TX3_B, RX3_B, CS1, D15
-PFC_IPSR3_A: .long 0xFFFC0028
-PFC_IPSR3_D: .long 0x09209248
-PFC_PMMR_IPSR3: .long 0xF6DF6DB7
-
-# Enable functios
-# RMII0_MDIO_A , RMII0_MDC_A,
-# RMII0_CRS_DV_A, RMII0_RX_ER_A,
-# RMII0_TXD_EN_A, MII0_RXD1_A
-PFC_IPSR4_A: .long 0xFFFC002C
-PFC_IPSR4_D: .long 0x0001B6DB
-PFC_PMMR_IPSR4: .long 0xFFFE4924
-
-# Enable functios
-# DACK1, DREQ1, SD1_DAT3_A, SD1_CLK_A, IERX_B,
-# IETX_B, TX0_A, RMII0_TXD0_A,
-# RMII0_TXD1_A, RMII0_TXD0_A, SDSEL, SDA0, SDA1, SCL1
-PFC_IPSR11_A: .long 0xFFFC0048
-PFC_IPSR11_D: .long 0x002C89B0
-PFC_PMMR_IPSR11:.long 0xFFD3764F
-
-PFC_GPSR0_A: .long 0xFFFC0004
-PFC_GPSR0_D: .long 0xFFFFFFFF
-PFC_PMMR_GPSR0: .long 0x00000000
-
-PFC_GPSR1_A: .long 0xFFFC0008
-PFC_GPSR1_D: .long 0x7FBF7FFF
-PFC_PMMR_GPSR1: .long 0x80408000
-
-PFC_GPSR2_A: .long 0xFFFC000C
-PFC_GPSR2_D: .long 0xBFC07EDF
-PFC_PMMR_GPSR2: .long 0x403F8120
-
-PFC_GPSR3_A: .long 0xFFFC0010
-PFC_GPSR3_D: .long 0xFFFFFFFF
-PFC_PMMR_GPSR3: .long 0x00000000
-
-PFC_GPSR4_A: .long 0xFFFC0014
-#if 0 /* orig */
-PFC_GPSR4_D: .long 0xFFFFFFFF
-PFC_PMMR_GPSR4: .long 0x00000000
-#else
-PFC_GPSR4_D: .long 0xFBFFFFFF
-PFC_PMMR_GPSR4: .long 0x04000000
-#endif
-
-PFC_GPSR5_A: .long 0xFFFC0018
-PFC_GPSR5_D: .long 0x00000C01
-PFC_PMMR_GPSR5: .long 0xFFFFF3FE
-
-I2C_ICCR2_A: .long 0xFFC70001
-I2C_ICCR2_D: .long 0x00
-I2C_ICCR2_D1: .long 0x20
-
-GPIO2_INOUTSEL1_A: .long 0xFFC41004
-GPIO2_INOUTSEL1_D: .long 0x80408000
-GPIO1_OUTDT1_A: .long 0xFFC41008 /* bit15: LED4, bit22: LED5 */
-GPIO1_OUTDT1_D: .long 0x80408000
-GPIO2_INOUTSEL2_A: .long 0xFFC42004
-GPIO2_INOUTSEL2_D: .long 0x40000120
-GPIO2_OUTDT2_A: .long 0xFFC42008
-GPIO2_OUTDT2_D: .long 0x40000120
-GPIO4_INOUTSEL4_A: .long 0xFFC44004
-GPIO4_INOUTSEL4_D: .long 0x04000000
-GPIO4_OUTDT4_A: .long 0xFFC44008
-GPIO4_OUTDT4_D: .long 0x04000000
-
-CCR_A: .long 0xFF00001C
-CCR_D: .long 0x0000090B
-SR_MASK_D: .long 0xEFFFFF0F
diff --git a/board/renesas/r0p7734/r0p7734.c b/board/renesas/r0p7734/r0p7734.c
deleted file mode 100644
index 7ebde48d29..0000000000
--- a/board/renesas/r0p7734/r0p7734.c
+++ /dev/null
@@ -1,58 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * Copyright (C) 2011 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <netdev.h>
-#include <i2c.h>
-
-#define MODEMR (0xFFCC0020)
-#define MODEMR_MASK (0x6)
-#define MODEMR_533MHZ (0x2)
-
-int checkboard(void)
-{
- u32 r = readl(MODEMR);
- if ((r & MODEMR_MASK) & MODEMR_533MHZ)
- puts("CPU Clock: 533MHz\n");
- else
- puts("CPU Clock: 400MHz\n");
-
- puts("BOARD: Renesas Technology Corp. R0P7734C00000RZ\n");
- return 0;
-}
-
-#define MSTPSR1 (0xFFC80044)
-#define MSTPCR1 (0xFFC80034)
-#define MSTPSR1_GETHER (1 << 14)
-
-int board_init(void)
-{
-#if defined(CONFIG_SH_ETHER)
- u32 r = readl(MSTPSR1);
- if (r & MSTPSR1_GETHER)
- writel((r & ~MSTPSR1_GETHER), MSTPCR1);
-#endif
-
- return 0;
-}
-
-int board_late_init(void)
-{
- printf("Cannot get MAC address from I2C\n");
-
- return 0;
-}
-
-#ifdef CONFIG_SMC911X
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
- return rc;
-}
-#endif
generated by cgit (git 2.34.1) at 2025-01-18 18:55:32 +0000