diff options
Diffstat (limited to 'board/samsung')
| -rw-r--r-- | board/samsung/dts/exynos5250-smdk5250.dts | 53 | ||||
| -rw-r--r-- | board/samsung/dts/exynos5250-snow.dts | 58 | ||||
| -rw-r--r-- | board/samsung/smdk5250/clock_init.c | 22 | ||||
| -rw-r--r-- | board/samsung/smdk5250/setup.h | 2 | ||||
| -rw-r--r-- | board/samsung/smdk5250/smdk5250-uboot-spl.lds | 4 | ||||
| -rw-r--r-- | board/samsung/smdk5250/smdk5250.c | 197 | ||||
| -rw-r--r-- | board/samsung/smdk6400/.gitignore | 5 | ||||
| -rw-r--r-- | board/samsung/smdk6400/Makefile | 48 | ||||
| -rw-r--r-- | board/samsung/smdk6400/config.mk | 30 | ||||
| -rw-r--r-- | board/samsung/smdk6400/lowlevel_init.S | 323 | ||||
| -rw-r--r-- | board/samsung/smdk6400/smdk6400.c | 134 | ||||
| -rw-r--r-- | board/samsung/smdk6400/smdk6400_nand_spl.c | 37 | ||||
| -rw-r--r-- | board/samsung/smdk6400/u-boot-nand.lds | 86 | ||||
| -rw-r--r-- | board/samsung/trats/trats.c | 69 | ||||
| -rw-r--r-- | board/samsung/universal_c210/universal.c | 23 |
15 files changed, 389 insertions, 702 deletions
diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts index cbfab6f97f..8da973b305 100644 --- a/board/samsung/dts/exynos5250-smdk5250.dts +++ b/board/samsung/dts/exynos5250-smdk5250.dts @@ -66,4 +66,57 @@ compatible = "maxim,max77686_pmic"; }; }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <2560>; + samsung,vl-row = <1600>; + samsung,vl-width = <2560>; + samsung,vl-height = <1600>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <32>; + samsung,vl-hbpd = <80>; + samsung,vl-hfpd = <48>; + samsung,vl-vspw = <6>; + samsung,vl-vbpd = <37>; + samsung,vl-vfpd = <3>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; + + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; }; diff --git a/board/samsung/dts/exynos5250-snow.dts b/board/samsung/dts/exynos5250-snow.dts new file mode 100644 index 0000000000..8b303bf4e4 --- /dev/null +++ b/board/samsung/dts/exynos5250-snow.dts @@ -0,0 +1,58 @@ +/* + * SAMSUNG Snow board device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ ARCH_CPU_DTS + +/ { + model = "Google Snow"; + compatible = "google,snow", "samsung,exynos5250"; + + aliases { + i2c0 = "/i2c@12c60000"; + i2c1 = "/i2c@12c70000"; + i2c2 = "/i2c@12c80000"; + i2c3 = "/i2c@12c90000"; + i2c4 = "/i2c@12ca0000"; + i2c5 = "/i2c@12cb0000"; + i2c6 = "/i2c@12cc0000"; + i2c7 = "/i2c@12cd0000"; + spi0 = "/spi@12d20000"; + spi1 = "/spi@12d30000"; + spi2 = "/spi@12d40000"; + spi3 = "/spi@131a0000"; + spi4 = "/spi@131b0000"; + }; + + sound@12d60000 { + samsung,i2s-epll-clock-frequency = <192000000>; + samsung,i2s-sampling-rate = <48000>; + samsung,i2s-bits-per-sample = <16>; + samsung,i2s-channels = <2>; + samsung,i2s-lr-clk-framesize = <256>; + samsung,i2s-bit-clk-framesize = <32>; + samsung,codec-type = "max98095"; + }; + + i2c@12cd0000 { + soundcodec@22 { + reg = <0x22>; + compatible = "maxim,max98095-codec"; + }; + }; + + i2c@12c60000 { + pmic@9 { + reg = <0x9>; + compatible = "maxim,max77686_pmic"; + }; + }; +}; diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index c009ae579a..5b9e82fdf7 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -434,10 +434,10 @@ void system_clock_init() val = readl(&clk->mux_stat_core1); } while ((val | MUX_MPLL_SEL_MASK) != val); - clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK | MUX_GPLL_SEL_MASK; do { @@ -494,35 +494,35 @@ void system_clock_init() val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, arm_clk_ratio->apll_sdiv); writel(val, &clk->apll_con0); - while (readl(&clk->apll_con0) & APLL_CON0_LOCKED) + while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) ; /* Set MPLL */ writel(MPLL_CON1_VAL, &clk->mpll_con1); val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); writel(val, &clk->mpll_con0); - while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) + while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) ; /* Set BPLL */ writel(BPLL_CON1_VAL, &clk->bpll_con1); val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); writel(val, &clk->bpll_con0); - while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) + while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0) ; /* Set CPLL */ writel(CPLL_CON1_VAL, &clk->cpll_con1); val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); writel(val, &clk->cpll_con0); - while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) + while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0) ; /* Set GPLL */ writel(GPLL_CON1_VAL, &clk->gpll_con1); val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); writel(val, &clk->gpll_con0); - while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) + while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0) ; /* Set EPLL */ @@ -530,7 +530,7 @@ void system_clock_init() writel(EPLL_CON1_VAL, &clk->epll_con1); val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); writel(val, &clk->epll_con0); - while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED) + while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) ; /* Set VPLL */ @@ -538,7 +538,7 @@ void system_clock_init() writel(VPLL_CON1_VAL, &clk->vpll_con1); val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); writel(val, &clk->vpll_con0); - while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) + while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) ; writel(CLK_SRC_CORE0_VAL, &clk->src_core0); diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h index a15960121c..34d8bc31f4 100644 --- a/board/samsung/smdk5250/setup.h +++ b/board/samsung/smdk5250/setup.h @@ -343,7 +343,7 @@ #define TOP2_VAL 0x0110000 /* CLK_SRC_PERIC0 */ -#define PWM_SEL 0 +#define PWM_SEL 6 #define UART3_SEL 6 #define UART2_SEL 6 #define UART1_SEL 6 diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds b/board/samsung/smdk5250/smdk5250-uboot-spl.lds index 4ef6a51976..7df0a1d3f8 100644 --- a/board/samsung/smdk5250/smdk5250-uboot-spl.lds +++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds @@ -37,7 +37,7 @@ SECTIONS .text : { __start = .; - arch/arm/cpu/armv7/start.o (.text) + arch/arm/cpu/armv7/start.o (.text*) *(.text*) } >.sram . = ALIGN(4); @@ -66,6 +66,6 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } >.sram } diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 7a5f132ebb..8b09e1de42 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -23,6 +23,7 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> +#include <errno.h> #include <i2c.h> #include <lcd.h> #include <netdev.h> @@ -35,9 +36,40 @@ #include <asm/arch/sromc.h> #include <asm/arch/dp_info.h> #include <power/pmic.h> +#include <power/max77686_pmic.h> +#include <tmu.h> DECLARE_GLOBAL_DATA_PTR; +#if defined CONFIG_EXYNOS_TMU +/* + * Boot Time Thermal Analysis for SoC temperature threshold breach + */ +static void boot_temp_check(void) +{ + int temp; + + switch (tmu_monitor(&temp)) { + /* Status TRIPPED ans WARNING means corresponding threshold breach */ + case TMU_STATUS_TRIPPED: + puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); + set_ps_hold_ctrl(); + hang(); + break; + case TMU_STATUS_WARNING: + puts("EXYNOS_TMU: WARNING! Temperature very high\n"); + break; + /* + * TMU_STATUS_INIT means something is wrong with temperature sensing + * and TMU status was changed back from NORMAL to INIT. + */ + case TMU_STATUS_INIT: + default: + debug("EXYNOS_TMU: Unknown TMU state\n"); + } +} +#endif + #ifdef CONFIG_USB_EHCI_EXYNOS int board_usb_vbus_init(void) { @@ -54,15 +86,39 @@ int board_usb_vbus_init(void) } #endif +#ifdef CONFIG_SOUND_MAX98095 +static void board_enable_audio_codec(void) +{ + struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) + samsung_get_base_gpio_part1(); + + /* Enable MAX98095 Codec */ + s5p_gpio_direction_output(&gpio1->x1, 7, 1); + s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); +} +#endif + int board_init(void) { gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); + +#if defined CONFIG_EXYNOS_TMU + if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { + debug("%s: Failed to init TMU\n", __func__); + return -1; + } + boot_temp_check(); +#endif + #ifdef CONFIG_EXYNOS_SPI spi_init(); #endif #ifdef CONFIG_USB_EHCI_EXYNOS board_usb_vbus_init(); #endif +#ifdef CONFIG_SOUND_MAX98095 + board_enable_audio_codec(); +#endif return 0; } @@ -80,12 +136,119 @@ int dram_init(void) } #if defined(CONFIG_POWER) +static int pmic_reg_update(struct pmic *p, int reg, uint regval) +{ + u32 val; + int ret = 0; + + ret = pmic_reg_read(p, reg, &val); + if (ret) { + debug("%s: PMIC %d register read failed\n", __func__, reg); + return -1; + } + val |= regval; + ret = pmic_reg_write(p, reg, val); + if (ret) { + debug("%s: PMIC %d register write failed\n", __func__, reg); + return -1; + } + return 0; +} + int power_init_board(void) { + struct pmic *p; + + set_ps_hold_ctrl(); + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (pmic_init(I2C_PMIC)) return -1; - else - return 0; + + p = pmic_get("MAX77686_PMIC"); + if (!p) + return -ENODEV; + + if (pmic_probe(p)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, + MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) + return -1; + + /* VDD_MIF */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, + MAX77686_BUCK1OUT_1V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK1OUT); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, + MAX77686_BUCK1CTRL_EN)) + return -1; + + /* VDD_ARM */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, + MAX77686_BUCK2DVS1_1_3V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK2DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, + MAX77686_BUCK2CTRL_ON)) + return -1; + + /* VDD_INT */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, + MAX77686_BUCK3DVS1_1_0125V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK3DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_G3D */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, + MAX77686_BUCK4DVS1_1_2V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK4DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_LDO2 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, + MAX77686_LD02CTRL1_1_5V | EN_LDO)) + return -1; + + /* VDD_LDO3 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, + MAX77686_LD03CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO5 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, + MAX77686_LD05CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO10 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, + MAX77686_LD10CTRL1_1_8V | EN_LDO)) + return -1; + + return 0; } #endif @@ -149,9 +312,10 @@ int board_eth_init(bd_t *bis) u32 smc_bw_conf, smc_bc_conf; struct fdt_sromc config; fdt_addr_t base_addr; - int node; #ifdef CONFIG_OF_CONTROL + int node; + node = decode_sromc(gd->fdt_blob, &config); if (node < 0) { debug("%s: Could not find sromc configuration\n", __func__); @@ -212,8 +376,17 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { - printf("\nBoard: SMDK5250\n"); +#ifdef CONFIG_OF_CONTROL + const char *board_name; + board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + if (board_name == NULL) + printf("\nUnknown Board\n"); + else + printf("\nBoard: %s\n", board_name); +#else + printf("\nBoard: SMDK5250\n"); +#endif return 0; } #endif @@ -282,7 +455,7 @@ int board_early_init_f(void) #endif #ifdef CONFIG_LCD -void cfg_lcd_gpio(void) +void exynos_cfg_lcd_gpio(void) { struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); @@ -299,6 +472,12 @@ void cfg_lcd_gpio(void) s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); } +void exynos_set_dp_phy(unsigned int onoff) +{ + set_dp_phy_ctrl(onoff); +} + +#ifndef CONFIG_OF_CONTROL vidinfo_t panel_info = { .vl_freq = 60, .vl_col = 2560, @@ -322,10 +501,6 @@ vidinfo_t panel_info = { .vl_cmd_allow_len = 0xf, .win_id = 3, - .cfg_gpio = cfg_lcd_gpio, - .backlight_on = NULL, - .lcd_power_on = NULL, - .reset_lcd = NULL, .dual_lcd_enabled = 0, .init_delay = 0, @@ -365,14 +540,16 @@ static struct edp_device_info edp_info = { }; static struct exynos_dp_platform_data dp_platform_data = { - .phy_enable = set_dp_phy_ctrl, .edp_dev_info = &edp_info, }; +#endif void init_panel_info(vidinfo_t *vid) { +#ifndef CONFIG_OF_CONTROL vid->rgb_mode = MODE_RGB_P, exynos_set_dp_platform_data(&dp_platform_data); +#endif } #endif diff --git a/board/samsung/smdk6400/.gitignore b/board/samsung/smdk6400/.gitignore deleted file mode 100644 index 25ab492c50..0000000000 --- a/board/samsung/smdk6400/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -# -# Generated files -# - -/config.tmp diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile deleted file mode 100644 index 0d3e63b769..0000000000 --- a/board/samsung/smdk6400/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := smdk6400.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(SOBJS) $(OBJS) - $(call cmd_link_o_target, $(SOBJS) $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk deleted file mode 100644 index 6f04c2f568..0000000000 --- a/board/samsung/smdk6400/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> -# -# (C) Copyright 2008 -# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> -# -# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu -# -# see http://www.samsung.com/ for more information on SAMSUNG - -# On SMDK6400 we use the 64 MB SDRAM bank at -# -# 0x50000000 to 0x58000000 -# -# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000 -# -# we load ourselves to 0x57e00000 without MMU -# with MMU, load address is changed to 0xc7e00000 -# -# download area is 0x5000c000 - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifndef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = $(RAM_TEXT) -else -CONFIG_SYS_TEXT_BASE = 0 -endif diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S deleted file mode 100644 index f7ce176945..0000000000 --- a/board/samsung/smdk6400/lowlevel_init.S +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <config.h> -#include <version.h> - -#include <asm/arch/s3c6400.h> - -#ifdef CONFIG_SERIAL1 -#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET) -#elif defined(CONFIG_SERIAL2) -#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET) -#else -#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET) -#endif - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - - .globl lowlevel_init -lowlevel_init: - mov r12, lr - - /* LED on only #8 */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x55540000 - str r1, [r0, #GPNCON_OFFSET] - - ldr r1, =0x55555555 - str r1, [r0, #GPNPUD_OFFSET] - - ldr r1, =0xf000 - str r1, [r0, #GPNDAT_OFFSET] - - /* Disable Watchdog */ - ldr r0, =0x7e000000 @0x7e004000 - orr r0, r0, #0x4000 - mov r1, #0 - str r1, [r0] - - /* External interrupt pending clear */ - ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/ - ldr r1, [r0] - str r1, [r0] - - ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 - ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 - - /* Disable all interrupts (VIC0 and VIC1) */ - mvn r3, #0x0 - str r3, [r0, #oINTMSK] - str r3, [r1, #oINTMSK] - - /* Set all interrupts as IRQ */ - mov r3, #0x0 - str r3, [r0, #oINTMOD] - str r3, [r1, #oINTMOD] - - /* Pending Interrupt Clear */ - mov r3, #0x0 - str r3, [r0, #oVECTADDR] - str r3, [r1, #oVECTADDR] - - /* init system clock */ - bl system_clock_init - -#ifndef CONFIG_NAND_SPL - /* for UART */ - bl uart_asm_init -#endif - -#ifdef CONFIG_BOOT_NAND - /* simple init for NAND */ - bl nand_asm_init -#endif - - /* Memory subsystem address 0x7e00f120 */ - ldr r0, =ELFIN_MEM_SYS_CFG - - /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */ - mov r1, #S3C64XX_MEM_SYS_CFG_NAND - str r1, [r0] - - bl mem_ctrl_asm_init - -/* Wakeup support. Don't know if it's going to be used, untested. */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) - ldr r1, [r0] - bic r1, r1, #0xfffffff7 - cmp r1, #0x8 - beq wakeup_reset - -1: - mov lr, r12 - mov pc, lr - -wakeup_reset: - - /* Clear wakeup status register */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) - ldr r1, [r0] - str r1, [r0] - - /* LED test */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x3000 - str r1, [r0, #GPNDAT_OFFSET] - - /* Load return address and jump to kernel */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) - /* r1 = physical address of s3c6400_cpu_resume function */ - ldr r1, [r0] - /* Jump to kernel (sleep-s3c6400.S) */ - mov pc, r1 - nop - nop -/* - * system_clock_init: Initialize core clock and bus clock. - * void system_clock_init(void) - */ -system_clock_init: - ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */ - -#ifdef CONFIG_SYNC_MODE - ldr r1, [r0, #OTHERS_OFFSET] - mov r2, #0x40 - orr r1, r1, r2 - str r1, [r0, #OTHERS_OFFSET] - - nop - nop - nop - nop - nop - - ldr r2, =0x80 - orr r1, r1, r2 - str r1, [r0, #OTHERS_OFFSET] - -check_syncack: - ldr r1, [r0, #OTHERS_OFFSET] - ldr r2, =0xf00 - and r1, r1, r2 - cmp r1, #0xf00 - bne check_syncack -#else /* ASYNC Mode */ - nop - nop - nop - nop - nop - - /* - * This was unconditional in original Samsung sources, but it doesn't - * seem to make much sense on S3C6400. - */ -#ifndef CONFIG_S3C6400 - ldr r1, [r0, #OTHERS_OFFSET] - bic r1, r1, #0xC0 - orr r1, r1, #0x40 - str r1, [r0, #OTHERS_OFFSET] - -wait_for_async: - ldr r1, [r0, #OTHERS_OFFSET] - and r1, r1, #0xf00 - cmp r1, #0x0 - bne wait_for_async -#endif - - ldr r1, [r0, #OTHERS_OFFSET] - bic r1, r1, #0x40 - str r1, [r0, #OTHERS_OFFSET] -#endif - - mov r1, #0xff00 - orr r1, r1, #0xff - str r1, [r0, #APLL_LOCK_OFFSET] - str r1, [r0, #MPLL_LOCK_OFFSET] - - /* Set Clock Divider */ - ldr r1, [r0, #CLK_DIV0_OFFSET] - bic r1, r1, #0x30000 - bic r1, r1, #0xff00 - bic r1, r1, #0xff - ldr r2, =CLK_DIV_VAL - orr r1, r1, r2 - str r1, [r0, #CLK_DIV0_OFFSET] - - ldr r1, =APLL_VAL - str r1, [r0, #APLL_CON_OFFSET] - ldr r1, =MPLL_VAL - str r1, [r0, #MPLL_CON_OFFSET] - - /* FOUT of EPLL is 96MHz */ - ldr r1, =0x200203 - str r1, [r0, #EPLL_CON0_OFFSET] - ldr r1, =0x0 - str r1, [r0, #EPLL_CON1_OFFSET] - - /* APLL, MPLL, EPLL select to Fout */ - ldr r1, [r0, #CLK_SRC_OFFSET] - orr r1, r1, #0x7 - str r1, [r0, #CLK_SRC_OFFSET] - - /* wait at least 200us to stablize all clock */ - mov r1, #0x10000 -1: subs r1, r1, #1 - bne 1b - - /* Synchronization for VIC port */ -#if defined(CONFIG_SYNC_MODE) - ldr r1, [r0, #OTHERS_OFFSET] - orr r1, r1, #0x20 - str r1, [r0, #OTHERS_OFFSET] -#elif !defined(CONFIG_S3C6400) - /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */ - ldr r1, [r0, #OTHERS_OFFSET] - bic r1, r1, #0x20 - str r1, [r0, #OTHERS_OFFSET] -#endif - mov pc, lr - - -#ifndef CONFIG_NAND_SPL -/* - * uart_asm_init: Initialize UART's pins - */ -uart_asm_init: - /* set GPIO to enable UART */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x220022 - str r1, [r0, #GPACON_OFFSET] - mov pc, lr -#endif - -#ifdef CONFIG_BOOT_NAND -/* - * NAND Interface init for SMDK6400 - */ -nand_asm_init: - ldr r0, =ELFIN_NAND_BASE - ldr r1, [r0, #NFCONF_OFFSET] - orr r1, r1, #0x70 - orr r1, r1, #0x7700 - str r1, [r0, #NFCONF_OFFSET] - - ldr r1, [r0, #NFCONT_OFFSET] - orr r1, r1, #0x07 - str r1, [r0, #NFCONT_OFFSET] - - mov pc, lr -#endif - -#ifdef CONFIG_ENABLE_MMU -/* - * MMU Table for SMDK6400 - */ - - /* form a first-level section entry */ -.macro FL_SECTION_ENTRY base,ap,d,c,b - .word (\base << 20) | (\ap << 10) | \ - (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1) -.endm - -.section .mmudata, "a" - .align 14 - /* the following alignment creates the mmu table at address 0x4000. */ - .globl mmu_table -mmu_table: - .set __base, 0 - /* 1:1 mapping for debugging */ - .rept 0xA00 - FL_SECTION_ENTRY __base, 3, 0, 0, 0 - .set __base, __base + 1 - .endr - - /* access is not allowed. */ - .rept 0xC00 - 0xA00 - .word 0x00000000 - .endr - - /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */ - .set __base, 0x500 - .rept 0xC80 - 0xC00 - FL_SECTION_ENTRY __base, 3, 0, 1, 1 - .set __base, __base + 1 - .endr - - /* access is not allowed. */ - .rept 0x1000 - 0xc80 - .word 0x00000000 - .endr -#endif diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c deleted file mode 100644 index c40d1f9b49..0000000000 --- a/board/samsung/smdk6400/smdk6400.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/s3c6400.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -#define CS8900_Tacs 0x0 /* 0clk address set-up */ -#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */ -#define CS8900_Tacc 0xE /* 14clk access cycle */ -#define CS8900_Tcoh 0x1 /* 1clk chip selection hold */ -#define CS8900_Tah 0x4 /* 4clk address holding time */ -#define CS8900_Tacp 0x6 /* 6clk page mode access cycle */ -#define CS8900_PMC 0x0 /* normal(1data)page mode configuration */ - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b" - : "=r" (loops) : "0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -static void cs8900_pre_init(void) -{ - SROM_BW_REG &= ~(0xf << 4); - SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4); - SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) + - (CS8900_Tacc << 16) + (CS8900_Tcoh << 12) + - (CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC); -} - -int board_init(void) -{ - cs8900_pre_init(); - - /* NOR-flash in SROM0 */ - - /* Enable WAIT */ - SROM_BW_REG |= 4 | 8 | 1; - - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - - return 0; -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("Board: SMDK6400\n"); - return 0; -} -#endif - -#ifdef CONFIG_ENABLE_MMU -ulong virt_to_phy_smdk6400(ulong addr) -{ - if ((0xc0000000 <= addr) && (addr < 0xc8000000)) - return addr - 0xc0000000 + 0x50000000; - else - printf("do not support this address : %08lx\n", addr); - - return addr; -} -#endif - -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = FLASH_CFI_16BIT; - info->chipwidth = FLASH_CFI_BY16; - info->interface = FLASH_CFI_X16; - return 1; - } else - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/samsung/smdk6400/smdk6400_nand_spl.c b/board/samsung/smdk6400/smdk6400_nand_spl.c deleted file mode 100644 index a02328497d..0000000000 --- a/board/samsung/smdk6400/smdk6400_nand_spl.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -void board_init_f(unsigned long bootflag) -{ - relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, - CONFIG_SYS_TEXT_BASE); -} diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds deleted file mode 100644 index ae32b1625e..0000000000 --- a/board/samsung/smdk6400/u-boot-nand.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm1176/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - - . = align(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = align(4); - .mmudata : { *(.mmudata) } - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 88d193de28..e20fb3d2e3 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -42,6 +42,7 @@ #include <power/max8997_muic.h> #include <power/battery.h> #include <power/max17042_fg.h> +#include <usb_mass_storage.h> #include "setup.h" @@ -634,7 +635,7 @@ int board_early_init_f(void) return 0; } -static void lcd_reset(void) +void exynos_reset_lcd(void) { struct exynos4_gpio_part2 *gpio2 = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); @@ -754,10 +755,6 @@ vidinfo_t panel_info = { .vl_cmd_allow_len = 0xf, .win_id = 3, - .cfg_gpio = NULL, - .backlight_on = NULL, - .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */ - .reset_lcd = lcd_reset, .dual_lcd_enabled = 0, .init_delay = 0, @@ -791,3 +788,65 @@ void init_panel_info(vidinfo_t *vid) setenv("lcdinfo", "lcd=s6e8ax0"); } + +#ifdef CONFIG_USB_GADGET_MASS_STORAGE +static int ums_read_sector(struct ums_device *ums_dev, + ulong start, lbaint_t blkcnt, void *buf) +{ + if (ums_dev->mmc->block_dev.block_read(ums_dev->dev_num, + start + ums_dev->offset, blkcnt, buf) != blkcnt) + return -1; + + return 0; +} + +static int ums_write_sector(struct ums_device *ums_dev, + ulong start, lbaint_t blkcnt, const void *buf) +{ + if (ums_dev->mmc->block_dev.block_write(ums_dev->dev_num, + start + ums_dev->offset, blkcnt, buf) != blkcnt) + return -1; + + return 0; +} + +static void ums_get_capacity(struct ums_device *ums_dev, + long long int *capacity) +{ + long long int tmp_capacity; + + tmp_capacity = (long long int) ((ums_dev->offset + ums_dev->part_size) + * SECTOR_SIZE); + *capacity = ums_dev->mmc->capacity - tmp_capacity; +} + +static struct ums_board_info ums_board = { + .read_sector = ums_read_sector, + .write_sector = ums_write_sector, + .get_capacity = ums_get_capacity, + .name = "TRATS UMS disk", + .ums_dev = { + .mmc = NULL, + .dev_num = 0, + .offset = 0, + .part_size = 0. + }, +}; + +struct ums_board_info *board_ums_init(unsigned int dev_num, unsigned int offset, + unsigned int part_size) +{ + struct mmc *mmc; + + mmc = find_mmc_device(dev_num); + if (!mmc) + return NULL; + + ums_board.ums_dev.mmc = mmc; + ums_board.ums_dev.dev_num = dev_num; + ums_board.ums_dev.offset = offset; + ums_board.ums_dev.part_size = part_size; + + return &ums_board; +} +#endif diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index e742707f79..9b2770f9d1 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -384,7 +384,7 @@ static void init_pmic_lcd(void) puts("LCD pmic initialisation error!\n"); } -static void lcd_cfg_gpio(void) +void exynos_cfg_lcd_gpio(void) { unsigned int i, f3_end = 4; @@ -423,7 +423,7 @@ static void lcd_cfg_gpio(void) spi_init(); } -static void reset_lcd(void) +void exynos_reset_lcd(void) { s5p_gpio_set_value(&gpio2->y4, 5, 1); udelay(10000); @@ -433,7 +433,7 @@ static void reset_lcd(void) udelay(100); } -static void lcd_power_on(void) +void exynos_lcd_power_on(void) { struct pmic *p = pmic_get("MAX8998_PMIC"); @@ -471,10 +471,6 @@ vidinfo_t panel_info = { .vl_cmd_allow_len = 0xf, .win_id = 0, - .cfg_gpio = lcd_cfg_gpio, - .backlight_on = NULL, - .lcd_power_on = lcd_power_on, - .reset_lcd = reset_lcd, .dual_lcd_enabled = 0, .init_delay = 0, @@ -484,6 +480,16 @@ vidinfo_t panel_info = { .mipi_enabled = 0, }; +void exynos_cfg_ldo(void) +{ + ld9040_cfg_ldo(); +} + +void exynos_enable_ldo(unsigned int onoff) +{ + ld9040_enable_ldo(onoff); +} + void init_panel_info(vidinfo_t *vid) { vid->logo_on = 1; @@ -498,9 +504,6 @@ void init_panel_info(vidinfo_t *vid) vid->pclk_name = 1; /* MPLL */ vid->sclk_div = 1; - vid->cfg_ldo = ld9040_cfg_ldo; - vid->enable_ldo = ld9040_enable_ldo; - setenv("lcdinfo", "lcd=ld9040"); } |