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-rw-r--r--board/ti/am43xx/board.c33
-rw-r--r--board/ti/beagle_x15/board.c67
-rw-r--r--board/ti/beagle_x15/mux_data.h351
-rw-r--r--board/ti/dra7xx/evm.c96
-rw-r--r--board/ti/dra7xx/mux_data.h339
5 files changed, 722 insertions, 164 deletions
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 4aae230608..d7b9e5af88 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -148,6 +148,29 @@ static const struct dpll_params idk_dpll_ddr = {
400, 23, 1, -1, 2, -1, -1
};
+static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
+ 0x00500050,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40001000,
+ 0x08102040
+};
+
const struct ctrl_ioregs ioregs_lpddr2 = {
.cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
.cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
@@ -318,6 +341,16 @@ static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
.emif_cos_config = 0x00ffffff
};
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+ if (board_is_eposevm()) {
+ *regs = ext_phy_ctrl_const_base_lpddr2;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+ }
+
+ return;
+}
+
/*
* get_sys_clk_index : returns the index of the sys_clk read from
* ctrl status register. This value is either
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
index ffcd53185b..b6c17ec83f 100644
--- a/board/ti/beagle_x15/board.c
+++ b/board/ti/beagle_x15/board.c
@@ -15,6 +15,7 @@
#include <asm/omap_common.h>
#include <asm/emif.h>
#include <asm/arch/clock.h>
+#include <asm/arch/dra7xx_iodelay.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
@@ -52,23 +53,29 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190b,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
+/* Ext phy ctrl regs 1-35 */
static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x10040100,
+ 0x00740074,
+ 0x00780078,
+ 0x007c007c,
+ 0x007b007b,
0x00800080,
0x00360036,
0x00340034,
@@ -90,14 +97,19 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
0x00000000,
0x00600020,
- 0x40010080,
+ 0x40011080,
0x08102040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
- 0x00400040
+ 0x00400040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
};
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
@@ -109,23 +121,28 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190b,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x10040100,
+ 0x00820082,
+ 0x008b008b,
+ 0x00800080,
+ 0x007e007e,
0x00800080,
0x00370037,
0x00390039,
@@ -145,14 +162,19 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
0x00000000,
0x00600020,
- 0x40010080,
+ 0x40011080,
0x08102040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
- 0x00400040
+ 0x00400040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
};
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
@@ -240,23 +262,20 @@ int board_late_init(void)
return 0;
}
-static void do_set_mux32(u32 base,
- struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_essential(void)
{
- int i;
- struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
-
- for (i = 0; i < size; i++, pad++)
- writel(pad->val, base + pad->offset);
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ early_padconf, ARRAY_SIZE(early_padconf));
}
-void set_muxconf_regs_essential(void)
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void recalibrate_iodelay(void)
{
- do_set_mux32((*ctrl)->control_padconf_core_base,
- core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
+ __recalibrate_iodelay(core_padconf_array_essential,
+ ARRAY_SIZE(core_padconf_array_essential),
+ iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
}
+#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h
index df658c5211..09d3650983 100644
--- a/board/ti/beagle_x15/mux_data.h
+++ b/board/ti/beagle_x15/mux_data.h
@@ -13,43 +13,318 @@
#include <asm/arch/mux_dra7xx.h>
const struct pad_conf_entry core_padconf_array_essential[] = {
- {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
- {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
- {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
- {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
- {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
- {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
- {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
- {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
- {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
- {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
- {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
- {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
- {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
- {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
- {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
- {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
- {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
- {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
- {UART2_CTSN, (FSC | IEN | PTU | PDIS | M2)}, /* uart2_ctsn.uart3_rxd */
- {UART2_RTSN, (FSC | IEN | PTU | PDIS | M1)}, /* uart2_rtsn.uart3_txd */
- {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
- {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
- {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
- {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
- {RGMII0_TXC, (M0) },
- {RGMII0_TXCTL, (M0) },
- {RGMII0_TXD3, (M0) },
- {RGMII0_TXD2, (M0) },
- {RGMII0_TXD1, (M0) },
- {RGMII0_TXD0, (M0) },
- {RGMII0_RXC, (IEN | M0) },
- {RGMII0_RXCTL, (IEN | M0) },
- {RGMII0_RXD3, (IEN | M0) },
- {RGMII0_RXD2, (IEN | M0) },
- {RGMII0_RXD1, (IEN | M0) },
- {RGMII0_RXD0, (IEN | M0) },
- {USB1_DRVVBUS, (M0 | FSC) },
- {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */
+ {GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */
+ {GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */
+ {GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */
+ {GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */
+ {GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */
+ {GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */
+ {GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */
+ {GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */
+ {GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */
+ {GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */
+ {GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */
+ {GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */
+ {GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */
+ {GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */
+ {GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */
+ {GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */
+ {GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */
+ {GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */
+ {GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */
+ {GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin3a_d19 */
+ {GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin3a_d20 */
+ {GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vin3a_d21 */
+ {GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin3a_d22 */
+ {GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin3a_d23 */
+ {GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vin3a_hsync0 */
+ {GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin3a_vsync0 */
+ {GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin3a_de0 */
+ {GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin3a_fld0 */
+ {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */
+ {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */
+ {GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */
+ {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */
+ {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */
+ {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */
+ {GPMC_A18, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a18.gpio2_8 */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */
+ {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */
+ {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.vin3a_clk0 */
+ {GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */
+ {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
+ {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
+ {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */
+ {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */
+ {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */
+ {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */
+ {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */
+ {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */
+ {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */
+ {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */
+ {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */
+ {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */
+ {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */
+ {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */
+ {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
+ {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d11.gpio3_15 */
+ {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */
+ {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */
+ {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */
+ {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */
+ {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */
+ {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d21.vin1a_d21 */
+ {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */
+ {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */
+ {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */
+ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
+ {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */
+ {VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */
+ {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
+ {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
+ {VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */
+ {VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */
+ {VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */
+ {VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */
+ {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */
+ {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */
+ {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */
+ {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */
+ {VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */
+ {VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */
+ {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
+ {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */
+ {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */
+ {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */
+ {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */
+ {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */
+ {GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */
+ {GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */
+ {XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.clkout2 */
+ {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */
+ {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
+ {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+ {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */
+ {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */
+ {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */
+ {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */
+ {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
+ {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
+ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.gpio5_10 */
+ {MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.gpio5_11 */
+ {MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.gpio5_12 */
+ {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */
+ {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.mcasp7_axr0 */
+ {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
+ {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.mcasp7_aclkx */
+ {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.mcasp7_fsx */
+ {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */
+ {MCASP2_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.mcasp2_fsx */
+ {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
+ {MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */
+ {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */
+ {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */
+ {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.mcasp2_axr2 */
+ {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.mcasp2_axr3 */
+ {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */
+ {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */
+ {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */
+ {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.mcasp2_axr7 */
+ {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
+ {MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */
+ {MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */
+ {MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */
+ {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.uart8_rxd */
+ {MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */
+ {MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */
+ {MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */
+ {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.uart9_rxd */
+ {MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */
+ {MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */
+ {MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.mmc1_sdcd */
+ {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
+ {GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */
+ {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
+ {MMC3_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_clk.mmc3_clk */
+ {MMC3_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.mmc3_cmd */
+ {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.mmc3_dat0 */
+ {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.mmc3_dat1 */
+ {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.mmc3_dat2 */
+ {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.mmc3_dat3 */
+ {MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */
+ {MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */
+ {MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */
+ {MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */
+ {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
+ {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
+ {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
+ {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */
+ {SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */
+ {SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */
+ {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */
+ {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
+ {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
+ {UART1_RXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_txd.uart1_txd */
+ {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.Driveroff */
+ {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* N/A.Driveroff */
+ {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.Driveroff */
+ {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
+ {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */
+ {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */
+ {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */
+ {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
+ {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */
};
+
+const struct pad_conf_entry early_padconf[] = {
+ {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
+ {I2C1_SDA, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SDA */
+ {I2C1_SCL, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SCL */
+};
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry iodelay_cfg_array[] = {
+ {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
+ {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
+ {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
+ {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */
+ {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */
+ {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */
+ {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */
+ {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */
+ {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */
+ {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */
+ {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */
+ {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */
+ {0x0264, 2466, 0}, /* CFG_GPMC_AD0_IN */
+ {0x0270, 2523, 0}, /* CFG_GPMC_AD10_IN */
+ {0x027C, 2453, 0}, /* CFG_GPMC_AD11_IN */
+ {0x0288, 2285, 0}, /* CFG_GPMC_AD12_IN */
+ {0x0294, 2206, 0}, /* CFG_GPMC_AD13_IN */
+ {0x02A0, 1898, 0}, /* CFG_GPMC_AD14_IN */
+ {0x02AC, 2473, 0}, /* CFG_GPMC_AD15_IN */
+ {0x02B8, 2307, 0}, /* CFG_GPMC_AD1_IN */
+ {0x02C4, 2691, 0}, /* CFG_GPMC_AD2_IN */
+ {0x02D0, 2384, 0}, /* CFG_GPMC_AD3_IN */
+ {0x02DC, 2462, 0}, /* CFG_GPMC_AD4_IN */
+ {0x02E8, 2335, 0}, /* CFG_GPMC_AD5_IN */
+ {0x02F4, 2370, 0}, /* CFG_GPMC_AD6_IN */
+ {0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */
+ {0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */
+ {0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */
+ {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 11, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 7, 120}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 276, 120}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 440, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
+ {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
+};
+#endif
#endif /* _MUX_DATA_BEAGLE_X15_H_ */
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index d4648558ec..94a1a8c256 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -17,6 +17,7 @@
#include <usb.h>
#include <linux/usb/gadget.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/dra7xx_iodelay.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
@@ -40,43 +41,6 @@ const struct omap_sysinfo sysinfo = {
"Board: DRA7xx\n"
};
-/*
- * Adjust I/O delays on the Tx control and data lines of each MAC port. This
- * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
- * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
- * essentially need to counteract the DRA7xx internal delay, and we do this
- * by delaying the control and data lines. If not using this PHY, you probably
- * don't need to do this stuff!
- */
-static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
-{
- int i = 0;
- u32 reg_val;
- u32 delta;
- u32 coarse;
- u32 fine;
-
- writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
-
- while(io_dly[i].addr) {
- writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
- io_dly[i].addr);
- delta = io_dly[i].dly;
- reg_val = readl(io_dly[i].addr) & 0x3ff;
- coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
- coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
- fine = (reg_val & 0x1F) + (delta & 0x1F);
- fine = (fine > 0x1F) ? (0x1F) : (fine);
- reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
- CFG_IO_DELAY_LOCK_MASK |
- ((coarse << 5) | (fine));
- writel(reg_val, io_dly[i].addr);
- i++;
- }
-
- writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
-}
-
/**
* @brief board_init
*
@@ -107,23 +71,28 @@ int board_late_init(void)
return 0;
}
-static void do_set_mux32(u32 base,
- struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_essential(void)
{
- int i;
- struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
-
- for (i = 0; i < size; i++, pad++)
- writel(pad->val, base + pad->offset);
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ early_padconf, ARRAY_SIZE(early_padconf));
}
-void set_muxconf_regs_essential(void)
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void recalibrate_iodelay(void)
{
- do_set_mux32((*ctrl)->control_padconf_core_base,
- core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
+ if (is_dra72x()) {
+ __recalibrate_iodelay(core_padconf_array_essential,
+ ARRAY_SIZE(core_padconf_array_essential),
+ iodelay_cfg_array,
+ ARRAY_SIZE(iodelay_cfg_array));
+ } else {
+ __recalibrate_iodelay(dra74x_core_padconf_array,
+ ARRAY_SIZE(dra74x_core_padconf_array),
+ dra742_iodelay_cfg_array,
+ ARRAY_SIZE(dra742_iodelay_cfg_array));
+ }
}
+#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
@@ -257,19 +226,6 @@ int spl_start_uboot(void)
#endif
#ifdef CONFIG_DRIVER_TI_CPSW
-
-/* Delay value to add to calibrated value */
-#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
-#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
-#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
-#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
-#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
-#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
-#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
-#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
-#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
-#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
-
extern u32 *const omap_si_rev;
static void cpsw_control(int enabled)
@@ -317,22 +273,6 @@ int board_eth_init(bd_t *bis)
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
uint32_t ctrl_val;
- const struct io_delay io_dly[] = {
- {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
- {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
- {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
- {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
- {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
- {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
- {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
- {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
- {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
- {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
- {0}
- };
-
- /* Adjust IO delay for RGMII tx path */
- dra7xx_adj_io_delay(io_dly);
/* try reading mac address from efuse */
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 48240779c9..c9301a51c0 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -76,30 +76,30 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
{MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
{MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
- {RGMII0_TXC, (M0) },
- {RGMII0_TXCTL, (M0) },
- {RGMII0_TXD3, (M0) },
- {RGMII0_TXD2, (M0) },
- {RGMII0_TXD1, (M0) },
- {RGMII0_TXD0, (M0) },
- {RGMII0_RXC, (IEN | M0) },
- {RGMII0_RXCTL, (IEN | M0) },
- {RGMII0_RXD3, (IEN | M0) },
- {RGMII0_RXD2, (IEN | M0) },
- {RGMII0_RXD1, (IEN | M0) },
- {RGMII0_RXD0, (IEN | M0) },
- {VIN2A_D12, (M3) },
- {VIN2A_D13, (M3) },
- {VIN2A_D14, (M3) },
- {VIN2A_D15, (M3) },
- {VIN2A_D16, (M3) },
- {VIN2A_D17, (M3) },
- {VIN2A_D18, (IEN | M3)},
- {VIN2A_D19, (IEN | M3)},
- {VIN2A_D20, (IEN | M3)},
- {VIN2A_D21, (IEN | M3)},
- {VIN2A_D22, (IEN | M3)},
- {VIN2A_D23, (IEN | M3)},
+ {RGMII0_TXC, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_TXCTL, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_TXD3, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_TXD2, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_TXD1, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_TXD0, (PIN_OUTPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXC, (PIN_INPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXCTL, (PIN_INPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXD3, (PIN_INPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXD2, (PIN_INPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXD1, (PIN_INPUT | MANUAL_MODE | M0) },
+ {RGMII0_RXD0, (PIN_INPUT | MANUAL_MODE | M0) },
+ {VIN2A_D12, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D13, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D14, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D15, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D16, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D17, (PIN_OUTPUT | MANUAL_MODE | M3) },
+ {VIN2A_D18, (PIN_INPUT | MANUAL_MODE | M3)},
+ {VIN2A_D19, (PIN_INPUT | MANUAL_MODE | M3)},
+ {VIN2A_D20, (PIN_INPUT | MANUAL_MODE | M3)},
+ {VIN2A_D21, (PIN_INPUT | MANUAL_MODE | M3)},
+ {VIN2A_D22, (PIN_INPUT | MANUAL_MODE | M3)},
+ {VIN2A_D23, (PIN_INPUT | MANUAL_MODE | M3)},
#if defined(CONFIG_NAND) || defined(CONFIG_NOR)
/* NAND / NOR pin-mux */
{GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
@@ -141,4 +141,295 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{USB2_DRVVBUS, (M0 | IEN | FSC) },
{SPI1_CS1, (PEN | IDIS | M14) },
};
+
+const struct pad_conf_entry early_padconf[] = {
+#if (CONFIG_CONS_INDEX == 1)
+ {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
+ {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */
+#elif (CONFIG_CONS_INDEX == 3)
+ {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */
+ {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */
+#endif
+ {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */
+ {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */
+};
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry iodelay_cfg_array[] = {
+ {0x6F0, 480, 0}, /* RGMMI0_RXC_IN */
+ {0x6FC, 111, 1641}, /* RGMMI0_RXCTL_IN */
+ {0x708, 272, 1116}, /* RGMMI0_RXD0_IN */
+ {0x714, 243, 1260}, /* RGMMI0_RXD1_IN */
+ {0x720, 0, 1614}, /* RGMMI0_RXD2_IN */
+ {0x72C, 105, 1673}, /* RGMMI0_RXD3_IN */
+ {0x740, 531, 120}, /* RGMMI0_TXC_OUT */
+ {0x74C, 11, 60}, /* RGMMI0_TXCTL_OUT */
+ {0x758, 7, 120}, /* RGMMI0_TXD0_OUT */
+ {0x764, 0, 0}, /* RGMMI0_TXD1_OUT */
+ {0x770, 276, 120}, /* RGMMI0_TXD2_OUT */
+ {0x77C, 440, 120}, /* RGMMI0_TXD3_OUT */
+ {0xAB0, 702, 0}, /* CFG_VIN2A_D18_IN */
+ {0xABC, 136, 976}, /* CFG_VIN2A_D19_IN */
+ {0xAD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
+ {0xAE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
+ {0xAEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
+ {0xAF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
+ {0xA70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
+ {0xA7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
+ {0xA88, 876, 0}, /* CFG_VIN2A_D14_OUT */
+ {0xA94, 312, 0}, /* CFG_VIN2A_D15_OUT */
+ {0xAA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
+ {0xAAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+};
+#endif
+
+const struct pad_conf_entry dra74x_core_padconf_array[] = {
+ {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
+ {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
+ {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
+ {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
+ {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
+ {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
+ {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
+ {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
+ {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
+ {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
+ {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
+ {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
+ {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
+ {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
+ {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
+ {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
+ {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
+ {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
+ {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
+ {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
+ {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
+ {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
+ {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
+ {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
+ {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
+ {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
+ {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
+ {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
+ {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.qspi1_rtclk */
+ {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a14.qspi1_d3 */
+ {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.qspi1_d2 */
+ {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.qspi1_d0 */
+ {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.qspi1_sclk */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.qspi1_cs0 */
+ {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
+ {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */
+ {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */
+ {VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_fld0.vin1a_fld0 */
+ {VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_hsync0.vin1a_hsync0 */
+ {VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_vsync0.vin1a_vsync0 */
+ {VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d0.vin1a_d0 */
+ {VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d1.vin1a_d1 */
+ {VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d2.vin1a_d2 */
+ {VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d3.vin1a_d3 */
+ {VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d4.vin1a_d4 */
+ {VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d5.vin1a_d5 */
+ {VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d6.vin1a_d6 */
+ {VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d7.vin1a_d7 */
+ {VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d8.vin1a_d8 */
+ {VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d9.vin1a_d9 */
+ {VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d10.vin1a_d10 */
+ {VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d11.vin1a_d11 */
+ {VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d12.vin1a_d12 */
+ {VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d13.vin1a_d13 */
+ {VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d14.vin1a_d14 */
+ {VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d15.vin1a_d15 */
+ {VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d16.vin1a_d16 */
+ {VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d17.vin1a_d17 */
+ {VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d18.vin1a_d18 */
+ {VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d19.vin1a_d19 */
+ {VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d20.vin1a_d20 */
+ {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d21.vin1a_d21 */
+ {VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d22.vin1a_d22 */
+ {VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d23.vin1a_d23 */
+ {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
+ {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
+ {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
+ {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
+ {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
+ {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
+ {MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.mcasp1_aclkx */
+ {MCASP1_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.mcasp1_fsx */
+ {MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp1_axr0.mcasp1_axr0 */
+ {MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.mcasp1_axr1 */
+ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
+ {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
+ {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
+ {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
+ {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
+ {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
+ {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
+ {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
+ {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */
+ {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
+ {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
+ {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
+ {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
+ {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
+ {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
+ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
+ {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
+ {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
+ {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
+ {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
+ {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
+ {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
+ {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
+ {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
+ {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
+ {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
+ {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
+ {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
+ {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */
+ {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */
+ {WAKEUP0, (M1 | PIN_OUTPUT)}, /* Wakeup0.dcan1_rx */
+ {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */
+};
+
+#ifdef CONFIG_IODELAY_RECALIBRATION
+const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = {
+ {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 0, 0}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 1560, 120}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 1570, 120}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 1500, 120}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 1775, 120}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 1875, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
+ {0x08DC, 2600, 0}, /* CFG_VIN1A_D0_IN */
+ {0x08E8, 2652, 46}, /* CFG_VIN1A_D10_IN */
+ {0x08F4, 2541, 0}, /* CFG_VIN1A_D11_IN */
+ {0x0900, 2603, 574}, /* CFG_VIN1A_D12_IN */
+ {0x090C, 2548, 443}, /* CFG_VIN1A_D13_IN */
+ {0x0918, 2624, 598}, /* CFG_VIN1A_D14_IN */
+ {0x0924, 2535, 1027}, /* CFG_VIN1A_D15_IN */
+ {0x0930, 2526, 818}, /* CFG_VIN1A_D16_IN */
+ {0x093C, 2623, 797}, /* CFG_VIN1A_D17_IN */
+ {0x0948, 2578, 888}, /* CFG_VIN1A_D18_IN */
+ {0x0954, 2574, 1008}, /* CFG_VIN1A_D19_IN */
+ {0x0960, 2527, 123}, /* CFG_VIN1A_D1_IN */
+ {0x096C, 2577, 737}, /* CFG_VIN1A_D20_IN */
+ {0x0978, 2627, 616}, /* CFG_VIN1A_D21_IN */
+ {0x0984, 2573, 777}, /* CFG_VIN1A_D22_IN */
+ {0x0990, 2730, 67}, /* CFG_VIN1A_D23_IN */
+ {0x099C, 2509, 303}, /* CFG_VIN1A_D2_IN */
+ {0x09A8, 2494, 267}, /* CFG_VIN1A_D3_IN */
+ {0x09B4, 2474, 0}, /* CFG_VIN1A_D4_IN */
+ {0x09C0, 2556, 181}, /* CFG_VIN1A_D5_IN */
+ {0x09CC, 2516, 195}, /* CFG_VIN1A_D6_IN */
+ {0x09D8, 2589, 210}, /* CFG_VIN1A_D7_IN */
+ {0x09E4, 2624, 75}, /* CFG_VIN1A_D8_IN */
+ {0x09F0, 2704, 14}, /* CFG_VIN1A_D9_IN */
+ {0x09FC, 2469, 55}, /* CFG_VIN1A_DE0_IN */
+ {0x0A08, 2557, 264}, /* CFG_VIN1A_FLD0_IN */
+ {0x0A14, 2465, 269}, /* CFG_VIN1A_HSYNC0_IN */
+ {0x0A20, 2411, 348}, /* CFG_VIN1A_VSYNC0_IN */
+ {0x0A70, 150, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 1500, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 1600, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 900, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 680, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 500, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
+ {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
+};
+#endif
+
#endif /* _MUX_DATA_DRA7XX_H_ */
generated by cgit (git 2.34.1) at 2025-01-24 04:53:41 +0000