14 files changed, 412 insertions, 43 deletions

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index f4b972b3e9..b371376bc7 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -134,7 +134,7 @@ static int read_eeprom(void)
 
 static void rtc32k_enable(void)
 {
-	struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
 	/*
 	 * Unlock the RTC's registers.  For more details please see the
@@ -208,6 +208,14 @@ static const struct ddr_data ddr3_data = {
 	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
+static const struct ddr_data ddr3_beagleblack_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
 static const struct ddr_data ddr3_evm_data = {
 	.datardsratio0 = MT41J512M8RH125_RD_DQS,
 	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
@@ -230,6 +238,20 @@ static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 };
 
+static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 	.cmd0csratio = MT41J512M8RH125_RATIO,
 	.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
@@ -251,7 +273,18 @@ static struct emif_regs ddr3_emif_reg_data = {
 	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 	.zq_config = MT41J128MJT125_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
+	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
+};
+
+static struct emif_regs ddr3_beagleblack_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 };
 
 static struct emif_regs ddr3_evm_emif_reg_data = {
@@ -261,7 +294,8 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
+	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
 };
 #endif
 
@@ -341,15 +375,20 @@ void s_init(void)
 		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 	}
 
-	if (board_is_evm_sk() || board_is_bone_lt())
+	if (board_is_evm_sk())
 		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
-			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+	else if (board_is_bone_lt())
+		config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
+			   &ddr3_beagleblack_data,
+			   &ddr3_beagleblack_cmd_ctrl_data,
+			   &ddr3_beagleblack_emif_reg_data, 0);
 	else if (board_is_evm_15_or_later())
 		config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
-			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
+			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 	else
 		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
-			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
+			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 #endif
 }
 
@@ -412,8 +451,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 };
 
 static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= AM335X_CPSW_MDIO_BASE,
-	.cpsw_base		= AM335X_CPSW_BASE,
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
 	.mdio_div		= 0xff,
 	.channels		= 8,
 	.cpdma_reg_ofs		= 0x800,
diff --git a/board/ti/omap2420h4/config.mk b/board/ti/omap2420h4/config.mk
index ca5ebdf96a..e5dff69a15 100644
--- a/board/ti/omap2420h4/config.mk
+++ b/board/ti/omap2420h4/config.mk
@@ -14,7 +14,7 @@
 # (mem base + reserved)
 
 # For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80e80000
+#CONFIG_SYS_TEXT_BASE = 0x80e80000
 
 # Used with full SRAM boot.
 # This is either with a GP system or a signed boot image.
@@ -24,5 +24,5 @@ CONFIG_SYS_TEXT_BASE = 0x80e80000
 
 # Handy to get symbols to debug ROM version.
 #CONFIG_SYS_TEXT_BASE = 0x0
-#CONFIG_SYS_TEXT_BASE = 0x08000000
+CONFIG_SYS_TEXT_BASE = 0x08000000
 #CONFIG_SYS_TEXT_BASE = 0x04000000
diff --git a/board/ti/omap2420h4/mem.c b/board/ti/omap2420h4/mem.c
index c8b4186dc8..ba3f12aded 100644
--- a/board/ti/omap2420h4/mem.c
+++ b/board/ti/omap2420h4/mem.c
@@ -200,19 +200,6 @@ void do_sdrc_init(u32 offset, u32 early)
 
 	__asm__ __volatile__("": : :"memory");  /* limit compiler scope */
 
-	/* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx.
-	 * If we are running in flash prior to relocation and we use data
-	 * here which is not pc relative we need to get the address correct.
-	 * We need to find the current flash mapping to dress up the initial
-	 * pointer load.  As long as this is const data we should be ok.
-	 */
-	if((early) && running_in_flash()){
-		sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base());
-		/* NOR internal boot offset is 0x4000 from xloader signature */
-		if(running_from_internal_boot())
-			sdata = (sdrc_data_t *)((u32)sdata + 0x4000);
-	}
-
 	if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) {
 		if(mtype == DDR_COMBO){
 			pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */
diff --git a/board/ti/omap2420h4/omap2420h4.c b/board/ti/omap2420h4/omap2420h4.c
index 188e4acc09..532e989bac 100644
--- a/board/ti/omap2420h4/omap2420h4.c
+++ b/board/ti/omap2420h4/omap2420h4.c
@@ -190,10 +190,10 @@ void ether_init (void)
  * Routine: dram_init
  * Description: sets uboots idea of sdram size
  **********************************************/
-int dram_init (void)
+int dram_init(void)
 {
 	unsigned int size0=0,size1=0;
-	u32 mtype, btype, rev;
+	u32 mtype, btype;
 	u8 chg_on = 0x5; /* enable charge of back up battery */
 	u8 vmode_on = 0x8C;
 	#define NOT_EARLY 0
@@ -202,7 +202,6 @@ int dram_init (void)
 
 	btype = get_board_type();
 	mtype = get_mem_type();
-	rev = get_cpu_rev();
 
 	display_board_info(btype);
 	if (btype == BOARD_H4_MENELAUS){
@@ -217,15 +216,28 @@ int dram_init (void)
 	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
 	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
 
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, size0 + size1);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	unsigned int size0, size1;
+	u32 rev;
+
+	rev = get_cpu_rev();
+	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
+
 	if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
 		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	else /* ES2 and above can remap at 32MB granularity */
 		gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
 	gd->bd->bi_dram[1].size = size1;
 
-	return 0;
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
 }
 
 /**********************************************************
diff --git a/board/ti/omap5912osk/config.mk b/board/ti/omap5912osk/config.mk
index 0ed7d8a6a7..5b8d952ba6 100644
--- a/board/ti/omap5912osk/config.mk
+++ b/board/ti/omap5912osk/config.mk
@@ -14,17 +14,17 @@
 # TI OSK board with OMAP5912 (ARM925EJS) cpu
 # see http://www.ti.com/ for more information on Texas Instruments
 #
-# OSK has 1 bank of 256 MB SDRAM
+# OSK has 1 bank of 32 MB SDRAM
 # Physical Address:
-# 1000'0000 to 2000'0000
+# 1000'0000 to 1200'0000
 #
 #
 # Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
 # (mem base + reserved)
 #
-# we load ourself to 1108'0000
+# When running from RAM use address 1108'0000, otherwise when
+# booting from NOR flash link to address 0000'0000.
 #
-#
-
 
-CONFIG_SYS_TEXT_BASE = 0x11080000
+CONFIG_SYS_TEXT_BASE = 0x00000000
+#CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S
index e60161ebaf..ca7361e05a 100644
--- a/board/ti/omap5912osk/lowlevel_init.S
+++ b/board/ti/omap5912osk/lowlevel_init.S
@@ -306,6 +306,23 @@ common_tc:
 	ldr	r1,	VAL_MPU_CNTL_TIMER
 	str	r1,	[r0]
 
+	/*
+	 * Setup a temporary stack
+	 */
+	ldr	sp,	SRAM_STACK
+	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
+
+	/*
+	 * Save the old lr(passed in ip) and the current lr to stack
+	 */
+	push	{ip, lr}
+
+	/*
+	 * go setup pll, mux, memory
+	 */
+	bl	s_init
+	pop	{ip, pc}
+
 	/* back to arch calling code */
 	mov	pc,	lr
 
@@ -470,6 +487,9 @@ VAL_ARM_IDLECT2:
 VAL_ARM_IDLECT3:
 	.word 0x00000015
 
+SRAM_STACK:
+	.word CONFIG_SYS_INIT_SP_ADDR
+
 /* command values */
 .equ CMD_SDRAM_NOP,             0x00000000
 .equ CMD_SDRAM_PRECHARGE,       0x00000001
diff --git a/board/ti/omap5912osk/omap5912osk.c b/board/ti/omap5912osk/omap5912osk.c
index fac683a7e6..95140719aa 100644
--- a/board/ti/omap5912osk/omap5912osk.c
+++ b/board/ti/omap5912osk/omap5912osk.c
@@ -66,6 +66,14 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x10000100;
 
+	flash__init();
+	ether__init();
+
+	return 0;
+}
+
+void s_init(void)
+{
 	/* Configure MUX settings */
 	set_muxconf_regs ();
 	peripheral_power_enable ();
@@ -75,10 +83,6 @@ int board_init (void)
  *  ... rkw ...
  */
 	icache_enable ();
-
-	flash__init ();
-	ether__init ();
-	return 0;
 }
 
 /******************************
@@ -128,14 +132,19 @@ void ether__init (void)
  Routine:
  Description:
 ******************************/
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 
 	return 0;
 }
 
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
 /******************************************************
  Routine: set_muxconf_regs
  Description: Setting up the configuration Mux registers
diff --git a/board/ti/omap5_evm/Makefile b/board/ti/omap5_uevm/Makefile
index fa81d64bee..fa81d64bee 100644
--- a/board/ti/omap5_evm/Makefile
+++ b/board/ti/omap5_uevm/Makefile
diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_uevm/evm.c
index 55337c09d5..55337c09d5 100644
--- a/board/ti/omap5_evm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_uevm/mux_data.h
index a82795dc13..a82795dc13 100644
--- a/board/ti/omap5_evm/mux_data.h
+++ b/board/ti/omap5_uevm/mux_data.h
diff --git a/board/ti/ti814x/Makefile b/board/ti/ti814x/Makefile
new file mode 100644
index 0000000000..09d24222f3
--- /dev/null
+++ b/board/ti/ti814x/Makefile
@@ -0,0 +1,46 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS	:= mux.o
+endif
+
+COBJS	+= evm.o
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
new file mode 100644
index 0000000000..446e36b844
--- /dev/null
+++ b/board/ti/ti814x/evm.c
@@ -0,0 +1,198 @@
+/*
+ * evm.c
+ *
+ * Board functions for TI814x EVM
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include "evm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+#endif
+
+/* UART Defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
+static void rtc32k_enable(void)
+{
+	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(0x83e70b13, &rtc->kick0r);
+	writel(0x95a4f1e0, &rtc->kick1r);
+
+	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
+	writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+static void uart_enable(void)
+{
+	u32 regVal;
+
+	/* UART softreset */
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_RESET;
+	writel(regVal, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_SMART_IDLE_EN;
+	writel(regVal, &uart_base->uartsyscfg);
+}
+
+static void wdt_disable(void)
+{
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
+
+static const struct cmd_control evm_ddr2_cctrl_data = {
+	.cmd0csratio	= 0x80,
+	.cmd0dldiff	= 0x04,
+	.cmd0iclkout	= 0x00,
+
+	.cmd1csratio	= 0x80,
+	.cmd1dldiff	= 0x04,
+	.cmd1iclkout	= 0x00,
+
+	.cmd2csratio	= 0x80,
+	.cmd2dldiff	= 0x04,
+	.cmd2iclkout	= 0x00,
+};
+
+static const struct emif_regs evm_ddr2_emif0_regs = {
+	.sdram_config			= 0x40801ab2,
+	.ref_ctrl			= 0x10000c30,
+	.sdram_tim1			= 0x0aaaf552,
+	.sdram_tim2			= 0x043631d2,
+	.sdram_tim3			= 0x00000327,
+	.emif_ddr_phy_ctlr_1		= 0x00000007
+};
+
+static const struct emif_regs evm_ddr2_emif1_regs = {
+	.sdram_config			= 0x40801ab2,
+	.ref_ctrl			= 0x10000c30,
+	.sdram_tim1			= 0x0aaaf552,
+	.sdram_tim2			= 0x043631d2,
+	.sdram_tim3			= 0x00000327,
+	.emif_ddr_phy_ctlr_1		= 0x00000007
+};
+
+const struct dmm_lisa_map_regs evm_lisa_map_regs = {
+	.dmm_lisa_map_0			= 0x00000000,
+	.dmm_lisa_map_1			= 0x00000000,
+	.dmm_lisa_map_2			= 0x806c0300,
+	.dmm_lisa_map_3			= 0x806c0300,
+};
+
+static const struct ddr_data evm_ddr2_data = {
+	.datardsratio0		= ((0x35<<10) | (0x35<<0)),
+	.datawdsratio0		= ((0x20<<10) | (0x20<<0)),
+	.datawiratio0		= ((0<<10) | (0<<0)),
+	.datagiratio0		= ((0<<10) | (0<<0)),
+	.datafwsratio0		= ((0x90<<10) | (0x90<<0)),
+	.datawrsratio0		= ((0x50<<10) | (0x50<<0)),
+	.datauserank0delay	= 1,
+	.datadldiff0		= 0x4,
+};
+#endif
+
+/*
+ * early system init of muxing and clocks.
+ */
+void s_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	/* WDT1 is already running when the bootloader gets control
+	 * Disable it to avoid "random" resets
+	 */
+	wdt_disable();
+
+	/* Setup the PLLs and the clocks for the peripherals */
+	pll_init();
+
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+
+	/* Set UART pins */
+	enable_uart0_pin_mux();
+
+	/* Set MMC pins */
+	enable_mmc1_pin_mux();
+
+	/* Enable UART */
+	uart_enable();
+
+	gd = &gdata;
+
+	preloader_console_init();
+
+	config_dmm(&evm_lisa_map_regs);
+
+	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+		   &evm_ddr2_emif0_regs, 0);
+	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+		   &evm_ddr2_emif1_regs, 1);
+#endif
+}
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+	return 0;
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(1, 0, 0, -1, -1);
+
+	return 0;
+}
+#endif
diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h
new file mode 100644
index 0000000000..40f8710c89
--- /dev/null
+++ b/board/ti/ti814x/evm.h
@@ -0,0 +1,7 @@
+#ifndef _EVM_H
+#define _EVM_H
+
+void enable_uart0_pin_mux(void);
+void enable_mmc1_pin_mux(void);
+
+#endif /* _EVM_H */
diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c
new file mode 100644
index 0000000000..137acb4523
--- /dev/null
+++ b/board/ti/ti814x/mux.c
@@ -0,0 +1,51 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "evm.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(pincntl70), PULLUP_EN | MODE(0x01)},	/* UART0_RXD */
+	{OFFSET(pincntl71), PULLUP_EN | MODE(0x01)},	/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(pincntl1), PULLUP_EN | MODE(0x01)},	/* SD1_CLK */
+	{OFFSET(pincntl2), PULLUP_EN | MODE(0x01)},	/* SD1_CMD */
+	{OFFSET(pincntl3), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[0] */
+	{OFFSET(pincntl4), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[1] */
+	{OFFSET(pincntl5), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[2] */
+	{OFFSET(pincntl6), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[3] */
+	{OFFSET(pincntl74), PULLUP_EN | MODE(0x40)},	/* SD1_POW */
+	{OFFSET(pincntl75), MODE(0x40)},		/* SD1_SDWP */
+	{OFFSET(pincntl80), PULLUP_EN | MODE(0x02)},	/* SD1_SDCD */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_mmc1_pin_mux(void)
+{
+	configure_module_pin_mux(mmc1_pin_mux);
+}