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-rw-r--r--board/ti/am335x/Makefile2
-rw-r--r--board/ti/am335x/README160
-rw-r--r--board/ti/am335x/board.c167
-rw-r--r--board/ti/am335x/board.h31
-rw-r--r--board/ti/am335x/mux.c84
-rw-r--r--board/ti/am335x/u-boot.lds117
-rw-r--r--board/ti/am43xx/Makefile38
-rw-r--r--board/ti/am43xx/board.c57
-rw-r--r--board/ti/am43xx/board.h17
-rw-r--r--board/ti/am43xx/mux.c27
-rw-r--r--board/ti/beagle/beagle.c28
-rw-r--r--board/ti/beagle/beagle.h3
-rw-r--r--board/ti/dra7xx/evm.c150
-rw-r--r--board/ti/dra7xx/mux_data.h14
-rw-r--r--board/ti/omap5_uevm/evm.c118
-rw-r--r--board/ti/omap5_uevm/mux_data.h6
-rw-r--r--board/ti/ti814x/evm.c68
-rw-r--r--board/ti/ti816x/Makefile37
-rw-r--r--board/ti/ti816x/evm.c229
19 files changed, 1168 insertions, 185 deletions
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
index cb2b999025..3dbeedab1a 100644
--- a/board/ti/am335x/Makefile
+++ b/board/ti/am335x/Makefile
@@ -10,7 +10,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
COBJS := mux.o
endif
diff --git a/board/ti/am335x/README b/board/ti/am335x/README
new file mode 100644
index 0000000000..67b524673a
--- /dev/null
+++ b/board/ti/am335x/README
@@ -0,0 +1,160 @@
+Summary
+=======
+
+This document covers various features of the 'am335x_evm' build, and some of
+the related build targets (am335x_evm_uartN, etc).
+
+Hardware
+========
+
+The binary produced by this board supports, based on parsing of the EEPROM
+documented in TI's reference designs:
+- AM335x GP EVM
+- AM335x EVM SK
+- Beaglebone White
+- Beaglebone Black
+'
+NAND
+====
+
+The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In
+this example to program the NAND we assume that an SD card has been
+inserted with the files to write in the first SD slot and that mtdparts
+have been configured correctly for the board. As a time saving measure we
+load MLO into memory in one location, copy it into the three locatations
+that the ROM checks for additional valid copies, then load U-Boot into
+memory. We then write that whole section of memory to NAND.
+
+U-Boot # mmc rescan
+U-Boot # env default -f -a
+U-Boot # nand erase.chip
+U-Boot # saveenv
+U-Boot # load mmc 0 81000000 MLO
+U-Boot # cp.b 81000000 81020000 20000
+U-Boot # cp.b 81000000 81040000 20000
+U-Boot # cp.b 81000000 81060000 20000
+U-Boot # load mmc 0 81080000 u-boot.img
+U-Boot # nand write 81000000 0 260000
+U-Boot # load mmc 0 ${loadaddr} uImage
+U-Boot # nand write ${loadaddr} kernel 500000
+
+NOR
+===
+
+The Beaglebone White can be equiped with a "memory cape" that in turn can
+have a NOR module plugged into it. In this case it is then possible to
+program and boot from NOR. Note that due to how U-Boot is architectured we
+must build a specific version of U-Boot that knows we have NOR flash. This
+build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot'
+build that will assume that the environment is on NOR rather than NAND. In
+the following example we assume that and SD card has been populated with
+MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the
+'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a
+binary must be written to the start of NOR, with no header or similar
+prepended. In the following example we use a size of 512KiB (0x80000)
+as that is how much space we set aside before the environment, as per
+the config file.
+
+U-Boot # mmc rescan
+U-Boot # load mmc 0 ${loadaddr} u-boot.bin
+U-Boot # protect off 08000000 +80000
+U-Boot # erase 08000000 +80000
+U-Boot # cp.b ${loadaddr} 08000000 ${filesize}
+
+Falcon Mode
+===========
+
+The default build includes "Falcon Mode" (see doc/README.falcon) via NAND,
+eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is
+to read a 'c' on the console while in SPL at any point prior to loading the
+OS payload (so as soon as possible) to opt to booting full U-Boot. Also
+note that while one can program Falcon Mode "in place" great care needs to
+be taken by the user to not 'brick' their setup. As these are all eval
+boards with multiple boot methods, recovery should not be an issue in this
+worst-case however.
+
+Falcon Mode: eMMC
+=================
+
+The recommended layout in this case is:
+
+MMC BLOCKS |--------------------------------| LOCATION IN BYTES
+0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000
+0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000
+0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000
+0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000
+0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000
+0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000
+0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000
+
+Note that when we run 'spl export' it will prepare to boot the kernel.
+This includes relocation of the uImage from where we loaded it to the entry
+point defined in the header. As these locations overlap by default, it
+would leave us with an image that if written to MMC will not boot, so
+instead of using the loadaddr variable we use 0x81000000 in the following
+example. In this example we are loading from the network, for simplicity,
+and assume a valid partition table already exists and 'mmc dev' has already
+been run to select the correct device. Also note that if you previously
+had a FAT partition (such as on a Beaglebone Black) it is not enough to
+write garbage into the area, you must delete it from the partition table
+first.
+
+# Ensure we are able to talk with this mmc device
+U-Boot # mmc rescan
+U-Boot # tftp 81000000 am335x/MLO
+# Write to two of the backup locations ROM uses
+U-Boot # mmc write 81000000 100 100
+U-Boot # mmc write 81000000 200 100
+# Write U-Boot to the location set in the config
+U-Boot # tftp 81000000 am335x/u-boot.img
+U-Boot # mmc write 81000000 300 400
+# Load kernel and device tree into memory, perform export
+U-Boot # tftp 81000000 am335x/uImage
+U-Boot # run findfdt
+U-Boot # tftp ${fdtaddr} am335x/${fdtfile}
+U-Boot # run mmcargs
+U-Boot # spl export fdt 81000000 - ${fdtaddr}
+# Write the updated device tree to MMC
+U-Boot # mmc write ${fdtaddr} 80 80
+# Write the uImage to MMC
+U-Boot # mmc write 81000000 900 2000
+
+Falcon Mode: FAT SD cards
+=========================
+
+In this case the additional file is written to the filesystem. In this
+example we assume that the uImage and device tree to be used are already on
+the FAT filesystem (only the uImage MUST be for this to function
+afterwards) along with a Falcon Mode aware MLO and the FAT partition has
+already been created and marked bootable:
+
+U-Boot # mmc rescan
+# Load kernel and device tree into memory, perform export
+U-Boot # load mmc 0:1 ${loadaddr} uImage
+U-Boot # run findfdt
+U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile}
+U-Boot # run mmcargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+
+This will print a number of lines and then end with something like:
+ Using Device Tree in place at 80f80000, end 80f85928
+ Using Device Tree in place at 80f80000, end 80f88928
+So then you:
+
+U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928
+
+Falcon Mode: NAND
+=================
+
+In this case the additional data is written to another partition of the
+NAND. In this example we assume that the uImage and device tree to be are
+already located on the NAND somewhere (such as fileystem or mtd partition)
+along with a Falcon Mode aware MLO written to the correct locations for
+booting and mtdparts have been configured correctly for the board:
+
+U-Boot # nand read ${loadaddr} kernel
+U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
+U-Boot # run nandargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+U-Boot # nand erase.part u-boot-spl-os
+U-Boot # nand write ${fdtaddr} u-boot-spl-os
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 7138d739e4..04c37e2db6 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -19,6 +19,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
@@ -29,8 +30,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
#define RGMII_MODE_ENABLE 0x3A
@@ -40,43 +39,10 @@ static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-static struct am335x_baseboard_id __attribute__((section (".data"))) header;
-
-static inline int board_is_bone(void)
-{
- return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
-}
-
-static inline int board_is_bone_lt(void)
-{
- return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_sk(void)
-{
- return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
-}
-
-static inline int board_is_idk(void)
-{
- return !strncmp(header.config, "SKU#02", 6);
-}
-
-static int __maybe_unused board_is_gp_evm(void)
-{
- return !strncmp("A33515BB", header.name, 8);
-}
-
-int board_is_evm_15_or_later(void)
-{
- return (!strncmp("A33515BB", header.name, 8) &&
- strncmp("1.5", header.version, 3) <= 0);
-}
-
/*
* Read header information from EEPROM into global structure.
*/
-static int read_eeprom(void)
+static int read_eeprom(struct am335x_baseboard_id *header)
{
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
@@ -86,28 +52,28 @@ static int read_eeprom(void)
}
/* read the eeprom using i2c */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
- sizeof(header))) {
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
+ sizeof(struct am335x_baseboard_id))) {
puts("Could not read the EEPROM; something fundamentally"
" wrong on the I2C bus.\n");
return -EIO;
}
- if (header.magic != 0xEE3355AA) {
+ if (header->magic != 0xEE3355AA) {
/*
* read the eeprom using i2c again,
* but use only a 1 byte address
*/
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
- (uchar *)&header, sizeof(header))) {
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+ sizeof(struct am335x_baseboard_id))) {
puts("Could not read the EEPROM; something "
"fundamentally wrong on the I2C bus.\n");
return -EIO;
}
- if (header.magic != 0xEE3355AA) {
+ if (header->magic != 0xEE3355AA) {
printf("Incorrect magic number (0x%x) in EEPROM\n",
- header.magic);
+ header->magic);
return -EINVAL;
}
}
@@ -115,7 +81,7 @@ static int read_eeprom(void)
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
(MT47H128M16RT25E_RD_DQS<<20) |
@@ -274,39 +240,35 @@ int spl_start_uboot(void)
}
#endif
-#endif
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+ 266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+ 303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_bone_black = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
+const struct dpll_params *get_dpll_ddr_params(void)
{
- /*
- * Save the boot parameters passed from romcode.
- * We cannot delay the saving further than this,
- * to prevent overwrites.
- */
-#ifdef CONFIG_SPL_BUILD
- save_omap_boot_params();
-#endif
-
- /* WDT1 is already running when the bootloader gets control
- * Disable it to avoid "random" resets
- */
- writel(0xAAAA, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
- writel(0x5555, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
+ struct am335x_baseboard_id header;
-#ifdef CONFIG_SPL_BUILD
- /* Setup the PLLs and the clocks for the peripherals */
- pll_init();
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
- /* Enable RTC32K clock */
- rtc32k_enable();
+ if (board_is_evm_sk(&header))
+ return &dpll_ddr_evm_sk;
+ else if (board_is_bone_lt(&header))
+ return &dpll_ddr_bone_black;
+ else if (board_is_evm_15_or_later(&header))
+ return &dpll_ddr_evm_sk;
+ else
+ return &dpll_ddr;
+}
+void set_uart_mux_conf(void)
+{
#ifdef CONFIG_SERIAL1
enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
@@ -325,21 +287,26 @@ void s_init(void)
#ifdef CONFIG_SERIAL6
enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */
+}
- uart_soft_reset();
+void set_mux_conf_regs(void)
+{
+ __maybe_unused struct am335x_baseboard_id header;
- gd = &gdata;
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
- preloader_console_init();
+ enable_board_pin_mux(&header);
+}
- /* Initalize the board header */
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- if (read_eeprom() < 0)
+void sdram_init(void)
+{
+ __maybe_unused struct am335x_baseboard_id header;
+
+ if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
- enable_board_pin_mux(&header);
- if (board_is_evm_sk()) {
+ if (board_is_evm_sk(&header)) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
@@ -348,36 +315,44 @@ void s_init(void)
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
- if (board_is_evm_sk())
+ if (board_is_evm_sk(&header))
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
- else if (board_is_bone_lt())
+ else if (board_is_bone_lt(&header))
config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
- else if (board_is_evm_15_or_later())
+ else if (board_is_evm_15_or_later(&header))
config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
else
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
-#endif
}
+#endif
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- if (read_eeprom() < 0)
- puts("Could not get board ID.\n");
+#ifdef CONFIG_NOR
+ const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
+ STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
+ STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
+#endif
- gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
+#ifdef CONFIG_NOR
+ /* Reconfigure CS0 for NOR instead of NAND. */
+ enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
+ CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
+#endif
+
return 0;
}
@@ -386,6 +361,10 @@ int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
char safe_string[HDR_NAME_LEN + 1];
+ struct am335x_baseboard_id header;
+
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
/* Now set variables based on the header. */
strncpy(safe_string, (char *)header.name, sizeof(header.name));
@@ -435,6 +414,7 @@ static struct cpsw_platform_data cpsw_data = {
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
@@ -449,6 +429,7 @@ int board_eth_init(bd_t *bis)
int rv, n = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
+ __maybe_unused struct am335x_baseboard_id header;
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
@@ -470,7 +451,11 @@ int board_eth_init(bd_t *bis)
}
#ifdef CONFIG_DRIVER_TI_CPSW
- if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ if (board_is_bone(&header) || board_is_bone_lt(&header) ||
+ board_is_idk(&header)) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
@@ -499,7 +484,7 @@ int board_eth_init(bd_t *bis)
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
#define AR8051_RGMII_TX_CLK_DLY 0x100
- if (board_is_evm_sk() || board_is_gp_evm()) {
+ if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
const char *devname;
devname = miiphy_get_current_dev();
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index 9fea1f15a6..bc700d56fe 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -29,6 +29,37 @@ struct am335x_baseboard_id {
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
};
+static inline int board_is_bone(struct am335x_baseboard_id *header)
+{
+ return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
+}
+
+static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
+{
+ return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
+{
+ return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
+}
+
+static inline int board_is_idk(struct am335x_baseboard_id *header)
+{
+ return !strncmp(header->config, "SKU#02", 6);
+}
+
+static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
+{
+ return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
+{
+ return (board_is_gp_evm(header) &&
+ strncmp("1.5", header->version, 3) <= 0);
+}
+
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 02837082cb..b2bfda5ea9 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -190,6 +190,75 @@ static struct module_pin_mux nand_pin_mux[] = {
{-1},
};
+#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+static struct module_pin_mux bone_norcape_pin_mux[] = {
+ {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
+ {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */
+ {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */
+ {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */
+ {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */
+ {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */
+ {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */
+ {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */
+ {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */
+ {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */
+ {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */
+ {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
+ {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */
+ {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */
+ {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */
+ {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */
+ {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */
+ {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */
+ {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */
+ {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */
+ {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */
+ {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */
+ {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */
+ {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */
+ {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */
+ {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */
+ {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */
+ {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */
+ {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */
+ {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */
+ {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */
+ {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */
+ {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */
+ {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */
+ {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */
+ {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */
+
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
+ {-1},
+};
+#endif
+
+#if defined(CONFIG_NOR_BOOT)
+static struct module_pin_mux norboot_pin_mux[] = {
+ {OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
+ {OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
+ {-1},
+};
+
+void enable_norboot_pin_mux(void)
+{
+ configure_module_pin_mux(norboot_pin_mux);
+}
+#endif
+
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
@@ -262,13 +331,18 @@ static unsigned short detect_daughter_board_profile(void)
void enable_board_pin_mux(struct am335x_baseboard_id *header)
{
/* Do board-specific muxes. */
- if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) {
+ if (board_is_bone(header)) {
/* Beaglebone pinmux */
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
+#ifndef CONFIG_NOR
configure_module_pin_mux(mmc1_pin_mux);
- } else if (!strncmp(header->config, "SKU#01", 6)) {
+#endif
+#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+ configure_module_pin_mux(bone_norcape_pin_mux);
+#endif
+ } else if (board_is_gp_evm(header)) {
/* General Purpose EVM */
unsigned short profile = detect_daughter_board_profile();
configure_module_pin_mux(rgmii1_pin_mux);
@@ -283,7 +357,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
configure_module_pin_mux(mmc1_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
}
- } else if (!strncmp(header->config, "SKU#02", 6)) {
+ } else if (board_is_idk(header)) {
/*
* Industrial Motor Control (IDK)
* note: IDK console is on UART3 by default.
@@ -292,13 +366,13 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
*/
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_no_cd_pin_mux);
- } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
+ } else if (board_is_evm_sk(header)) {
/* Starter Kit EVM */
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(gpio0_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux_sk_evm);
- } else if (!strncmp(header->name, "A335BNLT", HDR_NAME_LEN)) {
+ } else if (board_is_bone_lt(header)) {
/* Beaglebone LT pinmux */
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
new file mode 100644
index 0000000000..a173f620ef
--- /dev/null
+++ b/board/ti/am335x/u-boot.lds
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ CPUDIR/start.o (.text*)
+ board/ti/am335x/libam335x.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ _end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
new file mode 100644
index 0000000000..4a1bb7c47f
--- /dev/null
+++ b/board/ti/am43xx/Makefile
@@ -0,0 +1,38 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS := mux.o
+endif
+
+COBJS += board.o
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
new file mode 100644
index 0000000000..51b257683d
--- /dev/null
+++ b/board/ti/am43xx/board.c
@@ -0,0 +1,57 @@
+/*
+ * board.c
+ *
+ * Board functions for TI AM43XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+
+const struct dpll_params dpll_ddr = {
+ -1, -1, -1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr;
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+}
+#endif
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ return 0;
+}
+#endif
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
new file mode 100644
index 0000000000..8ca098b82a
--- /dev/null
+++ b/board/ti/am43xx/board.h
@@ -0,0 +1,17 @@
+/*
+ * board.h
+ *
+ * TI AM437x boards information header
+ * Derived from AM335x board.
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
new file mode 100644
index 0000000000..700e9a76ad
--- /dev/null
+++ b/board/ti/am43xx/mux.c
@@ -0,0 +1,27 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+}
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 36f73457ac..62e9beaef3 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -166,8 +166,7 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
}
- case REVISION_XM_A:
- case REVISION_XM_B:
+ case REVISION_XM_AB:
case REVISION_XM_C:
if (pop_mfr == 0) {
/* 256MB DDR */
@@ -240,8 +239,7 @@ static void beagle_display_init(void)
case REVISION_C4:
omap3_dss_panel_config(&dvid_cfg);
break;
- case REVISION_XM_A:
- case REVISION_XM_B:
+ case REVISION_XM_AB:
case REVISION_XM_C:
default:
omap3_dss_panel_config(&dvid_cfg_xm);
@@ -260,12 +258,11 @@ static void beagle_dvi_pup(void)
case REVISION_AXBX:
case REVISION_CX:
case REVISION_C4:
- case REVISION_XM_A:
gpio_request(170, "");
gpio_direction_output(170, 0);
gpio_set_value(170, 1);
break;
- case REVISION_XM_B:
+ case REVISION_XM_AB:
case REVISION_XM_C:
default:
#define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3)
@@ -343,19 +340,9 @@ int misc_init_r(void)
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
break;
- case REVISION_XM_A:
- printf("Beagle xM Rev A\n");
- setenv("beaglerev", "xMA");
- MUX_BEAGLE_XM();
- /* Set VAUX2 to 1.8V for EHCI PHY */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
- TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
- TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
- break;
- case REVISION_XM_B:
- printf("Beagle xM Rev B\n");
- setenv("beaglerev", "xMB");
+ case REVISION_XM_AB:
+ printf("Beagle xM Rev A/B\n");
+ setenv("beaglerev", "xMAB");
MUX_BEAGLE_XM();
/* Set VAUX2 to 1.8V for EHCI PHY */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
@@ -468,8 +455,7 @@ int misc_init_r(void)
twl4030_power_init();
switch (get_board_revision()) {
- case REVISION_XM_A:
- case REVISION_XM_B:
+ case REVISION_XM_AB:
twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
break;
default:
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
index 76be3589e0..6dd2ffe558 100644
--- a/board/ti/beagle/beagle.h
+++ b/board/ti/beagle/beagle.h
@@ -23,8 +23,7 @@ const omap3_sysinfo sysinfo = {
#define REVISION_AXBX 0x7
#define REVISION_CX 0x6
#define REVISION_C4 0x5
-#define REVISION_XM_A 0x0
-#define REVISION_XM_B 0x1
+#define REVISION_XM_AB 0x0
#define REVISION_XM_C 0x2
/*
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 8190e4bafb..9a114e2a75 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -23,12 +23,53 @@
#include <asm/ehci-omap.h>
#endif
+#ifdef CONFIG_DRIVER_TI_CPSW
+#include <cpsw.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
"Board: DRA7xx\n"
};
+/*
+ * Adjust I/O delays on the Tx control and data lines of each MAC port. This
+ * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
+ * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
+ * essentially need to counteract the DRA7xx internal delay, and we do this
+ * by delaying the control and data lines. If not using this PHY, you probably
+ * don't need to do this stuff!
+ */
+static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
+{
+ int i = 0;
+ u32 reg_val;
+ u32 delta;
+ u32 coarse;
+ u32 fine;
+
+ writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
+
+ while(io_dly[i].addr) {
+ writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
+ io_dly[i].addr);
+ delta = io_dly[i].dly;
+ reg_val = readl(io_dly[i].addr) & 0x3ff;
+ coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
+ coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
+ fine = (reg_val & 0x1F) + (delta & 0x1F);
+ fine = (fine > 0x1F) ? (0x1F) : (fine);
+ reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
+ CFG_IO_DELAY_LOCK_MASK |
+ ((coarse << 5) | (fine));
+ writel(reg_val, io_dly[i].addr);
+ i++;
+ }
+
+ writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
+}
+
/**
* @brief board_init
*
@@ -42,11 +83,6 @@ int board_init(void)
return 0;
}
-int board_eth_init(bd_t *bis)
-{
- return 0;
-}
-
/**
* @brief misc_init_r - Configure EVM board specific configurations
* such as power configurations, ethernet initialization as phase2 of
@@ -85,3 +121,107 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+/* Delay value to add to calibrated value */
+#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
+#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
+#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
+#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
+
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_id = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+ uint32_t ctrl_val;
+ const struct io_delay io_dly[] = {
+ {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
+ {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
+ {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
+ {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
+ {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
+ {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
+ {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
+ {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
+ {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
+ {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
+ {0}
+ };
+
+ /* Adjust IO delay for RGMII tx path */
+ dra7xx_adj_io_delay(io_dly);
+
+ /* try reading mac address from efuse */
+ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = mac_lo & 0xFF;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = (mac_lo & 0xFF0000) >> 16;
+
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+ ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
+ ctrl_val |= 0x22;
+ writel(ctrl_val, (*ctrl)->control_core_control_io1);
+
+ ret = cpsw_register(&cpsw_data);
+ if (ret < 0)
+ printf("Error %d registering CPSW switch\n", ret);
+
+ return ret;
+}
+#endif
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index ec8342276b..0a86594c6b 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -37,5 +37,19 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
{I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
+ {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
+ {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
+ {RGMII0_TXC, (M0) },
+ {RGMII0_TXCTL, (M0) },
+ {RGMII0_TXD3, (M0) },
+ {RGMII0_TXD2, (M0) },
+ {RGMII0_TXD1, (M0) },
+ {RGMII0_TXD0, (M0) },
+ {RGMII0_RXC, (IEN | M0) },
+ {RGMII0_RXCTL, (IEN | M0) },
+ {RGMII0_RXD3, (IEN | M0) },
+ {RGMII0_RXD2, (IEN | M0) },
+ {RGMII0_RXD1, (IEN | M0) },
+ {RGMII0_RXD0, (IEN | M0) },
};
#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index ea83e6c3e7..47063309e5 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -10,13 +10,45 @@
#include <palmas.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
+#include <tca642x.h>
#include "mux_data.h"
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ehci.h>
+#include <asm/ehci-omap.h>
+
+#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
+#define DIE_ID_REG_OFFSET 0x200
+
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
- "Board: OMAP5430 EVM\n"
+ "Board: OMAP5432 uEVM\n"
+};
+
+/**
+ * @brief tca642x_init - uEVM default values for the GPIO expander
+ * input reg, output reg, polarity reg, configuration reg
+ */
+struct tca642x_bank_info tca642x_init[] = {
+ { .input_reg = 0x00,
+ .output_reg = 0x04,
+ .polarity_reg = 0x00,
+ .configuration_reg = 0x80 },
+ { .input_reg = 0x00,
+ .output_reg = 0x00,
+ .polarity_reg = 0x00,
+ .configuration_reg = 0xff },
+ { .input_reg = 0x00,
+ .output_reg = 0x00,
+ .polarity_reg = 0x00,
+ .configuration_reg = 0x40 },
};
/**
@@ -30,6 +62,8 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+ tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
+
return 0;
}
@@ -87,3 +121,85 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#endif
+
+#ifdef CONFIG_USB_EHCI
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
+ .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
+};
+
+static void enable_host_clocks(void)
+{
+ int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
+ OPTFCLKEN_HSIC480M_P3_CLK |
+ OPTFCLKEN_HSIC60M_P2_CLK |
+ OPTFCLKEN_HSIC480M_P2_CLK |
+ OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
+
+ /* Enable port 2 and 3 clocks*/
+ setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
+
+ /* Enable port 2 and 3 usb host ports tll clocks*/
+ setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
+ (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
+}
+
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ int ret;
+ int auxclk;
+ int reg;
+ uint8_t device_mac[6];
+
+ enable_host_clocks();
+
+ if (!getenv("usbethaddr")) {
+ reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
+
+ /*
+ * create a fake MAC address from the processor ID code.
+ * first byte is 0x02 to signify locally administered.
+ */
+ device_mac[0] = 0x02;
+ device_mac[1] = readl(reg + 0x10) & 0xff;
+ device_mac[2] = readl(reg + 0xC) & 0xff;
+ device_mac[3] = readl(reg + 0x8) & 0xff;
+ device_mac[4] = readl(reg) & 0xff;
+ device_mac[5] = (readl(reg) >> 8) & 0xff;
+
+ eth_setenv_enetaddr("usbethaddr", device_mac);
+ }
+
+ auxclk = readl((*prcm)->scrm_auxclk1);
+ /* Request auxilary clock */
+ auxclk |= AUXCLK_ENABLE_MASK;
+ writel(auxclk, (*prcm)->scrm_auxclk1);
+
+ ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+ if (ret < 0) {
+ puts("Failed to initialize ehci\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+ int ret;
+
+ ret = omap_ehci_hcd_stop();
+ return ret;
+}
+
+void usb_hub_reset_devices(int port)
+{
+ /* The LAN9730 needs to be reset after the port power has been set. */
+ if (port == 3) {
+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
+ udelay(10);
+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
+ }
+}
+#endif
diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h
index 36b723e6cc..31ce363b63 100644
--- a/board/ti/omap5_uevm/mux_data.h
+++ b/board/ti/omap5_uevm/mux_data.h
@@ -40,7 +40,10 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */
{USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */
{USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
-
+ {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
+ {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
+ {HSI2_ACWAKE, (PTU | M6)}, /* HSI2_ACWAKE */
+ {HSI2_CAFLAG, (PTU | M6)}, /* HSI2_CAFLAG */
};
const struct pad_conf_entry wkup_padconf_array_essential[] = {
@@ -48,6 +51,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = {
{SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
{SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
{SYS_32K, (IEN | M0)}, /* SYS_32K */
+ {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */
};
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 17fba5aecd..e406326a11 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -27,30 +27,10 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SPL_BUILD
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#endif
-
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
/* UART Defines */
#ifdef CONFIG_SPL_BUILD
-static void uart_enable(void)
-{
- /* UART softreset */
- uart_soft_reset();
-}
-
-static void wdt_disable(void)
-{
- writel(0xAAAA, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
- writel(0x5555, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
-}
-
static const struct cmd_control evm_ddr2_cctrl_data = {
.cmd0csratio = 0x80,
.cmd0dldiff = 0x04,
@@ -100,68 +80,39 @@ static const struct ddr_data evm_ddr2_data = {
.datauserank0delay = 1,
.datadldiff0 = 0x4,
};
-#endif
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
+void set_uart_mux_conf(void)
{
-#ifdef CONFIG_SPL_BUILD
- /*
- * Save the boot parameters passed from romcode.
- * We cannot delay the saving further than this,
- * to prevent overwrites.
- */
-#ifdef CONFIG_SPL_BUILD
- save_omap_boot_params();
-#endif
-
- /* WDT1 is already running when the bootloader gets control
- * Disable it to avoid "random" resets
- */
- wdt_disable();
-
- /* Enable timer */
- timer_init();
-
- /* Setup the PLLs and the clocks for the peripherals */
- pll_init();
-
- /* Enable RTC32K clock */
- rtc32k_enable();
-
/* Set UART pins */
enable_uart0_pin_mux();
+}
+void set_mux_conf_regs(void)
+{
/* Set MMC pins */
enable_mmc1_pin_mux();
/* Set Ethernet pins */
enable_enet_pin_mux();
+}
- /* Enable UART */
- uart_enable();
-
- gd = &gdata;
-
- preloader_console_init();
-
+void sdram_init(void)
+{
config_dmm(&evm_lisa_map_regs);
config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif0_regs, 0);
config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif1_regs, 1);
-#endif
}
+#endif
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
- gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
@@ -207,6 +158,7 @@ static struct cpsw_platform_data cpsw_data = {
.ale_entries = 1024,
.host_port_reg_ofs = 0x28,
.hw_stats_reg_ofs = 0x400,
+ .bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
new file mode 100644
index 0000000000..17ce72a3cc
--- /dev/null
+++ b/board/ti/ti816x/Makefile
@@ -0,0 +1,37 @@
+#
+# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+# Antoine Tenart, <atenart@adeneo-embedded.com>
+#
+# Based on TI-PSP-04.00.02.14 :
+#
+# Copyright (C) 2009, Texas Instruments, Incorporated
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := evm.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
new file mode 100644
index 0000000000..74d35e936d
--- /dev/null
+++ b/board/ti/ti816x/evm.c
@@ -0,0 +1,229 @@
+/*
+ * evm.c
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+
+static struct module_pin_mux mmc_pin_mux[] = {
+ { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
+ { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { -1 },
+};
+
+const struct dmm_lisa_map_regs evm_lisa_map_regs = {
+ .dmm_lisa_map_0 = 0x00000000,
+ .dmm_lisa_map_1 = 0x00000000,
+ .dmm_lisa_map_2 = 0x80640300,
+ .dmm_lisa_map_3 = 0xC0640320,
+};
+
+/*
+ * DDR2 related definitions
+ */
+#ifdef CONFIG_TI816X_EVM_DDR2
+static struct ddr_data ddr2_data = {
+ .datardsratio0 = ((0x40<<10) | (0x40<<0)),
+ .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)),
+ .datawiratio0 = ((0x0<<10) | (0x0<<0)),
+ .datagiratio0 = ((0x0<<10) | (0x0<<0)),
+ .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)),
+ .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)),
+ .datauserank0delay = 0x1,
+ .datadldiff0 = 0x0, /* depend on cpu rev, set later */
+};
+
+static struct cmd_control ddr2_ctrl = {
+ .cmd0csratio = 0x80,
+ .cmd0dldiff = 0x04, /* reset value is 0x4 */
+ .cmd0iclkout = 0x00,
+
+ .cmd1csratio = 0x80,
+ .cmd1dldiff = 0x04, /* reset value is 0x4 */
+ .cmd1iclkout = 0x00,
+
+ .cmd2csratio = 0x80,
+ .cmd2dldiff = 0x04, /* reset value is 0x4 */
+ .cmd2iclkout = 0x00,
+
+};
+
+static struct emif_regs ddr2_emif0_regs = {
+ .sdram_config = 0x43801A3A,
+ .ref_ctrl = 0x10000C30,
+ .sdram_tim1 = 0x0AAB15E2,
+ .sdram_tim2 = 0x423631D2,
+ .sdram_tim3 = 0x0080032F,
+ .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
+};
+
+static struct emif_regs ddr2_emif1_regs = {
+ .sdram_config = 0x43801A3A,
+ .ref_ctrl = 0x10000C30,
+ .sdram_tim1 = 0x0AAB15E2,
+ .sdram_tim2 = 0x423631D2,
+ .sdram_tim3 = 0x0080032F,
+ .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
+};
+#endif
+
+/*
+ * DDR3 related definitions
+ */
+
+#if defined(CONFIG_TI816X_DDR_PLL_400)
+#define RD_DQS 0x03B
+#define WR_DQS 0x0A6
+#define RD_DQS_GATE 0x12A
+#define EMIF_SDCFG 0x62A41032
+#define EMIF_SDREF 0x10000C30
+#define EMIF_TIM1 0x0CCCE524
+#define EMIF_TIM2 0x30308023
+#define EMIF_TIM3 0x009F82CF
+#define EMIF_PHYCFG 0x0000010B
+#elif defined(CONFIG_TI816X_DDR_PLL_531)
+#define RD_DQS 0x039
+#define WR_DQS 0x0B4
+#define RD_DQS_GATE 0x13D
+#define EMIF_SDCFG 0x62A51832
+#define EMIF_SDREF 0x1000102E
+#define EMIF_TIM1 0x0EF136AC
+#define EMIF_TIM2 0x30408063
+#define EMIF_TIM3 0x009F83AF
+#define EMIF_PHYCFG 0x0000010C
+#elif defined(CONFIG_TI816X_DDR_PLL_675)
+#define RD_DQS 0x039
+#define WR_DQS 0x091
+#define RD_DQS_GATE 0x196
+#define EMIF_SDCFG 0x62A63032
+#define EMIF_SDREF 0x10001491
+#define EMIF_TIM1 0x13358875
+#define EMIF_TIM2 0x5051806C
+#define EMIF_TIM3 0x009F84AF
+#define EMIF_PHYCFG 0x0000010F
+#elif defined(CONFIG_TI816X_DDR_PLL_796)
+#define RD_DQS 0x035
+#define WR_DQS 0x093
+#define RD_DQS_GATE 0x1B3
+#define EMIF_SDCFG 0x62A73832
+#define EMIF_SDREF 0x10001841
+#define EMIF_TIM1 0x1779C9FE
+#define EMIF_TIM2 0x50608074
+#define EMIF_TIM3 0x009F857F
+#define EMIF_PHYCFG 0x00000110
+#endif
+
+static struct ddr_data ddr3_data = {
+ .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
+ .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
+ .datawiratio0 = ((0x20<<10) | 0x20<<0),
+ .datagiratio0 = ((0x20<<10) | 0x20<<0),
+ .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
+ .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
+ .datauserank0delay = 0x1,
+ .datadldiff0 = 0x0, /* depend on cpu rev, set later */
+};
+
+static const struct cmd_control ddr3_ctrl = {
+ .cmd0csratio = 0x100,
+ .cmd0dldiff = 0x004, /* reset value is 0x4 */
+ .cmd0iclkout = 0x001,
+
+ .cmd1csratio = 0x100,
+ .cmd1dldiff = 0x004, /* reset value is 0x4 */
+ .cmd1iclkout = 0x001,
+
+ .cmd2csratio = 0x100,
+ .cmd2dldiff = 0x004, /* reset value is 0x4 */
+ .cmd2iclkout = 0x001,
+};
+
+static const struct emif_regs ddr3_emif0_regs = {
+ .sdram_config = EMIF_SDCFG,
+ .ref_ctrl = EMIF_SDREF,
+ .sdram_tim1 = EMIF_TIM1,
+ .sdram_tim2 = EMIF_TIM2,
+ .sdram_tim3 = EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
+};
+
+static const struct emif_regs ddr3_emif1_regs = {
+ .sdram_config = EMIF_SDCFG,
+ .ref_ctrl = EMIF_SDREF,
+ .sdram_tim1 = EMIF_TIM1,
+ .sdram_tim2 = EMIF_TIM2,
+ .sdram_tim3 = EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
+};
+
+void set_uart_mux_conf(void) {}
+
+void set_mux_conf_regs(void)
+{
+ configure_module_pin_mux(mmc_pin_mux);
+}
+
+void sdram_init(void)
+{
+ config_dmm(&evm_lisa_map_regs);
+
+#ifdef CONFIG_TI816X_EVM_DDR2
+ ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
+ ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
+ ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
+ ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
+
+ if (CONFIG_TI816X_USE_EMIF0) {
+ ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
+ (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
+ config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0);
+ }
+
+ if (CONFIG_TI816X_USE_EMIF1) {
+ ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
+ (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
+ config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1);
+ }
+#endif
+
+#ifdef CONFIG_TI816X_EVM_DDR3
+ ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
+
+ if (CONFIG_TI816X_USE_EMIF0)
+ config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
+
+ if (CONFIG_TI816X_USE_EMIF1)
+ config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1);
+#endif
+}
+#endif /* CONFIG_SPL_BUILD */
generated by cgit (git 2.34.1) at 2024-12-27 07:51:25 +0000