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-rw-r--r--board/ti/am57xx/board.c54
-rw-r--r--board/ti/dra7xx/evm.c109
-rw-r--r--board/ti/dra7xx/mux_data.h102
-rw-r--r--board/ti/ks2_evm/board.c2
4 files changed, 225 insertions, 42 deletions
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 67191af405..a5f02e6390 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -324,7 +324,6 @@ int board_init(void)
int board_late_init(void)
{
- init_sata(0);
setup_board_eeprom_env();
/*
@@ -537,12 +536,39 @@ static struct cpsw_platform_data cpsw_data = {
.version = CPSW_CTRL_VERSION_2,
};
+static u64 mac_to_u64(u8 mac[6])
+{
+ int i;
+ u64 addr = 0;
+
+ for (i = 0; i < 6; i++) {
+ addr <<= 8;
+ addr |= mac[i];
+ }
+
+ return addr;
+}
+
+static void u64_to_mac(u64 addr, u8 mac[6])
+{
+ mac[5] = addr;
+ mac[4] = addr >> 8;
+ mac[3] = addr >> 16;
+ mac[2] = addr >> 24;
+ mac[1] = addr >> 32;
+ mac[0] = addr >> 40;
+}
+
int board_eth_init(bd_t *bis)
{
int ret;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
uint32_t ctrl_val;
+ int i;
+ u64 mac1, mac2;
+ u8 mac_addr1[6], mac_addr2[6];
+ int num_macs;
/* try reading mac address from efuse */
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
@@ -583,6 +609,32 @@ int board_eth_init(bd_t *bis)
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
+ /*
+ * Export any Ethernet MAC addresses from EEPROM.
+ * On AM57xx the 2 MAC addresses define the address range
+ */
+ board_ti_get_eth_mac_addr(0, mac_addr1);
+ board_ti_get_eth_mac_addr(1, mac_addr2);
+
+ if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
+ mac1 = mac_to_u64(mac_addr1);
+ mac2 = mac_to_u64(mac_addr2);
+
+ /* must contain an address range */
+ num_macs = mac2 - mac1 + 1;
+ /* <= 50 to protect against user programming error */
+ if (num_macs > 0 && num_macs <= 50) {
+ for (i = 0; i < num_macs; i++) {
+ u64_to_mac(mac1 + i, mac_addr);
+ if (is_valid_ethaddr(mac_addr)) {
+ eth_setenv_enetaddr_by_index("eth",
+ i + 2,
+ mac_addr);
+ }
+ }
+ }
+ }
+
return ret;
}
#endif
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 4e45abfff7..9bd71d87ba 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -27,13 +27,17 @@
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>
+#include <miiphy.h>
#include "mux_data.h"
#include "../common/board_detect.h"
#define board_is_dra74x_evm() board_ti_is("5777xCPU")
+#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \
(strncmp("H", board_ti_get_rev(), 1) <= 0)
+#define board_is_dra72x_revc_or_later() board_is_dra72x_evm() && \
+ (strncmp("C", board_ti_get_rev(), 1) <= 0)
#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
board_ti_get_emif2_size()
@@ -127,6 +131,31 @@ static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
.emif_rd_wr_exec_thresh = 0x00000305
};
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
+ .sdram_config_init = 0x61862BB2,
+ .sdram_config = 0x61862BB2,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x0000514D,
+ .ref_ctrl_final = 0x0000144A,
+ .sdram_tim1 = 0xD1137824,
+ .sdram_tim2 = 0x30B37FE3,
+ .sdram_tim3 = 0x409F8AD8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0824400E,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400E,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
+ .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
+ .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
+ .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
@@ -203,7 +232,11 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
}
break;
case DRA722_ES1_0:
- *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+ case DRA722_ES2_0:
+ if (ram_size < CONFIG_MAX_MEM_MAPPED)
+ *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+ else
+ *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
break;
default:
*regs = &emif1_ddr3_532_mhz_1cs;
@@ -234,6 +267,18 @@ const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
.is_ma_present = 0x1
};
+/*
+ * DRA722 EVM EMIF1 2GB CONFIGURATION
+ * EMIF1 4 devices of 512Mb x 8 Micron
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x80700100,
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
u64 ram_size;
@@ -250,8 +295,13 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
*dmm_lisa_regs = &lisa_map_dra7_1536MB;
break;
case DRA722_ES1_0:
+ case DRA722_ES2_0:
default:
- *dmm_lisa_regs = &lisa_map_2G_x_2;
+ if (ram_size < CONFIG_MAX_MEM_MAPPED)
+ *dmm_lisa_regs = &lisa_map_2G_x_2;
+ else
+ *dmm_lisa_regs = &lisa_map_2G_x_4;
+ break;
}
}
@@ -324,8 +374,10 @@ void do_board_detect(void)
if (board_is_dra74x_evm()) {
bname = "DRA74x EVM";
- /* If EEPROM is not populated */
+ } else if (board_is_dra72x_evm()) {
+ bname = "DRA72x EVM";
} else {
+ /* If EEPROM is not populated */
if (is_dra72x())
bname = "DRA72x EVM";
else
@@ -347,16 +399,29 @@ void set_muxconf_regs(void)
#ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void)
{
- struct pad_conf_entry const *pads;
+ struct pad_conf_entry const *pads, *delta_pads = NULL;
struct iodelay_cfg_entry const *iodelay;
- int npads, niodelays;
+ int npads, niodelays, delta_npads = 0;
+ int ret;
switch (omap_revision()) {
case DRA722_ES1_0:
- pads = dra72x_core_padconf_array;
- npads = ARRAY_SIZE(dra72x_core_padconf_array);
- iodelay = dra72_iodelay_cfg_array;
- niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array);
+ case DRA722_ES2_0:
+ pads = dra72x_core_padconf_array_common;
+ npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
+ if (board_is_dra72x_revc_or_later()) {
+ delta_pads = dra72x_rgmii_padconf_array_revc;
+ delta_npads =
+ ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
+ iodelay = dra72_iodelay_cfg_array_revc;
+ niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
+ } else {
+ delta_pads = dra72x_rgmii_padconf_array_revb;
+ delta_npads =
+ ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
+ iodelay = dra72_iodelay_cfg_array_revb;
+ niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
+ }
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
@@ -376,7 +441,24 @@ void recalibrate_iodelay(void)
RGMII1_ID_MODE_N_MASK);
break;
}
- __recalibrate_iodelay(pads, npads, iodelay, niodelays);
+ /* Setup I/O isolation */
+ ret = __recalibrate_iodelay_start();
+ if (ret)
+ goto err;
+
+ /* Do the muxing here */
+ do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
+
+ /* Now do the weird minor deltas that should be safe */
+ if (delta_npads)
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ delta_pads, delta_npads);
+
+ /* Setup IOdelay configuration */
+ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+err:
+ /* Closeup.. remove isolation */
+ __recalibrate_iodelay_end(ret);
}
#endif
@@ -598,6 +680,11 @@ int board_eth_init(bd_t *bis)
if (*omap_si_rev == DRA722_ES1_0)
cpsw_data.active_slave = 1;
+ if (board_is_dra72x_revc_or_later()) {
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
+ }
+
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
@@ -614,7 +701,7 @@ static inline void vtt_regulator_enable(void)
return;
/* Do not enable VTT for DRA722 */
- if (omap_revision() == DRA722_ES1_0)
+ if (is_dra72x())
return;
/*
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 6db11a2bbb..34a05dd6bd 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -12,7 +12,7 @@
#include <asm/arch/mux_dra7xx.h>
-const struct pad_conf_entry dra72x_core_padconf_array[] = {
+const struct pad_conf_entry dra72x_core_padconf_array_common[] = {
{GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
{GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
{GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
@@ -104,37 +104,11 @@ const struct pad_conf_entry dra72x_core_padconf_array[] = {
{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
- {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */
{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
{GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
{GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
{GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
- {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */
- {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */
{MCASP1_AXR0, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr0.i2c5_sda */
{MCASP1_AXR1, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.i2c5_scl */
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
@@ -160,7 +134,6 @@ const struct pad_conf_entry dra72x_core_padconf_array[] = {
{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
- {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
@@ -188,6 +161,65 @@ const struct pad_conf_entry dra72x_core_padconf_array[] = {
{WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
};
+const struct pad_conf_entry dra72x_rgmii_padconf_array_revb[] = {
+ {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */
+ {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */
+ {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */
+};
+
+const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = {
+ {VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {VIN2A_D12, (M3 | PIN_OUTPUT)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d23.rgmii1_rxd0 */
+ {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
+};
+
const struct pad_conf_entry early_padconf[] = {
#if (CONFIG_CONS_INDEX == 1)
{UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
@@ -201,7 +233,7 @@ const struct pad_conf_entry early_padconf[] = {
};
#ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry dra72_iodelay_cfg_array[] = {
+const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revb[] = {
{0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
{0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
{0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
@@ -236,6 +268,18 @@ const struct iodelay_cfg_entry dra72_iodelay_cfg_array[] = {
{0x188, 0, 0}, /* CFG_GPMC_A18_OUT */
{0x374, 121, 0}, /* CFG_GPMC_CS2_OUT */
};
+
+const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revc[] = {
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
+ {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
+ {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+};
+
#endif
const struct pad_conf_entry dra74x_core_padconf_array[] = {
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index ca668a7c69..e16669da08 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -7,8 +7,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "board.h"
#include <common.h>
+#include "board.h"
#include <spl.h>
#include <exports.h>
#include <fdt_support.h>
generated by cgit (git 2.34.1) at 2025-01-13 08:53:04 +0000