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-rw-r--r--board/tqm85xx/Makefile50
-rw-r--r--board/tqm85xx/config.mk29
-rw-r--r--board/tqm85xx/law.c54
-rw-r--r--board/tqm85xx/sdram.c223
-rw-r--r--board/tqm85xx/tlb.c114
-rw-r--r--board/tqm85xx/tqm85xx.c419
-rw-r--r--board/tqm85xx/u-boot.lds147
7 files changed, 0 insertions, 1036 deletions
diff --git a/board/tqm85xx/Makefile b/board/tqm85xx/Makefile
deleted file mode 100644
index 52f5ef9454..0000000000
--- a/board/tqm85xx/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := $(BOARD).o sdram.o law.o tlb.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
- rm -f $(OBJS) $(SOBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/tqm85xx/config.mk b/board/tqm85xx/config.mk
deleted file mode 100644
index 52e84ad772..0000000000
--- a/board/tqm85xx/config.mk
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright 2004 Freescale Semiconductor.
-# Modified by Xianghua Xiao, X.Xiao@motorola.com
-# (C) Copyright 2002,Motorola Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# tqm85xx board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 256k
-#
-TEXT_BASE = 0xfffc0000
diff --git a/board/tqm85xx/law.c b/board/tqm85xx/law.c
deleted file mode 100644
index 224af6ca77..0000000000
--- a/board/tqm85xx/law.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xf800_0000 0xf80f_ffff BCSR 1M
- * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
- SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
- SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
- SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
- SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c
deleted file mode 100644
index 788a48cd13..0000000000
--- a/board/tqm85xx/sdram.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-struct sdram_conf_s {
- unsigned long size;
- unsigned long reg;
-};
-
-typedef struct sdram_conf_s sdram_conf_t;
-
-sdram_conf_t ddr_cs_conf[] = {
- {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
- {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
- {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
- {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
-};
-
-#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
-
-int cas_latency(void);
-
-/*
- * Autodetect onboard DDR SDRAM on 85xx platforms
- *
- * NOTE: Some of the hardcoded values are hardware dependant,
- * so this should be extended for other future boards
- * using this routine!
- */
-long int sdram_setup(int casl)
-{
- int i;
- volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
- unsigned long cfg_ddr_timing1;
- unsigned long cfg_ddr_mode;
-
- /*
- * Disable memory controller.
- */
- ddr->cs0_config = 0;
- ddr->sdram_cfg = 0;
-
- switch (casl) {
- case 20:
- cfg_ddr_timing1 = 0x47405331 | (3 << 16);
- cfg_ddr_mode = 0x40020002 | (2 << 4);
- break;
-
- case 25:
- cfg_ddr_timing1 = 0x47405331 | (4 << 16);
- cfg_ddr_mode = 0x40020002 | (6 << 4);
- break;
-
- case 30:
- default:
- cfg_ddr_timing1 = 0x47405331 | (5 << 16);
- cfg_ddr_mode = 0x40020002 | (3 << 4);
- break;
- }
-
- ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
- ddr->cs0_config = ddr_cs_conf[0].reg;
- ddr->timing_cfg_1 = cfg_ddr_timing1;
- ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
- ddr->sdram_mode = cfg_ddr_mode;
- ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
- ddr->err_disable = 0x0000000D;
-
- asm ("sync;isync;msync");
- udelay(1000);
-
- ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
- asm ("sync; isync; msync");
- udelay(1000);
-
- for (i=0; i<N_DDR_CS_CONF; i++) {
- ddr->cs0_config = ddr_cs_conf[i].reg;
-
- if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) {
- /*
- * OK, size detected -> all done
- */
- return ddr_cs_conf[i].size;
- }
- }
-
- return 0; /* nothing found ! */
-}
-
-void board_add_ram_info(int use_default)
-{
- int casl;
-
- if (use_default)
- casl = CONFIG_DDR_DEFAULT_CL;
- else
- casl = cas_latency();
-
- puts(" (CL=");
- switch (casl) {
- case 20:
- puts("2)");
- break;
-
- case 25:
- puts("2.5)");
- break;
-
- case 30:
- puts("3)");
- break;
- }
-}
-
-long int initdram (int board_type)
-{
- long dram_size = 0;
- int casl;
-
-#if defined(CONFIG_DDR_DLL)
- /*
- * This DLL-Override only used on TQM8540 and TQM8560
- */
- {
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- int i,x;
-
- x = 10;
-
- /*
- * Work around to stabilize DDR DLL
- */
- gur->ddrdllcr = 0x81000000;
- asm("sync;isync;msync");
- udelay (200);
- while (gur->ddrdllcr != 0x81000100) {
- gur->devdisr = gur->devdisr | 0x00010000;
- asm("sync;isync;msync");
- for (i=0; i<x; i++)
- ;
- gur->devdisr = gur->devdisr & 0xfff7ffff;
- asm("sync;isync;msync");
- x++;
- }
- }
-#endif
-
- casl = cas_latency();
- dram_size = sdram_setup(casl);
- if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
- /*
- * Try again with default CAS latency
- */
- puts("Problem with CAS lantency");
- board_add_ram_info(1);
- puts(", using default CL!\n");
- casl = CONFIG_DDR_DEFAULT_CL;
- dram_size = sdram_setup(casl);
- puts(" ");
- }
-
- return dram_size;
-}
-
-#if defined(CFG_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
- uint *p;
-
- printf ("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf ("SDRAM test passed.\n");
- return 0;
-}
-#endif
diff --git a/board/tqm85xx/tlb.c b/board/tqm85xx/tlb.c
deleted file mode 100644
index ad26caeea2..0000000000
--- a/board/tqm85xx/tlb.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
-
- /*
- * TLB 0, 1: 128M Non-cacheable, guarded
- * 0xf8000000 128M FLASH
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_64M, 1),
- SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xc0000000 256M Rapid IO MEM First half
- */
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 5: 256M Non-cacheable, guarded
- * 0xd0000000 256M Rapid IO MEM Second half
- */
- SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 6: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- */
- SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
- * 0x00000000 512M DDR System memory
- * Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
- */
- SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_256M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c
deleted file mode 100644
index 8fa0162d83..0000000000
--- a/board/tqm85xx/tqm85xx.c
+++ /dev/null
@@ -1,419 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003, Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <ioports.h>
-#include <flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[]; /* FLASH chips info */
-
-void local_bus_init (void);
-ulong flash_get_size (ulong base, int banknum);
-
-#ifdef CONFIG_PS2MULT
-void ps2mult_early_init(void);
-#endif
-
-#ifdef CONFIG_CPM2
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-#endif /* CONFIG_CPM2 */
-
-#define CASL_STRING1 "casl=xx"
-#define CASL_STRING2 "casl="
-
-static const int casl_table[] = { 20, 25, 30 };
-#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
-
-int cas_latency(void)
-{
- char *s = getenv("serial#");
- int casl;
- int val;
- int i;
-
- casl = CONFIG_DDR_DEFAULT_CL;
-
- if (s != NULL) {
- if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
- strlen(CASL_STRING2)) == 0) {
- val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
-
- for (i=0; i<N_CASL; ++i) {
- if (val == casl_table[i]) {
- return val;
- }
- }
- }
- }
-
- return casl;
-}
-
-int checkboard (void)
-{
- char *s = getenv("serial#");
-
- printf("Board: %s", CONFIG_BOARDNAME);
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
- putc('\n');
-
-#ifdef CONFIG_PCI
- printf ("PCI1: 32 bit, %d MHz (compiled)\n",
- CONFIG_SYS_CLK_FREQ / 1000000);
-#else
- printf ("PCI1: disabled\n");
-#endif
-
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
-
- /*
- * Adjust flash start and offset to detected values
- */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- /*
- * Check if boot FLASH isn't max size
- */
- if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
- memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
- memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
- }
-
- /*
- * Check if only one FLASH bank is available
- */
- if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
- memctl->or1 = 0;
- memctl->br1 = 0;
-
- /*
- * Re-do flash protection upon new addresses
- */
- flash_protect (FLAG_PROTECT_CLEAR,
- gd->bd->bi_flashstart, 0xffffffff,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
- /* Monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
- /* Environment protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
- /* Redundant environment protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CFG_ENV_ADDR_REDUND,
- CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
- }
-
- return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void local_bus_init (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
-
- /*
- * Errata LBC11.
- * Fix Local Bus clock glitch when DLL is enabled.
- *
- * If localbus freq is < 66Mhz, DLL bypass mode must be used.
- * If localbus freq is > 133Mhz, DLL can be safely enabled.
- * Between 66 and 133, the DLL is enabled with an override workaround.
- */
-
- get_sys_info (&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-
- if (lbc_hz < 66) {
- lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
- lbc->ltedr = 0xa4c80000; /* DK: !!! */
-
- } else if (lbc_hz >= 133) {
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
-
- } else {
- /*
- * On REV1 boards, need to change CLKDIV before enable DLL.
- * Default CLKDIV is 8, change it to 4 temporarily.
- */
- uint pvr = get_pvr ();
- uint temp_lbcdll = 0;
-
- if (pvr == PVR_85xx_REV1) {
- /* FIXME: Justify the high bit here. */
- lbc->lcrr = 0x10000004;
- }
-
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
- udelay (200);
-
- /*
- * Sample LBC DLL ctrl reg, upshift it to set the
- * override bits.
- */
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
- asm ("sync;isync;msync");
- }
-}
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc85xxads_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER}},
- {}
-};
-#endif
-
-
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc85xxads_config_table,
-#endif
-};
-
-#endif /* CONFIG_PCI */
-
-
-void pci_init_board (void)
-{
-#ifdef CONFIG_PCI
- pci_mpc85xx_init (&hose);
-#endif /* CONFIG_PCI */
-}
-
-#ifdef CONFIG_BOARD_EARLY_INIT_R
-int board_early_init_r (void)
-{
-#ifdef CONFIG_PS2MULT
- ps2mult_early_init();
-#endif /* CONFIG_PS2MULT */
- return (0);
-}
-#endif /* CONFIG_BOARD_EARLY_INIT_R */
diff --git a/board/tqm85xx/u-boot.lds b/board/tqm85xx/u-boot.lds
deleted file mode 100644
index 8cb551ae4b..0000000000
--- a/board/tqm85xx/u-boot.lds
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * (C) Copyright 2002,2003, Motorola,Inc.
- * Xianghua Xiao, X.Xiao@motorola.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xFFFFFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xFFFFF000 :
- {
- cpu/mpc85xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- cpu/mpc85xx/start.o (.text)
- cpu/mpc85xx/traps.o (.text)
- cpu/mpc85xx/interrupts.o (.text)
- cpu/mpc85xx/cpu_init.o (.text)
- cpu/mpc85xx/cpu.o (.text)
- cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/pci.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
- *(.text)
- *(.fixup)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
generated by cgit (git 2.34.1) at 2024-12-28 15:55:21 +0000