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-rw-r--r--board/w7o/flash.c4
-rw-r--r--board/w7o/fpga.c34
-rw-r--r--board/w7o/u-boot.lds3
-rw-r--r--board/w7o/u-boot.lds.debug2
-rw-r--r--board/w7o/vpd.c4
-rw-r--r--board/w7o/w7o.c22
-rw-r--r--board/w7o/w7o.h12
7 files changed, 43 insertions, 38 deletions
diff --git a/board/w7o/flash.c b/board/w7o/flash.c
index d6ea63530c..32815fb63e 100644
--- a/board/w7o/flash.c
+++ b/board/w7o/flash.c
@@ -805,7 +805,7 @@ static int _flash_protect(flash_info_t *info, long sector)
int flag;
ulong status;
int rcode = 0;
- volatile long *addr = (unsigned long *)sector;
+ volatile long *addr = (long *)sector;
switch(info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F320J3A:
@@ -863,7 +863,7 @@ static int _flash_unprotect(flash_info_t *info, long sector)
int flag;
ulong status;
int rcode = 0;
- volatile long *addr = (unsigned long *)sector;
+ volatile long *addr = (long *)sector;
switch(info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F320J3A:
diff --git a/board/w7o/fpga.c b/board/w7o/fpga.c
index 97af924294..100bce4722 100644
--- a/board/w7o/fpga.c
+++ b/board/w7o/fpga.c
@@ -77,17 +77,17 @@ fpgaDownload(unsigned char *saddr,
dest = (unsigned short *)daddr;
/* Get DCR output register */
- grego = in32(IBM405GP_GPIO0_OR);
+ grego = in32(PPC405GP_GPIO0_OR);
/* Reset FPGA */
grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
/* Setup timeout timer */
start = get_timer(0);
/* Wait for FPGA init line */
- while(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
+ while(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
/* Check for timeout - 100us max, so use 3ms */
if (get_timer(start) > 3) {
printf(" failed to start init.\n");
@@ -100,10 +100,10 @@ fpgaDownload(unsigned char *saddr,
/* Unreset FPGA */
grego |= GPIO_XCV_PROG; /* PROG line high */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
/* Wait for FPGA end of init period . */
- while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
+ while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
/* Check for timeout */
if (get_timer(start) > 3) {
@@ -112,7 +112,7 @@ fpgaDownload(unsigned char *saddr,
/* Reset FPGA */
grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
goto done;
}
@@ -127,18 +127,18 @@ fpgaDownload(unsigned char *saddr,
mtdcr(CPC0_CR0, greg); /* ... just do it */
/* turn on open drain for CNFG */
- greg = in32(IBM405GP_GPIO0_ODR); /* get open drain register */
+ greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */
greg |= cnfg; /* CNFG open drain */
- out32(IBM405GP_GPIO0_ODR, greg); /* .. just do it */
+ out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */
/* Turn output enable on for CNFG */
- greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */
+ greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
greg |= cnfg; /* CNFG tristate inactive */
- out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */
+ out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
/* Setup FPGA for programming */
grego &= ~cnfg; /* CONFIG line low */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
/*
* Program the FPGA
@@ -149,12 +149,12 @@ fpgaDownload(unsigned char *saddr,
/* Done programming */
grego |= cnfg; /* CONFIG line high */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
/* Turn output enable OFF for CNFG */
- greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */
+ greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
greg &= ~cnfg; /* CNFG tristate inactive */
- out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */
+ out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
/* Toggle IRQ/GPIO */
greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
@@ -180,7 +180,7 @@ fpgaDownload(unsigned char *saddr,
start = get_timer(0);
/* Wait for FPGA end of programming period . */
- while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
+ while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
/* Check for timeout */
if (get_timer(start) > 3) {
@@ -189,7 +189,7 @@ fpgaDownload(unsigned char *saddr,
/* Reset FPGA */
grego &= ~GPIO_XCV_PROG; /* PROG line low */
- out32(IBM405GP_GPIO0_OR, grego);
+ out32(PPC405GP_GPIO0_OR, grego);
goto done;
}
@@ -252,7 +252,7 @@ int init_fpga(void)
xcv_len = len - 14 - fn_len; /* fpga image length */
/* Check for uninitialized FLASH */
- if ((strncmp(buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0))
+ if ((strncmp((char *)buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0))
goto bad_image;
/*
diff --git a/board/w7o/u-boot.lds b/board/w7o/u-boot.lds
index 5576ab9a67..7e3e15dc2e 100644
--- a/board/w7o/u-boot.lds
+++ b/board/w7o/u-boot.lds
@@ -71,6 +71,7 @@ SECTIONS
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
@@ -103,11 +104,13 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
+ . = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug
index f996db30ad..a0c72c9210 100644
--- a/board/w7o/u-boot.lds.debug
+++ b/board/w7o/u-boot.lds.debug
@@ -74,6 +74,8 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
diff --git a/board/w7o/vpd.c b/board/w7o/vpd.c
index fc2cd98321..2ce15680e1 100644
--- a/board/w7o/vpd.c
+++ b/board/w7o/vpd.c
@@ -125,7 +125,7 @@ static int vpd_is_valid(unsigned dev_addr, unsigned char *buf)
unsigned short stored_crc16, calc_crc16 = 0xffff;
/* Check Eyecatcher */
- if (strncmp(vpd->header.eyecatcher, VPD_EYECATCHER, VPD_EYE_SIZE) != 0) {
+ if (strncmp((char *)(vpd->header.eyecatcher), VPD_EYECATCHER, VPD_EYE_SIZE) != 0) {
unsigned offset = 0;
if (dev_addr == CFG_DEF_EEPROM_ADDR)
offset += SDRAM_SPD_DATA_SIZE;
@@ -259,7 +259,7 @@ int vpd_get_data(unsigned char dev_addr, VPD *vpdInfo)
case VPD_PID_PID:
if (strlen_ok(packet, MAX_PROD_ID)) {
strncpy(vpdInfo->productId,
- packet->data, packet->size);
+ (char *)(packet->data), packet->size);
}
break;
case VPD_PID_REV:
diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c
index 1e3ceb20d6..c56c269dae 100644
--- a/board/w7o/w7o.c
+++ b/board/w7o/w7o.c
@@ -47,9 +47,9 @@ int board_early_init_f (void)
/*
* Setup GPIO pins - reset devices.
*/
- out32 (IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
- out32 (IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
- out32 (IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
+ out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
+ out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
+ out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
@@ -78,9 +78,9 @@ int board_early_init_f (void)
/*
* Setup GPIO pins
*/
- out32 (IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
- out32 (IBM405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
- out32 (IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
+ out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
+ out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
+ out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
@@ -207,8 +207,8 @@ static void w7o_env_init (VPD * vpd)
(strncmp (vpd->productId, "CMM", 3) == 0))) {
char buf[30];
char *eth;
- unsigned char *serial = getenv ("serial#");
- unsigned char *ethaddr = getenv ("ethaddr");
+ char *serial = getenv ("serial#");
+ char *ethaddr = getenv ("ethaddr");
/* Set 'serial#' envvar if serial# isn't set */
if (!serial) {
@@ -218,7 +218,7 @@ static void w7o_env_init (VPD * vpd)
}
/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
- eth = vpd->ethAddrs[0];
+ eth = (char *)(vpd->ethAddrs[0]);
if (ethaddr
&& (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
/* Now setup ethaddr */
@@ -238,14 +238,14 @@ int misc_init_r (void)
#if defined(CONFIG_W7OLMG)
unsigned long greg; /* GPIO Register */
- greg = in32 (IBM405GP_GPIO0_OR);
+ greg = in32 (PPC405GP_GPIO0_OR);
/*
* XXX - Unreset devices - this should be moved into VxWorks driver code
*/
greg |= 0x41800000L; /* SAM, PHY, Galileo */
- out32 (IBM405GP_GPIO0_OR, greg); /* set output pins to default */
+ out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */
#endif /* CONFIG_W7OLMG */
/*
diff --git a/board/w7o/w7o.h b/board/w7o/w7o.h
index 84581664e8..d6f50e2e67 100644
--- a/board/w7o/w7o.h
+++ b/board/w7o/w7o.h
@@ -25,13 +25,13 @@
#define _W7O_H_
#include <config.h>
-/* IBM 405GP PowerPC GPIO registers */
-#define IBM405GP_GPIO0_OR 0xef600700L /* GPIO Output */
-#define IBM405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
-#define IBM405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
-#define IBM405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
+/* AMCC 405GP PowerPC GPIO registers */
+#define PPC405GP_GPIO0_OR 0xef600700L /* GPIO Output */
+#define PPC405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
+#define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
+#define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
-/* IBM 405GP DCRs */
+/* AMCC 405GP DCRs */
#define CPC0_CR0 0xb1 /* Chip control register 0 */
/* LMG FPGA <=> CPU GPIO signals */
generated by cgit (git 2.34.1) at 2024-12-27 21:52:59 +0000