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-rw-r--r--board/xilinx/ppc405-generic/MAINTAINERS2
-rw-r--r--board/xilinx/ppc405-generic/Makefile4
-rw-r--r--board/xilinx/ppc405-generic/xilinx_ppc405_generic.c31
-rw-r--r--board/xilinx/ppc405-generic/xparameters.h7
4 files changed, 18 insertions, 26 deletions
diff --git a/board/xilinx/ppc405-generic/MAINTAINERS b/board/xilinx/ppc405-generic/MAINTAINERS
index 2b0c98dc8b..ba48f50c29 100644
--- a/board/xilinx/ppc405-generic/MAINTAINERS
+++ b/board/xilinx/ppc405-generic/MAINTAINERS
@@ -1,5 +1,5 @@
PPC405-GENERIC BOARD
-M: Ricardo Ribalda <ricardo.ribalda@uam.es>
+M: Ricardo Ribalda <ricardo.ribalda@gmail.com>
S: Maintained
F: board/xilinx/ppc405-generic/
F: include/configs/xilinx-ppc405-generic.h
diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile
index c9da870657..2800f68626 100644
--- a/board/xilinx/ppc405-generic/Makefile
+++ b/board/xilinx/ppc405-generic/Makefile
@@ -3,10 +3,10 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
# Work supported by Qtechnology http://www.qtec.com
#
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
+obj-y += xilinx_ppc405_generic.o
diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
index e3dd468f1e..3729f07624 100644
--- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
+++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
*
* SPDX-License-Identifier: GPL-2.0+
@@ -10,39 +10,32 @@
#include <common.h>
#include <asm/processor.h>
-ulong __get_PCI_freq(void)
+ulong get_PCI_freq(void)
{
return 0;
}
-ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq")));
-
-int __board_pre_init(void)
-{
- return 0;
-}
-int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
-
-int __checkboard(void)
+int checkboard(void)
{
puts("Xilinx PPC405 Generic Board\n");
return 0;
}
-int checkboard(void) __attribute__((weak, alias("__checkboard")));
-phys_size_t __initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
}
-phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
-void __get_sys_info(sys_info_t *sysInfo)
+void get_sys_info(sys_info_t *sys_info)
{
- sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
- sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
- sysInfo->freqPCI = 0;
+ sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+ sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+ sys_info->freqPCI = 0;
return;
}
-void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
+
+int get_serial_clock(void){
+ return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
+}
diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h
index f0ff78fca5..c3df9e5109 100644
--- a/board/xilinx/ppc405-generic/xparameters.h
+++ b/board/xilinx/ppc405-generic/xparameters.h
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
* This work has been supported by: QTechnology http://qtec.com/
* based on xparameters-ml507.h by Xilinx
*
@@ -14,12 +14,11 @@
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
#define XPAR_INTC_0_BASEADDR 0x81800000
#define XPAR_SPI_0_BASEADDR 0x83400000
-#define XPAR_UARTLITE_0_BASEADDR 0x84000000
#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
-#define XPAR_UARTLITE_0_BAUDRATE 9600
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif