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-rw-r--r--board/xilinx/zynq/board.c13
-rw-r--r--board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c815
l---------board/xilinx/zynq/zynq-cse-qspi-single1
-rw-r--r--board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c285
-rw-r--r--board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h117
-rw-r--r--board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c289
-rw-r--r--board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h117
-rw-r--r--board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c285
-rw-r--r--board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h117
-rw-r--r--board/xilinx/zynq/zynq-zed/ps7_init_gpl.c285
-rw-r--r--board/xilinx/zynq/zynq-zed/ps7_init_gpl.h117
-rw-r--r--board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c292
-rw-r--r--board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h98
13 files changed, 831 insertions, 2000 deletions
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 90ef542458..e59038106a 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -11,6 +11,7 @@
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/ps7_init_gpl.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -111,7 +112,15 @@ int board_late_init(void)
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
+ u32 version = zynq_get_silicon_version();
+
+ version <<= 1;
+ if (version > (PCW_SILICON_VERSION_3 << 1))
+ version += 1;
+
puts("Board: Xilinx Zynq\n");
+ printf("Silicon: v%d.%d\n", version >> 1, version & 1);
+
return 0;
}
#endif
@@ -132,9 +141,7 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
- fdtdec_setup_memory_banksize();
-
- return 0;
+ return fdtdec_setup_memory_banksize();
}
int dram_init(void)
diff --git a/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
new file mode 100644
index 0000000000..9a65a27f0e
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
@@ -0,0 +1,815 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+ EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+ EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+ EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+ EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+ EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+ EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+ EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+ EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+ EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+ EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+ EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+ EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+ EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+ EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+ EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+ EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+ EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+ EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+ EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+ EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+ EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+ EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_MASKDELAY(0XF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+ EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret = -1;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config(ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config(ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else {
+ ret = ps7_config(ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ unsigned long *ps7_mio_init_data;
+ unsigned long *ps7_pll_init_data;
+ unsigned long *ps7_clock_init_data;
+ unsigned long *ps7_ddr_init_data;
+ unsigned long *ps7_peripherals_init_data;
+ int ret;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ }
+
+ ret = ps7_config(ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/xilinx/zynq/zynq-cse-qspi-single b/board/xilinx/zynq/zynq-cse-qspi-single
new file mode 120000
index 0000000000..764d141171
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cse-qspi-single
@@ -0,0 +1 @@
+zynq-zc706 \ No newline at end of file
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index eb290023a1..5cf627d223 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -14,7 +14,7 @@
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
@@ -4121,37 +4121,6 @@ unsigned long ps7_post_config_3_0[] = {
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
@@ -8419,37 +8388,6 @@ unsigned long ps7_post_config_2_0[] = {
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
@@ -12650,173 +12588,9 @@ unsigned long ps7_post_config_1_0[] = {
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -12844,25 +12618,6 @@ ps7_post_config()
}
int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
ps7_init()
{
// Get the PS_VERSION on run time
@@ -12923,41 +12678,3 @@ ps7_init()
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
deleted file mode 100644
index bdea5a0443..0000000000
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 100000000
-#define FPGA2_FREQ 33333336
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
index abfd91187d..fc325a6b02 100644
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -14,7 +14,7 @@
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
@@ -4228,37 +4228,6 @@ unsigned long ps7_post_config_3_0[] = {
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
@@ -8639,37 +8608,6 @@ unsigned long ps7_post_config_2_0[] = {
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
@@ -12983,173 +12921,9 @@ unsigned long ps7_post_config_1_0[] = {
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -13177,25 +12951,6 @@ ps7_post_config()
}
int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
ps7_init()
{
// Get the PS_VERSION on run time
@@ -13252,45 +13007,3 @@ ps7_init()
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
return PS7_INIT_SUCCESS;
}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
deleted file mode 100644
index 16fa8104a4..0000000000
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 25000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 23809523
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 50000000
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
index 77fd9499df..ca5490f0b0 100644
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -14,7 +14,7 @@
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
@@ -4197,37 +4197,6 @@ unsigned long ps7_post_config_3_0[] = {
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
@@ -8577,37 +8546,6 @@ unsigned long ps7_post_config_2_0[] = {
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
@@ -12890,173 +12828,9 @@ unsigned long ps7_post_config_1_0[] = {
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -13084,25 +12858,6 @@ ps7_post_config()
}
int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
ps7_init()
{
// Get the PS_VERSION on run time
@@ -13163,41 +12918,3 @@ ps7_init()
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
deleted file mode 100644
index 8527eef447..0000000000
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 25000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 50000000
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
index f4f45becd6..54c803cfa6 100644
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -14,7 +14,7 @@
*
*****************************************************************************/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
@@ -4087,37 +4087,6 @@ unsigned long ps7_post_config_3_0[] = {
//
};
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_2_0[] = {
// START: top
@@ -8351,37 +8320,6 @@ unsigned long ps7_post_config_2_0[] = {
//
};
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
unsigned long ps7_pll_init_data_1_0[] = {
// START: top
@@ -12548,173 +12486,9 @@ unsigned long ps7_post_config_1_0[] = {
//
};
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- unsigned long *addr = (unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- unsigned long *addr = (unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -12742,25 +12516,6 @@ ps7_post_config()
}
int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
ps7_init()
{
// Get the PS_VERSION on run time
@@ -12821,41 +12576,3 @@ ps7_init()
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
deleted file mode 100644
index 9b41e28697..0000000000
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
+++ /dev/null
@@ -1,117 +0,0 @@
-
-/******************************************************************************
-*
-* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
-*******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158731
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 50000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 142857132
-#define FPGA2_FREQ 50000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
index 83daf7bf15..84625f0746 100644
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "ps7_init_gpl.h"
+#include <asm/arch/ps7_init_gpl.h>
unsigned long ps7_pll_init_data_3_0[] = {
/* START: top */
@@ -4141,37 +4141,6 @@ unsigned long ps7_post_config_3_0[] = {
/* */
};
-unsigned long ps7_debug_3_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
unsigned long ps7_pll_init_data_2_0[] = {
/* START: top */
@@ -8467,37 +8436,6 @@ unsigned long ps7_post_config_2_0[] = {
/* */
};
-unsigned long ps7_debug_2_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
unsigned long ps7_pll_init_data_1_0[] = {
/* START: top */
@@ -12726,178 +12664,8 @@ unsigned long ps7_post_config_1_0[] = {
/* */
};
-unsigned long ps7_debug_1_0[] = {
- /* START: top */
- /* .. START: CROSS TRIGGER CONFIGURATIONS */
- /* .. .. START: UNLOCKING CTI REGISTERS */
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. KEY = 0XC5ACCE55 */
- /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */
- /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */
- /* .. .. */
- EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U),
- /* .. .. FINISH: UNLOCKING CTI REGISTERS */
- /* .. .. START: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */
- /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */
- /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */
- /* FINISH: top */
- /* */
- EMIT_EXIT(),
-
- /* */
-};
#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char *getPS7MessageInfo(unsigned key)
-{
- char *err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS:
- err_msg = "PS7 initialization successful";
- break;
- case PS7_INIT_CORRUPT:
- err_msg = "PS7 init Data Corrupted";
- break;
- case PS7_INIT_TIMEOUT:
- err_msg = "PS7 init mask poll timeout";
- break;
- case PS7_POLL_FAILED_DDR_INIT:
- err_msg = "Mask Poll failed for DDR Init";
- break;
- case PS7_POLL_FAILED_DMA:
- err_msg = "Mask Poll failed for PLL Init";
- break;
- case PS7_POLL_FAILED_PLL:
- err_msg = "Mask Poll failed for DMA done bit";
- break;
- default:
- err_msg = "Undefined error status";
- break;
- }
-
- return err_msg;
-}
-
-unsigned long ps7GetSiliconVersion(void)
-{
- /* Read PS version from MCTRL register [31:28] */
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long *)0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write(unsigned long add, unsigned long mask, unsigned long val)
-{
- unsigned long *addr = (unsigned long *)add;
- *addr = (val & mask) | (*addr & ~mask);
-}
-
-int mask_poll(unsigned long add, unsigned long mask)
-{
- volatile unsigned long *addr = (volatile unsigned long *)add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME)
- return -1;
- i++;
- }
- return 1;
-}
-
-unsigned long mask_read(unsigned long add, unsigned long mask)
-{
- unsigned long *addr = (unsigned long *)add;
- unsigned long val = (*addr & mask);
- return val;
-}
-
-int ps7_config(unsigned long *ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; /* current instruction .. */
- unsigned long args[16]; /* no opcode has so many args ... */
- int numargs; /* number of arguments of this instruction */
- int j; /* general purpose index */
-
- volatile unsigned long *addr; /* some variable to make code readable */
- unsigned long val, mask; /* some variable to make code readable */
-
- int finish = -1; /* loop while this is negative ! */
- int i = 0; /* Timeout variable */
-
- while (finish < 0) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for (j = 0; j < numargs; j++)
- args[j] = ptr[j + 1];
- ptr += numargs + 1;
-
- switch (opcode) {
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long *)args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long *)args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long *)args[0];
- mask = args[1];
- val = args[2];
- *addr = (val & mask) | (*addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long *)args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- addr = (unsigned long *)args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay))
- ;
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
@@ -12926,27 +12694,6 @@ int ps7_post_config(void)
return PS7_INIT_SUCCESS;
}
-int ps7_debug(void)
-{
- /* Get the PS_VERSION on run time */
- unsigned long si_ver = ps7GetSiliconVersion();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config(ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config(ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- } else {
- ret = ps7_config(ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS)
- return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
int ps7_init(void)
{
/* Get the PS_VERSION on run time */
@@ -13006,40 +12753,3 @@ int ps7_init(void)
return PS7_INIT_SUCCESS;
}
-/* For delay calculation using global timer */
-
-/* start timer */
-void perf_start_clock(void)
-{
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */
- (1 << 3) | /* Auto-increment */
- (0 << 8) /* Pre-scale */
- );
-}
-
-/* stop timer and reset timer count regs */
-void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- /* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */
- return APU_FREQ * delay / (2 * 1000);
-}
-
-/* stop timer */
-void perf_disable_clock(void)
-{
- *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer(void)
-{
- perf_reset_clock();
- perf_start_clock();
-}
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
deleted file mode 100644
index 22d9fd9250..0000000000
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*typedef unsigned int u32; */
-
-/** do we need to make this name more unique ? **/
-/*extern u32 ps7_init_data[]; */
-extern unsigned long *ps7_ddr_init_data;
-extern unsigned long *ps7_mio_init_data;
-extern unsigned long *ps7_pll_init_data;
-extern unsigned long *ps7_clock_init_data;
-extern unsigned long *ps7_peripherals_init_data;
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0)
-#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr
-#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val
-#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val
-#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask
-#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */
-#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */
-#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */
-#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */
-#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */
-#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 650000000
-#define DDR_FREQ 525000000
-#define DCI_FREQ 10096154
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 100000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 108333336
-#define WDT_FREQ 108333336
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 100000000
-#define FPGA1_FREQ 142857132
-#define FPGA2_FREQ 200000000
-#define FPGA3_FREQ 50000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config(unsigned long *);
-int ps7_init(void);
-int ps7_post_config(void);
-int ps7_debug(void);
-char *getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer(void);
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
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