diff options
Diffstat (limited to 'board')
32 files changed, 791 insertions, 264 deletions
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index c7f6479a0c..c21d2f3ffa 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -379,7 +379,7 @@ int board_init(void) puts("Cannot find Armada 385 watchdog!\n"); } else { puts("Enabling Armada 385 watchdog.\n"); - wdt_start(watchdog_dev, (u32) 25000000 * 120, 0); + wdt_start(watchdog_dev, 120000, 0); } # endif diff --git a/board/Marvell/db-xc3-24g4xg/.gitignore b/board/Marvell/db-xc3-24g4xg/.gitignore new file mode 100644 index 0000000000..775b9346b8 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/.gitignore @@ -0,0 +1 @@ +kwbimage.cfg diff --git a/board/Marvell/db-xc3-24g4xg/MAINTAINERS b/board/Marvell/db-xc3-24g4xg/MAINTAINERS new file mode 100644 index 0000000000..2b27e48181 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/MAINTAINERS @@ -0,0 +1,7 @@ +DB-XC3-24G4XG BOARD +M: Chris Packham <chris.packham@alliedtelesis.co.nz> +S: Maintained +F: board/Marvell/db-xc3-24g4xg/ +F: include/configs/db-xc3-24g4xg.h +F: configs/db-xc3-24g4xg_defconfig +F: arch/arm/dts/armada-xp-db-xc3-24g4xg.dts diff --git a/board/Marvell/db-xc3-24g4xg/Makefile b/board/Marvell/db-xc3-24g4xg/Makefile new file mode 100644 index 0000000000..4dd57902d4 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> + +obj-y := db-xc3-24g4xg.o +extra-y := kwbimage.cfg + +quiet_cmd_sed = SED $@ + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F) + +SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|" +$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ + include/config/auto.conf + $(call if_changed,sed) diff --git a/board/Marvell/db-xc3-24g4xg/README b/board/Marvell/db-xc3-24g4xg/README new file mode 100644 index 0000000000..5e479b433e --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/README @@ -0,0 +1,4 @@ +To generate binary.0 from Marvell's bin_hdr.elf use the following command + + arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \ + board/Marvell/db-xc3-24g4xg/binary.0 diff --git a/board/Marvell/db-xc3-24g4xg/binary.0 b/board/Marvell/db-xc3-24g4xg/binary.0 new file mode 100644 index 0000000000..8dd687286a --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/binary.0 @@ -0,0 +1,11 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. diff --git a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c new file mode 100644 index 0000000000..cae428ffd0 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + */ + +#include <common.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * These values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-2016_T1.0.eng_drop_v6" + */ +#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \ + | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))) +#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0)) +#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \ + | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)) +#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0 +#define DB_DX_AC3_GPP_POL_LOW 0x0 +#define DB_DX_AC3_GPP_POL_MID 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00142222, MVEBU_MPP_BASE + 0x00); + writel(0x11122000, MVEBU_MPP_BASE + 0x04); + writel(0x44444004, MVEBU_MPP_BASE + 0x08); + writel(0x14444444, MVEBU_MPP_BASE + 0x0c); + writel(0x00000001, MVEBU_MPP_BASE + 0x10); + + /* Set GPP Out value */ + writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board: " CONFIG_SYS_BOARD "\n"); + + return 0; +} +#endif diff --git a/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in new file mode 100644 index 0000000000..b8bb7a6eb7 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068 diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c index eb3694ea6e..d23e97c9b9 100644 --- a/board/Synology/ds414/ds414.c +++ b/board/Synology/ds414/ds414.c @@ -115,14 +115,14 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) return &ds414_ddr_modes[0]; } -MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) { return &ds414_serdes_cfg[0]; } u8 board_sat_r_get(u8 dev_num, u8 reg) { - return (0x1 << 1 | 1); + return 0xf; /* All PEX ports support PCIe Gen2 */ } int board_early_init_f(void) diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index d7d1942fe6..6934fd8017 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -7,6 +7,7 @@ #include <command.h> #include <dm.h> #include <i2c.h> +#include <wdt.h> #include <asm/gpio.h> #include <linux/mbus.h> #include <linux/io.h> @@ -24,6 +25,10 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_NVS_LOCATION 0xf4800000 #define CONFIG_NVS_SIZE (512 << 10) +#ifdef CONFIG_WATCHDOG +static struct udevice *watchdog_dev; +#endif + static struct serdes_map board_serdes_map[] = { {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, @@ -75,6 +80,10 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) int board_early_init_f(void) { +#ifdef CONFIG_WATCHDOG + watchdog_dev = NULL; +#endif + /* Configure MPP */ writel(0x00001111, MVEBU_MPP_BASE + 0x00); writel(0x00000000, MVEBU_MPP_BASE + 0x04); @@ -88,6 +97,17 @@ int board_early_init_f(void) return 0; } +void spl_board_init(void) +{ +#ifdef CONFIG_WATCHDOG + int ret; + + ret = uclass_get_device(UCLASS_WDT, 0, &watchdog_dev); + if (!ret) + wdt_start(watchdog_dev, 120000, 0); +#endif +} + int board_init(void) { /* address of boot parameters */ @@ -100,9 +120,37 @@ int board_init(void) /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */ writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8); + spl_board_init(); + return 0; } +void arch_preboot_os(void) +{ +#ifdef CONFIG_WATCHDOG + wdt_stop(watchdog_dev); +#endif +} + +#ifdef CONFIG_WATCHDOG +void watchdog_reset(void) +{ + static ulong next_reset = 0; + ulong now; + + if (!watchdog_dev) + return; + + now = timer_get_us(); + + /* Do not reset the watchdog too often */ + if (now > next_reset) { + wdt_reset(watchdog_dev); + next_reset = now + 1000; + } +} +#endif + static int led_7seg_init(unsigned int segments) { int node; diff --git a/board/bosch/guardian/Kconfig b/board/bosch/guardian/Kconfig new file mode 100644 index 0000000000..1417da61f0 --- /dev/null +++ b/board/bosch/guardian/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AM335X_GUARDIAN + +config SYS_BOARD + default "guardian" + +config SYS_VENDOR + default "bosch" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "am335x_guardian" + +endif diff --git a/board/bosch/guardian/MAINTAINERS b/board/bosch/guardian/MAINTAINERS new file mode 100644 index 0000000000..8d16ec0202 --- /dev/null +++ b/board/bosch/guardian/MAINTAINERS @@ -0,0 +1,6 @@ +Guardian BOARD +M: Sjoerd Simons <sjoerd.simons@collabora.co.uk> +S: Maintained +F: board/bosch/guardian/ +F: include/configs/am335x_guardian.h +F: configs/am335x_guardian_defconfig diff --git a/board/bosch/guardian/Makefile b/board/bosch/guardian/Makefile new file mode 100644 index 0000000000..11625c9dd6 --- /dev/null +++ b/board/bosch/guardian/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Makefile +# +# Copyright (C) 2018 Robert Bosch Power Tools GmbH +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c new file mode 100644 index 0000000000..86ab180f5c --- /dev/null +++ b/board/bosch/guardian/board.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * board.c + * + * Board functions for Bosch Guardian + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Robert Bosch Power Tools GmbH + */ + +#include <common.h> +#include <cpsw.h> +#include <dm.h> +#include <environment.h> +#include <environment.h> +#include <errno.h> +#include <i2c.h> +#include <miiphy.h> +#include <panel.h> +#include <power/tps65217.h> +#include <power/tps65910.h> +#include <spl.h> +#include <watchdog.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/omap.h> +#include <asm/arch/sys_proto.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K128M16JT125K_RD_DQS, + .datawdsratio0 = MT41K128M16JT125K_WR_DQS, + .datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE, + .datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K128M16JT125K_RATIO, + .cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT, + + .cmd1csratio = MT41K128M16JT125K_RATIO, + .cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT, + + .cmd2csratio = MT41K128M16JT125K_RATIO, + .cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K128M16JT125K_EMIF_SDCFG, + .ref_ctrl = MT41K128M16JT125K_EMIF_SDREF, + .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1, + .sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2, + .sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3, + .zq_config = MT41K128M16JT125K_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY, +}; + +#define OSC (V_OSCK / 1000000) +const struct dpll_params dpll_ddr = { + 400, OSC - 1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + int mpu_vdd; + int usb_cur_lim; + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + if (i2c_probe(TPS65217_CHIP_PM)) + return; + + /* + * Increase USB current limit to 1300mA or 1800mA and set + * the MPU voltage controller as needed. + */ + if (dpll_mpu_opp100.m == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_POWER_PATH, + usb_cur_lim, + TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set DCDC3 (CORE) voltage to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* + * Set LDO3 to 1.8V and LDO4 to 3.3V + */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + return &dpll_ddr; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41K128M16JT125K_IOCTRL_VALUE, + .cm1ioctl = MT41K128M16JT125K_IOCTRL_VALUE, + .cm2ioctl = MT41K128M16JT125K_IOCTRL_VALUE, + .dt0ioctl = MT41K128M16JT125K_IOCTRL_VALUE, + .dt1ioctl = MT41K128M16JT125K_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + config_ddr(400, &ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif + +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND + gpmc_init(); +#endif + return 0; +} diff --git a/board/bosch/guardian/board.h b/board/bosch/guardian/board.h new file mode 100644 index 0000000000..b301caf47f --- /dev/null +++ b/board/bosch/guardian/board.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * board.h + * + * Board header for Bosch Guardian + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Robert Bosch Power Tools GmbH + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/bosch/guardian/mux.c b/board/bosch/guardian/mux.c new file mode 100644 index 0000000000..708c3e7fdd --- /dev/null +++ b/board/bosch/guardian/mux.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * mux.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Robert Bosch Power Tools GmbH + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux adc_voltages_en[] = { + {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux asp_power_en[] = { + {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux switch_off_3v6_pin_mux[] = { + {OFFSET(mii1_txd0), (MODE(7) | PULLUP_EN)}, + /* + * The uart1 lines are made floating inputs, based on the Guardian + * A2 Sample Power Supply Schematics + */ + {OFFSET(uart1_rxd), (MODE(7) | PULLUDDIS)}, + {OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)}, + {-1}, +}; + +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, +#endif + {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, + {-1}, +}; +#endif + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#endif + configure_module_pin_mux(adc_voltages_en); + configure_module_pin_mux(asp_power_en); + configure_module_pin_mux(switch_off_3v6_pin_mux); +} diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index b0b29b3887..e8ec553f99 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -49,33 +49,6 @@ DECLARE_GLOBAL_DATA_PTR; #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) -#ifdef CONFIG_SPL_BUILD -#include <ns16550.h> -#include <dm/platform_data/spi_davinci.h> - -static const struct ns16550_platdata da850evm_serial = { - .base = DAVINCI_UART2_BASE, - .reg_shift = 2, - .clock = 150000000, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(da850evm_uart) = { - .name = "ns16550_serial", - .platdata = &da850evm_serial, -}; - -static const struct davinci_spi_platdata davinci_spi_data = { - .regs = (struct davinci_spi_regs *)0x01f0e000, - .num_cs = 4, -}; - -U_BOOT_DEVICE(davinci_spi) = { - .name = "davinci_spi", - .platdata = &davinci_spi_data, -}; -#endif - #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH static int get_mac_addr(u8 *addr) { diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 7b5fab7756..8f04911306 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -10,6 +10,9 @@ MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\ LENGTH = CONFIG_SPL_MAX_FOOTPRINT } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) ENTRY(_start) @@ -42,6 +45,15 @@ SECTIONS __rel_dyn_end = .; } >.sram + __image_copy_end = .; + + .end : + { + *(.__end) + } + + _image_binary_end = .; + .bss : { . = ALIGN(4); @@ -49,12 +61,5 @@ SECTIONS *(.bss*) . = ALIGN(4); __bss_end = .; - } >.sram - - __image_copy_end = .; - - .end : - { - *(.__end) - } + } >.sdram } diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 6f728398c3..10031a4801 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -37,6 +37,15 @@ DECLARE_GLOBAL_DATA_PTR; #define CPGMACSS_SW_RST (1 << 1) #define PHY_GPIO 30 +#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif +#endif /* * Routine: board_init diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c index e8f8f7ba5b..395904f8c8 100644 --- a/board/maxbcm/maxbcm.c +++ b/board/maxbcm/maxbcm.c @@ -95,7 +95,7 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) return &maxbcm_ddr_modes[0]; } -MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) { return &maxbcm_serdes_cfg[0]; } diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index 1129f4bf0c..1ce6e2eac1 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -8,57 +8,4 @@ */ #include <common.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> #include <asm/arch/rmobile.h> -#include <asm/arch/rcar-mstp.h> - -#define TSTR0 0x04 -#define TSTR0_STR0 0x01 - -static struct mstp_ctl mstptbl[] = { - { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA, - RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA }, - { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA, - RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA }, - { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA, - RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA }, - { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA, - RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA }, - { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA, - RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA }, - { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA, - RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA }, -#ifdef CONFIG_RCAR_GEN3 - { SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA, - RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA }, -#endif - { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA, - RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA }, - { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA, - RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA }, - { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA, - RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA }, - { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA, - RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA }, - { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA, - RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA }, -}; - -void arch_preboot_os(void) -{ - int i; - - /* stop TMU0 */ - mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0); - - /* Stop module clock */ - for (i = 0; i < ARRAY_SIZE(mstptbl); i++) { - mstp_setclrbits_le32((uintptr_t)mstptbl[i].s_addr, - mstptbl[i].s_dis, - mstptbl[i].s_ena); - mstp_setclrbits_le32((uintptr_t)mstptbl[i].r_addr, - mstptbl[i].r_dis, - mstptbl[i].r_ena); - } -} diff --git a/board/renesas/ulcb/MAINTAINERS b/board/renesas/ulcb/MAINTAINERS index e7cdc5217f..8549f543f4 100644 --- a/board/renesas/ulcb/MAINTAINERS +++ b/board/renesas/ulcb/MAINTAINERS @@ -5,3 +5,4 @@ F: board/renesas/ulcb/ F: include/configs/ulcb.h F: configs/r8a7795_ulcb_defconfig F: configs/r8a7796_ulcb_defconfig +F: configs/r8a77965_ulcb_defconfig diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index 81d6f8f6f2..9785107e56 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -97,6 +97,10 @@ int board_fit_config_name_match(const char *name) !strcmp(name, "r8a7796-m3ulcb-u-boot")) return 0; + if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) && + !strcmp(name, "r8a77965-m3nulcb-u-boot")) + return 0; + return -1; } #endif diff --git a/board/solidrun/clearfog/README b/board/solidrun/clearfog/README index a7bc0d4e23..0b0e98de90 100644 --- a/board/solidrun/clearfog/README +++ b/board/solidrun/clearfog/README @@ -17,6 +17,29 @@ $ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1 Please use the correct device node for your setup instead of "/dev/sdX" here! +Install U-Boot on eMMC: +----------------------- + +The ROM loads the bootloader from eMMC first boot partition at offset 0. This +is unlike load from SD card that is at offset 512. As a result, the offset of +the main U-Boot image on the eMMC boot partition changes. Set +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x140 for SPL to load U-Boot from +the correct location. + +To make SPL load the main U-Boot image from the eMMC boot partition enable +eMMC boot acknowledgement and boot partition with the following U-Boot +command: + + mmc partconf 0 1 1 0 + +Install U-Boot on eMMC boot partition from Linux running on Clearfog: + + echo 0 > /sys/block/mmcblk0boot0/force_ro + dd if=u-boot-spl.kwb of=/dev/mmcblk0boot0 + +Note that the SD card is not accessible when the Clearfog SOM has eMMC. +Consider initial boot from UART (see below). + Boot selection: --------------- diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 8e2f90fc68..7f96d2bb1c 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -341,6 +341,11 @@ M: FUKAUMI Naoki <naobsd@gmail.com> S: Maintained F: configs/Nintendo_NES_Classic_Edition_defconfig +OCEANIC 5205 5INMFD BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/oceanic_5205_5inmfd_defconfig + OLIMEX A20-SOM204 BOARD M: Stefan Mavrodiev <stefan@olimex.com> S: Maintained diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index dd6def5e6e..d42350319c 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -1,11 +1,15 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> + * Copyright (C) 2015-2019 Stefan Roese <sr@denx.de> */ #include <common.h> +#include <console.h> #include <i2c.h> #include <pci.h> +#if !defined(CONFIG_SPL_BUILD) +#include <bootcount.h> +#endif #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/cpu.h> @@ -42,6 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; #define STM_I2C_BUS 1 #define STM_I2C_ADDR 0x27 #define REBOOT_DELAY 1000 /* reboot-delay in ms */ +#define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */ /* DDR3 static configuration */ static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = { @@ -127,15 +132,15 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) return &board_ddr_modes[0]; } -MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) { return &theadorable_serdes_cfg[0]; } u8 board_sat_r_get(u8 dev_num, u8 reg) { - /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */ - return 0x01; + /* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */ + return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */ } int board_early_init_f(void) @@ -218,7 +223,7 @@ int board_eth_init(bd_t *bis) } #endif -#ifdef CONFIG_BOARD_LATE_INIT +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT) int board_late_init(void) { pci_dev_t bdf; @@ -232,6 +237,7 @@ int board_late_init(void) */ bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0); if (bdf == -1) { + unsigned long start_time = get_timer(0); u8 i2c_buf[8]; int ret; @@ -239,6 +245,28 @@ int board_late_init(void) bootcount = bootcount_load(); printf("Failed to find PLX PEX-switch (bootcount=%ld)\n", bootcount); + + /* + * The user can exit this boot-loop in the error case by + * hitting Ctrl-C. So wait some time for this key here. + */ + printf("Continue booting with Ctrl-C, otherwise rebooting\n"); + do { + /* Handle control-c and timeouts */ + if (ctrlc()) { + printf("PEX error boot-loop aborted!\n"); + return 0; + } + } while (get_timer(start_time) < ABORT_TIMEOUT); + + + /* + * At this stage the bootcounter has not been incremented + * yet. We need to do this manually here to get an actually + * working bootcounter in this error case. + */ + bootcount_inc(); + if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) { printf("Issuing power-switch via uC!\n"); diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index d67f94ad47..2c32b92d94 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -875,157 +875,55 @@ int board_late_init(void) } #endif -#ifndef CONFIG_DM_ETH - -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { +/* CPSW platdata */ +#if !CONFIG_IS_ENABLED(OF_CONTROL) +struct cpsw_slave_data slave_data[] = { { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, + .slave_reg_ofs = CPSW_SLAVE0_OFFSET, + .sliver_reg_ofs = CPSW_SLIVER0_OFFSET, + .phy_addr = 0, }, { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_addr = 1, + .slave_reg_ofs = CPSW_SLAVE1_OFFSET, + .sliver_reg_ofs = CPSW_SLIVER1_OFFSET, + .phy_addr = 1, }, }; -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, +struct cpsw_platform_data am335_eth_data = { .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, + .version = CPSW_CTRL_VERSION_2, + .bd_ram_ofs = CPSW_BD_OFFSET, + .ale_reg_ofs = CPSW_ALE_OFFSET, + .cpdma_reg_ofs = CPSW_CPDMA_OFFSET, + .mdio_div = CPSW_MDIO_DIV, + .host_port_reg_ofs = CPSW_HOST_PORT_OFFSET, .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, + .slaves = 2, + .slave_data = slave_data, .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, + .mac_control = 0x20, + .active_slave = 0, + .mdio_base = 0x4a101000, + .gmii_sel = 0x44e10650, + .phy_sel_compat = "ti,am3352-cpsw-phy-sel", + .syscon_addr = 0x44e10630, + .macid_sel_compat = "cpsw,am33xx", }; -#endif - -#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\ - defined(CONFIG_SPL_BUILD)) || \ - ((defined(CONFIG_DRIVER_TI_CPSW) || \ - defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ - !defined(CONFIG_SPL_BUILD)) -/* - * This function will: - * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr - * in the environment - * Perform fixups to the PHY present on certain boards. We only need this - * function in: - * - SPL with either CPSW or USB ethernet support - * - Full U-Boot, with either CPSW or USB ethernet - * Build in only these cases to avoid warnings about unused variables - * when we build an SPL that has neither option but full U-Boot will. - */ -int board_eth_init(bd_t *bis) -{ - int rv, n = 0; -#if defined(CONFIG_USB_ETHER) && \ - (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) - uint8_t mac_addr[6]; - uint32_t mac_hi, mac_lo; - - /* - * use efuse mac address for USB ethernet as we know that - * both CPSW and USB ethernet will never be active at the same time - */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; -#endif - - -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) - -#ifdef CONFIG_DRIVER_TI_CPSW - if (board_is_bone() || board_is_bone_lt() || board_is_bben() || - board_is_idk()) { - writel(MII_MODE_ENABLE, &cdev->miisel); - cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = - PHY_INTERFACE_MODE_MII; - } else if (board_is_icev2()) { - writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); - cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; - cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; - cpsw_slaves[0].phy_addr = 1; - cpsw_slaves[1].phy_addr = 3; - } else { - writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); - cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = - PHY_INTERFACE_MODE_RGMII; - } - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - n += rv; -#endif +struct eth_pdata cpsw_pdata = { + .iobase = 0x4a100000, + .phy_interface = 0, + .priv_pdata = &am335_eth_data, +}; - /* - * - * CPSW RGMII Internal Delay Mode is not supported in all PVT - * operating points. So we must set the TX clock delay feature - * in the AR8051 PHY. Since we only support a single ethernet - * device in U-Boot, we only do this for the first instance. - */ -#define AR8051_PHY_DEBUG_ADDR_REG 0x1d -#define AR8051_PHY_DEBUG_DATA_REG 0x1e -#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 -#define AR8051_RGMII_TX_CLK_DLY 0x100 - - if (board_is_evm_sk() || board_is_gp_evm() || board_is_bben()) { - const char *devname; - devname = miiphy_get_current_dev(); - - miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, - AR8051_DEBUG_RGMII_CLK_DLY_REG); - miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, - AR8051_RGMII_TX_CLK_DLY); - } -#endif -#if defined(CONFIG_USB_ETHER) && \ - (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) - if (is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("usbnet_devaddr", mac_addr); - - rv = usb_eth_initialize(bis); - if (rv < 0) - printf("Error %d registering USB_ETHER\n", rv); - else - n += rv; -#endif - return n; -} +U_BOOT_DEVICE(am335x_eth) = { + .name = "eth_cpsw", + .platdata = &cpsw_pdata, +}; #endif -#endif /* CONFIG_DM_ETH */ - #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 784b2b0191..52f5d6b11e 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/io.h> #include <spl.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -66,3 +67,16 @@ int board_fit_config_name_match(const char *name) return -1; } #endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + int ret; + + ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000", "sram@70000000"); + if (ret) + printf("%s: fixing up msmc ram failed %d\n", __func__, ret); + + return ret; +} +#endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 060c471032..179adc2fff 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -27,6 +27,7 @@ #include <environment.h> #include <dwc3-uboot.h> #include <dwc3-omap-uboot.h> +#include <i2c.h> #include <ti-usb-phy-uboot.h> #include <miiphy.h> @@ -55,6 +56,10 @@ DECLARE_GLOBAL_DATA_PTR; #define SYSINFO_BOARD_NAME_MAX_LEN 37 +/* I2C I/O Expander */ +#define NAND_PCF8575_ADDR 0x21 +#define NAND_PCF8575_I2C_BUS_NUM 0 + const struct omap_sysinfo sysinfo = { "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" }; @@ -777,6 +782,44 @@ void set_muxconf_regs(void) early_padconf, ARRAY_SIZE(early_padconf)); } +#if defined(CONFIG_NAND) +static int nand_sw_detect(void) +{ + int rc; + uchar data[2]; + struct udevice *dev; + + rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM, + NAND_PCF8575_ADDR, 0, &dev); + if (rc) + return -1; + + rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data)); + if (rc) + return -1; + + /* We are only interested in P10 and P11 on PCF8575 which is equal to + * bits 8 and 9. + */ + data[1] = data[1] & 0x3; + + /* Ensure only P11 is set and P10 is cleared. This ensures only + * NAND (P10) is configured and not NOR (P11) which are both low + * true signals. NAND and NOR settings should not be enabled at + * the same time. + */ + if (data[1] == 0x2) + return 0; + + return -1; +} +#else +int nand_sw_detect(void) +{ + return -1; +} +#endif + #ifdef CONFIG_IODELAY_RECALIBRATION void recalibrate_iodelay(void) { @@ -796,6 +839,19 @@ void recalibrate_iodelay(void) npads = ARRAY_SIZE(dra71x_core_padconf_array); iodelay = dra71_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); + /* If SW8 on the EVM is set to enable NAND then + * overwrite the pins used by VOUT3 with NAND. + */ + if (!nand_sw_detect()) { + delta_pads = dra71x_nand_padconf_array; + delta_npads = + ARRAY_SIZE(dra71x_nand_padconf_array); + } else { + delta_pads = dra71x_vout3_padconf_array; + delta_npads = + ARRAY_SIZE(dra71x_vout3_padconf_array); + } + } else if (board_is_dra72x_revc_or_later()) { delta_pads = dra72x_rgmii_padconf_array_revc; delta_npads = diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index f1f6bd5316..75da5cb608 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -220,22 +220,6 @@ const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = { }; const struct pad_conf_entry dra71x_core_padconf_array[] = { - {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ - {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ - {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ - {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */ - {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */ - {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */ - {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */ - {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */ - {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */ - {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */ - {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */ - {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */ - {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */ - {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */ - {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */ - {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */ {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */ {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */ {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */ @@ -370,6 +354,50 @@ const struct pad_conf_entry dra71x_core_padconf_array[] = { {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */ }; +const struct pad_conf_entry dra71x_vout3_padconf_array[] = { + {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ + {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ + {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ + {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */ + {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */ + {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */ + {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */ + {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */ + {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */ + {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */ + {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */ + {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */ + {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */ + {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */ + {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */ + {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */ +}; + +const struct pad_conf_entry dra71x_nand_padconf_array[] = { + {GPMC_AD0, (M0 | PIN_INPUT)}, /* gpmc_ad0.gpmc_ad0 */ + {GPMC_AD1, (M0 | PIN_INPUT)}, /* gpmc_ad1.gpmc_ad1 */ + {GPMC_AD2, (M0 | PIN_INPUT)}, /* gpmc_ad2.gpmc_ad2 */ + {GPMC_AD3, (M0 | PIN_INPUT)}, /* gpmc_ad3.gpmc_ad3 */ + {GPMC_AD4, (M0 | PIN_INPUT)}, /* gpmc_ad4.gpmc_ad4 */ + {GPMC_AD5, (M0 | PIN_INPUT)}, /* gpmc_ad5.gpmc_ad5 */ + {GPMC_AD6, (M0 | PIN_INPUT)}, /* gpmc_ad6.gpmc_ad6 */ + {GPMC_AD7, (M0 | PIN_INPUT)}, /* gpmc_ad7.gpmc_ad7 */ + {GPMC_AD8, (M0 | PIN_INPUT)}, /* gpmc_ad8.gpmc_ad8 */ + {GPMC_AD9, (M0 | PIN_INPUT)}, /* gpmc_ad9.gpmc_ad9 */ + {GPMC_AD10, (M0 | PIN_INPUT)}, /* gpmc_ad10.gpmc_ad10 */ + {GPMC_AD11, (M0 | PIN_INPUT)}, /* gpmc_ad11.gpmc_ad11 */ + {GPMC_AD12, (M0 | PIN_INPUT)}, /* gpmc_ad12.gpmc_ad12 */ + {GPMC_AD13, (M0 | PIN_INPUT)}, /* gpmc_ad13.gpmc_ad13 */ + {GPMC_AD14, (M0 | PIN_INPUT)}, /* gpmc_ad14.gpmc_ad14 */ + {GPMC_AD15, (M0 | PIN_INPUT)}, /* gpmc_ad15.gpmc_ad15 */ + {GPMC_CS0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpmc_cs0 */ + {GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLDOWN)}, /* gpmc_advn_ale.gpmc_advn_ale */ + {GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpmc_oen_ren */ + {GPMC_WEN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpmc_wen */ + {GPMC_BEN0, (M0 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.gpmc_ben0 */ + {GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpmc_wait0 */ +}; + const struct pad_conf_entry early_padconf[] = { {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */ diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 39a782e479..6d0fc21c67 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -315,6 +315,21 @@ int embedded_dtb_select(void) BIT(9)); setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, BIT(9)); + } else if (board_is_k2g_ice()) { + /* GBE Phy workaround. For Phy to latch the input + * configuration, a GPIO reset is asserted at the + * Phy reset pin to latch configuration correctly after SoC + * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE + * board. Just do a low to high transition. + */ + clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET, + BIT(10)); + setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET, + BIT(10)); + /* Delay just to get a transition to high */ + udelay(100); + setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET, + BIT(10)); } return 0; diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h index 706fb7e838..89c49f9e4f 100644 --- a/board/ti/ks2_evm/mux-k2g.h +++ b/board/ti/ks2_evm/mux-k2g.h @@ -125,21 +125,23 @@ struct pin_cfg k2g_evm_pin_cfg[] = { { 70, MODE(0) }, /* SOC_MMC1_SDWP */ { 71, MODE(0) }, /* MMC1POW TP124 */ - /* RGMII */ - { 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */ - { 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */ - { 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */ - { 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */ - { 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */ - { 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */ - { 85, MODE(1) }, /* SOC_RGMII_TXCLK */ - { 91, MODE(1) }, /* SOC_RGMII_TXD3 */ - { 92, MODE(1) }, /* SOC_RGMII_TXD2 */ - { 93, MODE(1) }, /* SOC_RGMII_TXD1 */ - { 94, MODE(1) }, /* SOC_RGMII_TXD0 */ - { 95, MODE(1) }, /* SOC_RGMII_TXCTL */ - { 98, MODE(0) }, /* SOC_MDIO_DATA */ - { 99, MODE(0) }, /* SOC_MDIO_CLK */ + /* EMAC */ + { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */ + { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */ + { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */ + { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */ + { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */ + { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */ + { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */ + { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */ + { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */ + { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */ + { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */ + { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */ + + /* MDIO */ + { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */ + { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */ /* PWM */ { 73, MODE(4) }, /* SOC_EHRPWM3A */ @@ -346,6 +348,25 @@ struct pin_cfg k2g_ice_evm_pin_cfg[] = { { 133, MODE(0) }, /* SOC_QSPI_D2 */ { 134, MODE(0) }, /* SOC_QSPI_D3 */ { 135, MODE(0) }, /* SOC_QSPI_CSN0 */ + + /* EMAC */ + { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */ + { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */ + { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */ + { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */ + { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */ + { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */ + { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */ + { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */ + { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */ + { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */ + { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */ + { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */ + + /* MDIO */ + { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */ + { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */ + { MAX_PIN_N, } }; |