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-rw-r--r--board/AndesTech/ax25-ae350/Kconfig1
-rw-r--r--board/emulation/qemu-riscv/Kconfig1
-rw-r--r--board/gardena/smart-gateway-at91sam/Kconfig12
-rw-r--r--board/gardena/smart-gateway-at91sam/MAINTAINERS7
-rw-r--r--board/gardena/smart-gateway-at91sam/Makefile7
-rw-r--r--board/gardena/smart-gateway-at91sam/board.c59
-rw-r--r--board/gardena/smart-gateway-at91sam/spl.c135
-rw-r--r--board/renesas/rcar-common/common.c53
-rw-r--r--board/renesas/ulcb/MAINTAINERS1
-rw-r--r--board/renesas/ulcb/ulcb.c4
-rw-r--r--board/ronetix/pm9g45/pm9g45.c10
-rw-r--r--board/sifive/fu540/Kconfig1
12 files changed, 233 insertions, 58 deletions
diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index 44cb302f70..5e682b679d 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -24,5 +24,6 @@ config ENV_OFFSET
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
+ imply SMP
endif
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 88d07d568e..cf057e7de6 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -34,5 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply BOARD_LATE_INIT
imply OF_BOARD_SETUP
imply SIFIVE_SERIAL
+ imply SMP
endif
diff --git a/board/gardena/smart-gateway-at91sam/Kconfig b/board/gardena/smart-gateway-at91sam/Kconfig
new file mode 100644
index 0000000000..ea2b5ff4e6
--- /dev/null
+++ b/board/gardena/smart-gateway-at91sam/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GARDENA_SMART_GATEWAY_AT91SAM
+
+config SYS_BOARD
+ default "smart-gateway-at91sam"
+
+config SYS_VENDOR
+ default "gardena"
+
+config SYS_CONFIG_NAME
+ default "gardena-smart-gateway-at91sam"
+
+endif
diff --git a/board/gardena/smart-gateway-at91sam/MAINTAINERS b/board/gardena/smart-gateway-at91sam/MAINTAINERS
new file mode 100644
index 0000000000..a5e4c71b82
--- /dev/null
+++ b/board/gardena/smart-gateway-at91sam/MAINTAINERS
@@ -0,0 +1,7 @@
+GARDENA_SMART_GATEWAY_AT91SAM BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/gardena/smart-gateway-at91sam/
+F: include/configs/gardena-smart-gateway-at91sam.h
+F: configs/gardena-smart-gateway-at91sam_defconfig
+F: arch/arm/dts/gardena-smart-gateway-at91sam.dts
diff --git a/board/gardena/smart-gateway-at91sam/Makefile b/board/gardena/smart-gateway-at91sam/Makefile
new file mode 100644
index 0000000000..a2ed79fd06
--- /dev/null
+++ b/board/gardena/smart-gateway-at91sam/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += board.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/gardena/smart-gateway-at91sam/board.c b/board/gardena/smart-gateway-at91sam/board.c
new file mode 100644
index 0000000000..6a1389eb05
--- /dev/null
+++ b/board/gardena/smart-gateway-at91sam/board.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ * Copyright (C) 2019 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <led.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void at91_prepare_cpu_var(void)
+{
+ env_set("cpu", get_cpu_name());
+}
+
+int board_late_init(void)
+{
+ at91_prepare_cpu_var();
+
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ at91_seriald_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}
diff --git a/board/gardena/smart-gateway-at91sam/spl.c b/board/gardena/smart-gateway-at91sam/spl.c
new file mode 100644
index 0000000000..3ab6760df7
--- /dev/null
+++ b/board/gardena/smart-gateway-at91sam/spl.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ * Copyright (C) 2019 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <spl.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+static void at91sam9x5ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+
+ /* NAND flash on D16 */
+ csa |= AT91_MATRIX_NFD0_ON_D16;
+
+ /* Configure IO drive */
+ csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ &smc->cs[3].mode);
+
+ at91_periph_clk_enable(ATMEL_ID_PIOCD);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
+}
+
+void at91_spl_board_init(void)
+{
+ at91sam9x5ek_nand_hw_init();
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
+
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct atmel_mpddrc_config ddr2;
+ unsigned long csa;
+
+ ddr2_conf(&ddr2);
+
+ /* Enable DDR2 clock */
+ writel(AT91_PMC_DDR, &pmc->scer);
+
+ /* Chip select 1 is for DDR2/SDRAM */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+ csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+ csa |= AT91_MATRIX_EBI_DBPD_OFF;
+ csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+ writel(csa, &matrix->ebicsa);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
+}
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c
index 1129f4bf0c..1ce6e2eac1 100644
--- a/board/renesas/rcar-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -8,57 +8,4 @@
*/
#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
#include <asm/arch/rmobile.h>
-#include <asm/arch/rcar-mstp.h>
-
-#define TSTR0 0x04
-#define TSTR0_STR0 0x01
-
-static struct mstp_ctl mstptbl[] = {
- { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
- RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
- { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
- RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
- { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
- RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
- { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
- RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
- { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
- RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
- { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
- RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
-#ifdef CONFIG_RCAR_GEN3
- { SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA,
- RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA },
-#endif
- { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
- RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
- { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
- RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
- { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
- RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
- { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
- RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
- { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
- RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
-};
-
-void arch_preboot_os(void)
-{
- int i;
-
- /* stop TMU0 */
- mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
-
- /* Stop module clock */
- for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
- mstp_setclrbits_le32((uintptr_t)mstptbl[i].s_addr,
- mstptbl[i].s_dis,
- mstptbl[i].s_ena);
- mstp_setclrbits_le32((uintptr_t)mstptbl[i].r_addr,
- mstptbl[i].r_dis,
- mstptbl[i].r_ena);
- }
-}
diff --git a/board/renesas/ulcb/MAINTAINERS b/board/renesas/ulcb/MAINTAINERS
index e7cdc5217f..8549f543f4 100644
--- a/board/renesas/ulcb/MAINTAINERS
+++ b/board/renesas/ulcb/MAINTAINERS
@@ -5,3 +5,4 @@ F: board/renesas/ulcb/
F: include/configs/ulcb.h
F: configs/r8a7795_ulcb_defconfig
F: configs/r8a7796_ulcb_defconfig
+F: configs/r8a77965_ulcb_defconfig
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index 81d6f8f6f2..9785107e56 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -97,6 +97,10 @@ int board_fit_config_name_match(const char *name)
!strcmp(name, "r8a7796-m3ulcb-u-boot"))
return 0;
+ if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
+ !strcmp(name, "r8a77965-m3nulcb-u-boot"))
+ return 0;
+
return -1;
}
#endif
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index 17e520a9e9..c5d28c61e2 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -124,7 +124,7 @@ int board_init(void)
/* arch number of AT91SAM9M10G45EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
/* adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
pm9g45_nand_hw_init();
@@ -139,15 +139,15 @@ int board_init(void)
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
- PHYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
return 0;
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 6be3d88144..f46437901d 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -38,5 +38,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply PHY_LIB
imply PHY_MSCC
imply SIFIVE_SERIAL
+ imply SMP
endif
generated by cgit (git 2.34.1) at 2025-01-31 00:32:38 +0000