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-rw-r--r--board/mscc/ocelot/ocelot.c24
-rw-r--r--board/mscc/serval/Kconfig14
-rw-r--r--board/mscc/serval/Makefile3
-rw-r--r--board/mscc/serval/serval.c74
-rw-r--r--board/mscc/servalt/Kconfig14
-rw-r--r--board/mscc/servalt/Makefile3
-rw-r--r--board/mscc/servalt/servalt.c52
-rw-r--r--board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c34
-rw-r--r--board/xilinx/zynqmp/cmds.c10
-rw-r--r--board/xilinx/zynqmp/zynqmp.c6
10 files changed, 211 insertions, 23 deletions
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index 0f7a532158..532d06f000 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -10,6 +10,7 @@
#include <environment.h>
#include <spi.h>
#include <led.h>
+#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -18,6 +19,29 @@ enum {
BOARD_TYPE_PCB123,
};
+void mscc_switch_reset(bool enter)
+{
+ /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
+ mscc_gpio_set_alternate(19, 2);
+
+ debug("applying SwC reset\n");
+
+ writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+ if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
+ PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
+ pr_err("Tiemout while waiting for switch reset\n");
+
+ /*
+ * Reset GPIO19 mode back as regular GPIO, output, high (DDR
+ * not reset) (Order is important)
+ */
+ setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+ writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
+ mscc_gpio_set_alternate(19, 0);
+}
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
diff --git a/board/mscc/serval/Kconfig b/board/mscc/serval/Kconfig
new file mode 100644
index 0000000000..64f1c683e4
--- /dev/null
+++ b/board/mscc/serval/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+ default "mscc"
+
+if SOC_SERVAL
+
+config SYS_BOARD
+ default "serval"
+
+config SYS_CONFIG_NAME
+ default "serval"
+
+endif
diff --git a/board/mscc/serval/Makefile b/board/mscc/serval/Makefile
new file mode 100644
index 0000000000..c7ba56e951
--- /dev/null
+++ b/board/mscc/serval/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_SERVAL) := serval.o
diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c
new file mode 100644
index 0000000000..24ee5e528d
--- /dev/null
+++ b/board/mscc/serval/serval.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <led.h>
+
+enum {
+ BOARD_TYPE_PCB106 = 0xAABBCD00,
+ BOARD_TYPE_PCB105,
+};
+
+int board_early_init_r(void)
+{
+ /* Prepare SPI controller to be used in master mode */
+ writel(0, BASE_CFG + ICPU_SW_MODE);
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+ /* LED setup */
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
+
+static void do_board_detect(void)
+{
+ u16 gpio_in_reg;
+
+ /* Set MDIO and MDC */
+ mscc_gpio_set_alternate(9, 2);
+ mscc_gpio_set_alternate(10, 2);
+
+ /* Set GPIO page */
+ mscc_phy_wr(1, 16, 31, 0x10);
+ if (!mscc_phy_rd(1, 16, 15, &gpio_in_reg)) {
+ if (gpio_in_reg & 0x200)
+ gd->board_type = BOARD_TYPE_PCB106;
+ else
+ gd->board_type = BOARD_TYPE_PCB105;
+ mscc_phy_wr(1, 16, 15, 0);
+ } else {
+ gd->board_type = BOARD_TYPE_PCB105;
+ }
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_PCB106 &&
+ strcmp(name, "serval_pcb106") == 0)
+ return 0;
+
+ if (gd->board_type == BOARD_TYPE_PCB105 &&
+ strcmp(name, "serval_pcb105") == 0)
+ return 0;
+
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ do_board_detect();
+ fdtdec_setup();
+
+ return 0;
+}
+#endif
diff --git a/board/mscc/servalt/Kconfig b/board/mscc/servalt/Kconfig
new file mode 100644
index 0000000000..61140f89bf
--- /dev/null
+++ b/board/mscc/servalt/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+ default "mscc"
+
+if SOC_SERVALT
+
+config SYS_BOARD
+ default "servalt"
+
+config SYS_CONFIG_NAME
+ default "servalt"
+
+endif
diff --git a/board/mscc/servalt/Makefile b/board/mscc/servalt/Makefile
new file mode 100644
index 0000000000..9a37eeabaf
--- /dev/null
+++ b/board/mscc/servalt/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_SERVALT) := servalt.o
diff --git a/board/mscc/servalt/servalt.c b/board/mscc/servalt/servalt.c
new file mode 100644
index 0000000000..566f9765c2
--- /dev/null
+++ b/board/mscc/servalt/servalt.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <led.h>
+
+enum {
+ BOARD_TYPE_PCB116 = 0xAABBCE00,
+};
+
+int board_early_init_r(void)
+{
+ /* Prepare SPI controller to be used in master mode */
+ writel(0, BASE_CFG + ICPU_SW_MODE);
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+ /* LED setup */
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
+
+static void do_board_detect(void)
+{
+ gd->board_type = BOARD_TYPE_PCB116; /* ServalT */
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (gd->board_type == BOARD_TYPE_PCB116 &&
+ strcmp(name, "servalt_pcb116") == 0)
+ return 0;
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+ do_board_detect();
+ fdtdec_setup();
+
+ return 0;
+}
+#endif
diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
index c1cc1df23d..d90a350d3f 100644
--- a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
+++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
@@ -8,8 +8,8 @@
static unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA240U),
+ EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00030000U),
EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
@@ -24,8 +24,8 @@ static unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
+ EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
@@ -37,20 +37,18 @@ static unsigned long ps7_pll_init_data_3_0[] = {
static unsigned long ps7_clock_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
- EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+ EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
- EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
- EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
- EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
- EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
- EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
+ EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+ EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A03U),
+ EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00200500U),
+ EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+ EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
@@ -88,7 +86,7 @@ static unsigned long ps7_ddr_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB52U),
EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c
index 3e039ccb13..321670d4e3 100644
--- a/board/xilinx/zynqmp/cmds.c
+++ b/board/xilinx/zynqmp/cmds.c
@@ -174,11 +174,11 @@ static char zynqmp_help_text[] =
"zynqmp mmio_write address mask value - write value after masking to\n"
" address\n"
#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
- "zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n"
- " initialized before accessing to avoid ECC\n"
- " errors. mode specifies in which mode TCM has\n"
- " to be initialized. Supported modes will be\n"
- " lock(0)/split(1)\n"
+ "zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n"
+ " initialized before accessing to avoid ECC\n"
+ " errors. mode specifies in which mode TCM has\n"
+ " to be initialized. Supported modes will be\n"
+ " lock(0)/split(1)\n"
#endif
;
#endif
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 13c404b6ef..41e88b03f9 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -489,6 +489,7 @@ void reset_cpu(ulong addr)
{
}
+#if defined(CONFIG_BOARD_LATE_INIT)
static const struct {
u32 bit;
const char *name;
@@ -587,6 +588,8 @@ int board_late_init(void)
case SD_MODE:
puts("SD_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
+ "mmc@ff160000", &dev) &&
+ uclass_get_device_by_name(UCLASS_MMC,
"sdhci@ff160000", &dev)) {
puts("Boot from SD0 but without SD0 enabled!\n");
return -1;
@@ -603,6 +606,8 @@ int board_late_init(void)
case SD_MODE1:
puts("SD_MODE1\n");
if (uclass_get_device_by_name(UCLASS_MMC,
+ "mmc@ff170000", &dev) &&
+ uclass_get_device_by_name(UCLASS_MMC,
"sdhci@ff170000", &dev)) {
puts("Boot from SD1 but without SD1 enabled!\n");
return -1;
@@ -655,6 +660,7 @@ int board_late_init(void)
return 0;
}
+#endif
int checkboard(void)
{
generated by cgit (git 2.34.1) at 2025-01-19 07:58:44 +0000