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-rw-r--r--board/dbau1x00/lowlevel_init.S1
-rw-r--r--board/gth2/gth2.c2
-rw-r--r--board/gth2/lowlevel_init.S1
-rw-r--r--board/incaip/incaip.c2
-rw-r--r--board/incaip/lowlevel_init.S1
-rw-r--r--board/pb1x00/lowlevel_init.S1
-rw-r--r--board/purple/lowlevel_init.S1
-rw-r--r--board/purple/purple.c14
-rw-r--r--board/qemu-mips/lowlevel_init.S1
-rw-r--r--board/tb0229/lowlevel_init.S1
-rw-r--r--board/tb0229/vr4131-pci.c56
11 files changed, 37 insertions, 44 deletions
diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S
index 27b51f73f0..13e6bfcf33 100644
--- a/board/dbau1x00/lowlevel_init.S
+++ b/board/dbau1x00/lowlevel_init.S
@@ -1,7 +1,6 @@
/* Memory sub-system initialization code */
#include <config.h>
-#include <version.h>
#include <asm/regdef.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
index 9bc4d3fe5e..3e56678c08 100644
--- a/board/gth2/gth2.c
+++ b/board/gth2/gth2.c
@@ -36,7 +36,7 @@ static int wdi_status = 0;
#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
-#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096))
+#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
void inline log_serial_char(char c){
char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S
index bf615c1bb1..4c4f0ebd2d 100644
--- a/board/gth2/lowlevel_init.S
+++ b/board/gth2/lowlevel_init.S
@@ -1,7 +1,6 @@
/* Memory sub-system initialization code */
#include <config.h>
-#include <version.h>
#include <asm/regdef.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index c624b3d82e..dc513739fa 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -63,7 +63,7 @@ long int initdram(int board_type)
/* Can't probe for RAM size unless we are running from Flash.
*/
- if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1))
+ if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
{
return max_sdram_size();
}
diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S
index 08f7f211f7..fe525ec70e 100644
--- a/board/incaip/lowlevel_init.S
+++ b/board/incaip/lowlevel_init.S
@@ -23,7 +23,6 @@
*/
#include <config.h>
-#include <version.h>
#include <asm/regdef.h>
diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S
index 98bb394acb..b145e438f0 100644
--- a/board/pb1x00/lowlevel_init.S
+++ b/board/pb1x00/lowlevel_init.S
@@ -1,7 +1,6 @@
/* Memory sub-system initialization code */
#include <config.h>
-#include <version.h>
#include <asm/regdef.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S
index b9d03fc15e..1bd3edb815 100644
--- a/board/purple/lowlevel_init.S
+++ b/board/purple/lowlevel_init.S
@@ -23,7 +23,6 @@
*/
#include <config.h>
-#include <version.h>
#include <asm/regdef.h>
#define MC_IOGP 0xBF800800
diff --git a/board/purple/purple.c b/board/purple/purple.c
index 89cb906972..72d5734427 100644
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -85,16 +85,16 @@ static void sdram_timing_init (ulong size)
while (p4 < 32 && done == 0) {
WRITE_MC_IOGP_1;
- for (addr = KSEG1 + 0x4000;
- addr < KSEG1ADDR (size);
+ for (addr = CKSEG1 + 0x4000;
+ addr < CKSEG1ADDR (size);
addr = addr + 4) {
*(uint *) addr = 0xaa55aa55;
}
pass = 1;
- for (addr = KSEG1 + 0x4000;
- addr < KSEG1ADDR (size) && pass == 1;
+ for (addr = CKSEG1 + 0x4000;
+ addr < CKSEG1ADDR (size) && pass == 1;
addr = addr + 4) {
if (*(uint *) addr != 0xaa55aa55)
pass = 0;
@@ -138,7 +138,7 @@ long int initdram(int board_type)
ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
void (* sdram_init) (ulong);
- sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init);
+ sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
sdram_init(0x10000);
@@ -260,14 +260,14 @@ void copy_code (ulong dest_addr)
/* flush caches
*/
- start = KSEG0;
+ start = CKSEG0;
end = start + CFG_DCACHE_SIZE;
while(start < end) {
cache_unroll(start,Index_Writeback_Inv_D);
start += CFG_CACHELINE_SIZE;
}
- start = KSEG0;
+ start = CKSEG0;
end = start + CFG_ICACHE_SIZE;
while(start < end) {
cache_unroll(start,Index_Invalidate_I);
diff --git a/board/qemu-mips/lowlevel_init.S b/board/qemu-mips/lowlevel_init.S
index 836e0271a1..b0f7072701 100644
--- a/board/qemu-mips/lowlevel_init.S
+++ b/board/qemu-mips/lowlevel_init.S
@@ -1,7 +1,6 @@
/* Memory sub-system initialization code */
#include <config.h>
-#include <version.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
diff --git a/board/tb0229/lowlevel_init.S b/board/tb0229/lowlevel_init.S
index df318067b9..5fce8567d7 100644
--- a/board/tb0229/lowlevel_init.S
+++ b/board/tb0229/lowlevel_init.S
@@ -10,7 +10,6 @@
*/
#include <config.h>
-#include <version.h>
#include <asm/regdef.h>
diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c
index 0ee4bf30ea..4c9192341e 100644
--- a/board/tb0229/vr4131-pci.c
+++ b/board/tb0229/vr4131-pci.c
@@ -13,34 +13,34 @@
#include <pci.h>
#include <asm/addrspace.h>
-#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00)
-#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04)
-#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08)
-#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c)
-#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10)
-#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14)
-#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18)
-#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c)
-#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24)
-#define VR4131_INTCNTSTAREG (volatile unsigned int*)(KSEG1 + 0x0f000c28)
-#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c)
-#define VR4131_PCIRECONTREG (volatile unsigned int*)(KSEG1 + 0x0f000c30)
-#define VR4131_PCIENREG (volatile unsigned int*)(KSEG1 + 0x0f000c34)
-#define VR4131_PCICLKSELREG (volatile unsigned int*)(KSEG1 + 0x0f000c38)
-#define VR4131_PCITRDYREG (volatile unsigned int*)(KSEG1 + 0x0f000c3c)
-#define VR4131_PCICLKRUNREG (volatile unsigned int*)(KSEG1 + 0x0f000c60)
-#define VR4131_PCIHOSTCONFIG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
-#define VR4131_VENDORIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
-#define VR4131_DEVICEIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
-#define VR4131_COMMANDREG (volatile unsigned int*)(KSEG1 + 0x0f000d04)
-#define VR4131_STATUSREG (volatile unsigned int*)(KSEG1 + 0x0f000d04)
-#define VR4131_REVREG (volatile unsigned int*)(KSEG1 + 0x0f000d08)
-#define VR4131_CLASSREG (volatile unsigned int*)(KSEG1 + 0x0f000d08)
-#define VR4131_CACHELSREG (volatile unsigned int*)(KSEG1 + 0x0f000d0c)
-#define VR4131_LATTIMERRG (volatile unsigned int*)(KSEG1 + 0x0f000d0c)
-#define VR4131_MAILBAREG (volatile unsigned int*)(KSEG1 + 0x0f000d10)
-#define VR4131_PCIMBA1REG (volatile unsigned int*)(KSEG1 + 0x0f000d14)
-#define VR4131_PCIMBA2REG (volatile unsigned int*)(KSEG1 + 0x0f000d18)
+#define VR4131_PCIMMAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c00)
+#define VR4131_PCIMMAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c04)
+#define VR4131_PCITAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c08)
+#define VR4131_PCITAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c0c)
+#define VR4131_PCIMIOAWREG (volatile unsigned int *)(CKSEG1 + 0x0f000c10)
+#define VR4131_PCICONFDREG (volatile unsigned int *)(CKSEG1 + 0x0f000c14)
+#define VR4131_PCICONFAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c18)
+#define VR4131_PCIMAILREG (volatile unsigned int *)(CKSEG1 + 0x0f000c1c)
+#define VR4131_BUSERRADREG (volatile unsigned int *)(CKSEG1 + 0x0f000c24)
+#define VR4131_INTCNTSTAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c28)
+#define VR4131_PCIEXACCREG (volatile unsigned int *)(CKSEG1 + 0x0f000c2c)
+#define VR4131_PCIRECONTREG (volatile unsigned int *)(CKSEG1 + 0x0f000c30)
+#define VR4131_PCIENREG (volatile unsigned int *)(CKSEG1 + 0x0f000c34)
+#define VR4131_PCICLKSELREG (volatile unsigned int *)(CKSEG1 + 0x0f000c38)
+#define VR4131_PCITRDYREG (volatile unsigned int *)(CKSEG1 + 0x0f000c3c)
+#define VR4131_PCICLKRUNREG (volatile unsigned int *)(CKSEG1 + 0x0f000c60)
+#define VR4131_PCIHOSTCONFIG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
+#define VR4131_VENDORIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
+#define VR4131_DEVICEIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
+#define VR4131_COMMANDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04)
+#define VR4131_STATUSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04)
+#define VR4131_REVREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08)
+#define VR4131_CLASSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08)
+#define VR4131_CACHELSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
+#define VR4131_LATTIMERRG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
+#define VR4131_MAILBAREG (volatile unsigned int *)(CKSEG1 + 0x0f000d10)
+#define VR4131_PCIMBA1REG (volatile unsigned int *)(CKSEG1 + 0x0f000d14)
+#define VR4131_PCIMBA2REG (volatile unsigned int *)(CKSEG1 + 0x0f000d18)
/*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */
/*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */
generated by cgit (git 2.34.1) at 2024-12-26 01:42:38 +0000