diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/bachmann/ot1200/ot1200.c | 4 | ||||
| -rw-r--r-- | board/congatec/cgtqmx6eval/cgtqmx6eval.c | 2 | ||||
| -rw-r--r-- | board/davinci/da8xxevm/Kconfig | 2 | ||||
| -rw-r--r-- | board/freescale/m5253demo/flash.c | 4 | ||||
| -rw-r--r-- | board/freescale/mx6slevk/mx6slevk.c | 2 | ||||
| -rw-r--r-- | board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 2 | ||||
| -rw-r--r-- | board/gateworks/gw_ventana/common.c | 27 | ||||
| -rw-r--r-- | board/gateworks/gw_ventana/gw_ventana.c | 3 | ||||
| -rw-r--r-- | board/gdsys/p1022/controlcenterd-id.c | 49 | ||||
| -rw-r--r-- | board/phytec/pcm058/pcm058.c | 9 | ||||
| -rw-r--r-- | board/socrates/socrates.c | 2 | ||||
| -rw-r--r-- | board/ti/am335x/board.c | 343 | ||||
| -rw-r--r-- | board/ti/am43xx/board.c | 21 | ||||
| -rw-r--r-- | board/toradex/apalis_imx6/apalis_imx6.c | 47 | ||||
| -rw-r--r-- | board/toradex/colibri_imx7/colibri_imx7.c | 16 |
15 files changed, 256 insertions, 277 deletions
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index eeced7943e..c0a8b6423e 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -273,10 +273,6 @@ int board_mmc_init(bd_t *bis) return 0; } -static iomux_v3_cfg_t const pwm_pad[] = { - MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM), -}; - static void leds_on(void) { /* turn on all possible leds connected via GPIO expander */ diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index a4a602943e..24956a8a94 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -71,6 +71,7 @@ static iomux_v3_cfg_t const uart2_pads[] = { IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; +#ifndef CONFIG_SPL_BUILD static iomux_v3_cfg_t const usdhc2_pads[] = { IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -94,6 +95,7 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; +#endif static iomux_v3_cfg_t const usdhc4_pads[] = { IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig index 7d0de1d0fa..0935abfd42 100644 --- a/board/davinci/da8xxevm/Kconfig +++ b/board/davinci/da8xxevm/Kconfig @@ -22,4 +22,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "omapl138_lcdk" +source "board/ti/common/Kconfig" + endif diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c index 071701d234..099decabb8 100644 --- a/board/freescale/m5253demo/flash.c +++ b/board/freescale/m5253demo/flash.c @@ -31,7 +31,7 @@ typedef volatile unsigned short FLASH_PORT_WIDTHV; ulong flash_get_size(FPWV * addr, flash_info_t * info); int flash_get_offsets(ulong base, flash_info_t * info); int write_word(flash_info_t * info, FPWV * dest, u16 data); -void inline spin_wheel(void); +static inline void spin_wheel(void); flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; @@ -439,7 +439,7 @@ int write_word(flash_info_t * info, FPWV * dest, u16 data) return (res); } -void inline spin_wheel(void) +static inline void spin_wheel(void) { static int p = 0; static char w[] = "\\/-"; diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index d49543315b..228514b106 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -66,6 +66,7 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#ifdef CONFIG_SPL_BUILD static iomux_v3_cfg_t const usdhc1_pads[] = { /* 8 bit SD */ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -106,6 +107,7 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { /*CD pin*/ MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +#endif static iomux_v3_cfg_t const fec_pads[] = { MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index b28ce10495..a5746fe086 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -225,6 +225,7 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#ifndef CONFIG_SPL_BUILD static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -240,6 +241,7 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { /* RST_B */ MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +#endif /* * mx6ul_14x14_evk board default supports sd card. If want to use diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index d27bd57648..186eb18048 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -180,33 +180,6 @@ void setup_ventana_i2c(void) /* * Baseboard specific GPIO */ - -/* prototype */ -static iomux_v3_cfg_t const gwproto_gpio_pads[] = { - /* RS232_EN# */ - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* RS485_EN */ - IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), - /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), - /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* DIOI2C_DIS# */ - IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* PCICK_SSON */ - IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), -}; - static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index dc8cd883e9..c4c2d23532 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -76,7 +76,7 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), }; -/* NAND */ +#ifdef CONFIG_CMD_NAND static iomux_v3_cfg_t const nfc_pads[] = { IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), @@ -95,7 +95,6 @@ static iomux_v3_cfg_t const nfc_pads[] = { IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; -#ifdef CONFIG_CMD_NAND static void setup_gpmi_nand(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c index 1648f13340..db8a917563 100644 --- a/board/gdsys/p1022/controlcenterd-id.c +++ b/board/gdsys/p1022/controlcenterd-id.c @@ -156,33 +156,8 @@ static const uint8_t prg_stage1_prepare[] = { 0x81, 0x2e, 0x30, 0x00, /* opcode: LOAD PCR3, f3 */ }; -static const uint8_t prg_stage2_prepare[] = { - 0x00, 0x80, 0x00, 0x00, /* opcode: SYNC PCR0 */ - 0x00, 0x84, 0x00, 0x00, /* opcode: SYNC PCR1 */ - 0x00, 0x88, 0x00, 0x00, /* opcode: SYNC PCR2 */ - 0x00, 0x8c, 0x00, 0x00, /* opcode: SYNC PCR3 */ - 0x00, 0x90, 0x00, 0x00, /* opcode: SYNC PCR4 */ -}; - -static const uint8_t prg_stage2_success[] = { - 0x81, 0x02, 0x40, 0x14, /* opcode: LOAD PCR4, #<20B data> */ - 0x48, 0xfd, 0x95, 0x17, 0xe7, 0x54, 0x6b, 0x68, /* data */ - 0x92, 0x31, 0x18, 0x05, 0xf8, 0x58, 0x58, 0x3c, /* data */ - 0xe4, 0xd2, 0x81, 0xe0, /* data */ -}; - -static const uint8_t prg_stage_fail[] = { - 0x81, 0x01, 0x00, 0x14, /* opcode: LOAD v0, #<20B data> */ - 0xc0, 0x32, 0xad, 0xc1, 0xff, 0x62, 0x9c, 0x9b, /* data */ - 0x66, 0xf2, 0x27, 0x49, 0xad, 0x66, 0x7e, 0x6b, /* data */ - 0xea, 0xdf, 0x14, 0x4b, /* data */ - 0x81, 0x42, 0x30, 0x00, /* opcode: LOAD PCR3, v0 */ - 0x81, 0x42, 0x40, 0x00, /* opcode: LOAD PCR4, v0 */ -}; - static const uint8_t vendor[] = "Guntermann & Drunck"; - /** * @brief read a bunch of data from MMC into memory. * @@ -1013,6 +988,30 @@ static int first_stage_init(void) #endif #ifdef CCDM_SECOND_STAGE +static const uint8_t prg_stage2_prepare[] = { + 0x00, 0x80, 0x00, 0x00, /* opcode: SYNC PCR0 */ + 0x00, 0x84, 0x00, 0x00, /* opcode: SYNC PCR1 */ + 0x00, 0x88, 0x00, 0x00, /* opcode: SYNC PCR2 */ + 0x00, 0x8c, 0x00, 0x00, /* opcode: SYNC PCR3 */ + 0x00, 0x90, 0x00, 0x00, /* opcode: SYNC PCR4 */ +}; + +static const uint8_t prg_stage2_success[] = { + 0x81, 0x02, 0x40, 0x14, /* opcode: LOAD PCR4, #<20B data> */ + 0x48, 0xfd, 0x95, 0x17, 0xe7, 0x54, 0x6b, 0x68, /* data */ + 0x92, 0x31, 0x18, 0x05, 0xf8, 0x58, 0x58, 0x3c, /* data */ + 0xe4, 0xd2, 0x81, 0xe0, /* data */ +}; + +static const uint8_t prg_stage_fail[] = { + 0x81, 0x01, 0x00, 0x14, /* opcode: LOAD v0, #<20B data> */ + 0xc0, 0x32, 0xad, 0xc1, 0xff, 0x62, 0x9c, 0x9b, /* data */ + 0x66, 0xf2, 0x27, 0x49, 0xad, 0x66, 0x7e, 0x6b, /* data */ + 0xea, 0xdf, 0x14, 0x4b, /* data */ + 0x81, 0x42, 0x30, 0x00, /* opcode: LOAD PCR3, v0 */ + 0x81, 0x42, 0x40, 0x00, /* opcode: LOAD PCR4, v0 */ +}; + static int second_stage_init(void) { static const char mac_suffix[] = ".mac"; diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c index c3607daf46..3dc8cbd6a5 100644 --- a/board/phytec/pcm058/pcm058.c +++ b/board/phytec/pcm058/pcm058.c @@ -108,6 +108,7 @@ static iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +#ifdef CONFIG_CMD_NAND /* NAND */ static iomux_v3_cfg_t const nfc_pads[] = { MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), @@ -130,11 +131,7 @@ static iomux_v3_cfg_t const nfc_pads[] = { MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), }; - - -/* GPIOS */ -static iomux_v3_cfg_t const gpios_pads[] = { -}; +#endif static struct i2c_pads_info i2c_pad_info2 = { .scl = { @@ -167,7 +164,7 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; -#ifndef CONFIG_CMD_NAND +#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD) static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 8b34a80e8f..fb691c22d9 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -378,7 +378,7 @@ static void board_backlight_brightness(int br) /* LEDs on */ reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); - if (!(reg & BACKLIGHT_ENABLE)); + if (!(reg & BACKLIGHT_ENABLE)) out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg | BACKLIGHT_ENABLE); } else { diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 3e842d3187..3e81521399 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <spl.h> #include <serial.h> @@ -26,6 +27,7 @@ #include <asm/emif.h> #include <asm/gpio.h> #include <asm/omap_sec_common.h> +#include <asm/omap_mmc.h> #include <i2c.h> #include <miiphy.h> #include <cpsw.h> @@ -254,163 +256,222 @@ int spl_start_uboot(void) } #endif -#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr = { - 266, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_ddr_evm_sk = { - 303, OSC-1, 1, -1, -1, -1, -1}; -const struct dpll_params dpll_ddr_bone_black = { - 400, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params *get_dpll_ddr_params(void) +{ + int ind = get_sys_clk_index(); + + if (board_is_evm_sk()) + return &dpll_ddr3_303MHz[ind]; + else if (board_is_bone_lt() || board_is_icev2()) + return &dpll_ddr3_400MHz[ind]; + else if (board_is_evm_15_or_later()) + return &dpll_ddr3_303MHz[ind]; + else + return &dpll_ddr2_266MHz[ind]; +} -void am33xx_spl_board_init(void) +static u8 bone_not_connected_to_ac_power(void) { - int mpu_vdd; + if (board_is_bone()) { + uchar pmic_status_reg; + if (tps65217_reg_read(TPS65217_STATUS, + &pmic_status_reg)) + return 1; + if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { + puts("No AC power, switching to default OPP\n"); + return 1; + } + } + return 0; +} - /* Get the frequency */ - dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); +const struct dpll_params *get_dpll_mpu_params(void) +{ + int ind = get_sys_clk_index(); + int freq = am335x_get_efuse_mpu_max_freq(cdev); + + if (bone_not_connected_to_ac_power()) + freq = MPUPLL_M_600; + + if (board_is_bone_lt()) + freq = MPUPLL_M_1000; + + switch (freq) { + case MPUPLL_M_1000: + return &dpll_mpu_opp[ind][5]; + case MPUPLL_M_800: + return &dpll_mpu_opp[ind][4]; + case MPUPLL_M_720: + return &dpll_mpu_opp[ind][3]; + case MPUPLL_M_600: + return &dpll_mpu_opp[ind][2]; + case MPUPLL_M_500: + return &dpll_mpu_opp100; + case MPUPLL_M_300: + return &dpll_mpu_opp[ind][0]; + } - if (board_is_bone() || board_is_bone_lt()) { - /* BeagleBone PMIC Code */ - int usb_cur_lim; + return &dpll_mpu_opp[ind][0]; +} - /* - * Only perform PMIC configurations if board rev > A1 - * on Beaglebone White - */ - if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) - return; +static void scale_vcores_bone(int freq) +{ + int usb_cur_lim, mpu_vdd; - if (i2c_probe(TPS65217_CHIP_PM)) - return; + /* + * Only perform PMIC configurations if board rev > A1 + * on Beaglebone White + */ + if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) + return; - /* - * On Beaglebone White we need to ensure we have AC power - * before increasing the frequency. - */ - if (board_is_bone()) { - uchar pmic_status_reg; - if (tps65217_reg_read(TPS65217_STATUS, - &pmic_status_reg)) - return; - if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { - puts("No AC power, disabling frequency switch\n"); - return; - } - } + if (i2c_probe(TPS65217_CHIP_PM)) + return; - /* - * Override what we have detected since we know if we have - * a Beaglebone Black it supports 1GHz. - */ - if (board_is_bone_lt()) - dpll_mpu_opp100.m = MPUPLL_M_1000; + /* + * On Beaglebone White we need to ensure we have AC power + * before increasing the frequency. + */ + if (bone_not_connected_to_ac_power()) + freq = MPUPLL_M_600; - /* - * Increase USB current limit to 1300mA or 1800mA and set - * the MPU voltage controller as needed. - */ - if (dpll_mpu_opp100.m == MPUPLL_M_1000) { - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; - } else { - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; - } + /* + * Override what we have detected since we know if we have + * a Beaglebone Black it supports 1GHz. + */ + if (board_is_bone_lt()) + freq = MPUPLL_M_1000; - if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, - TPS65217_POWER_PATH, - usb_cur_lim, - TPS65217_USB_INPUT_CUR_LIMIT_MASK)) - puts("tps65217_reg_write failure\n"); + if (freq == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + } - /* Set DCDC3 (CORE) voltage to 1.125V */ - if (tps65217_voltage_update(TPS65217_DEFDCDC3, - TPS65217_DCDC_VOLT_SEL_1125MV)) { - puts("tps65217_voltage_update failure\n"); - return; - } + switch (freq) { + case MPUPLL_M_1000: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + break; + case MPUPLL_M_800: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + break; + case MPUPLL_M_720: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + break; + case MPUPLL_M_600: + case MPUPLL_M_500: + case MPUPLL_M_300: + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + break; + } - /* Set CORE Frequencies to OPP100 */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_POWER_PATH, + usb_cur_lim, + TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n"); - /* Set DCDC2 (MPU) voltage */ - if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { - puts("tps65217_voltage_update failure\n"); - return; - } + /* Set DCDC3 (CORE) voltage to 1.10V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1100MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } - /* - * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. - * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. - */ - if (board_is_bone()) { - if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, - TPS65217_DEFLS1, - TPS65217_LDO_VOLTAGE_OUT_3_3, - TPS65217_LDO_MASK)) - puts("tps65217_reg_write failure\n"); - } else { - if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, - TPS65217_DEFLS1, - TPS65217_LDO_VOLTAGE_OUT_1_8, - TPS65217_LDO_MASK)) - puts("tps65217_reg_write failure\n"); - } + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + /* + * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. + * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. + */ + if (board_is_bone()) { if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, - TPS65217_DEFLS2, + TPS65217_DEFLS1, TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK)) puts("tps65217_reg_write failure\n"); } else { - int sil_rev; + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + } - /* - * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all - * MPU frequencies we support we use a CORE voltage of - * 1.1375V. For MPU voltage we need to switch based on - * the frequency we are running at. - */ - if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) - return; + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); +} - /* - * Depending on MPU clock and PG we will need a different - * VDD to drive at that speed. - */ - sil_rev = readl(&cdev->deviceid) >> 28; - mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, - dpll_mpu_opp100.m); +void scale_vcores_generic(int freq) +{ + int sil_rev, mpu_vdd; - /* Tell the TPS65910 to use i2c */ - tps65910_set_i2c_control(); + /* + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * MPU frequencies we support we use a CORE voltage of + * 1.10V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) + return; - /* First update MPU voltage. */ - if (tps65910_voltage_update(MPU, mpu_vdd)) - return; + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq); - /* Second, update the CORE voltage. */ - if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) - return; + /* Tell the TPS65910 to use i2c */ + tps65910_set_i2c_control(); - /* Set CORE Frequencies to OPP100 */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - } + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0)) + return; - /* Set MPU Frequency to what we detected now that voltages are set */ - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); } -const struct dpll_params *get_dpll_ddr_params(void) +void gpi2c_init(void) { - if (board_is_evm_sk()) - return &dpll_ddr_evm_sk; - else if (board_is_bone_lt() || board_is_icev2()) - return &dpll_ddr_bone_black; - else if (board_is_evm_15_or_later()) - return &dpll_ddr_evm_sk; + /* When needed to be invoked prior to BSS initialization */ + static bool first_time = true; + + if (first_time) { + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); + first_time = false; + } +} + +void scale_vcores(void) +{ + int freq; + + gpi2c_init(); + freq = am335x_get_efuse_mpu_max_freq(cdev); + + if (board_is_bone()) + scale_vcores_bone(freq); else - return &dpll_ddr; + scale_vcores_generic(freq); } void set_uart_mux_conf(void) @@ -892,3 +953,33 @@ void board_fit_image_post_process(void **p_image, size_t *p_size) secure_boot_verify_image(p_image, p_size); } #endif + +#if !CONFIG_IS_ENABLED(OF_CONTROL) +static const struct omap_hsmmc_plat am335x_mmc0_platdata = { + .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, + .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, + .cfg.f_min = 400000, + .cfg.f_max = 52000000, + .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, + .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + +U_BOOT_DEVICE(am335x_mmc0) = { + .name = "omap_hsmmc", + .platdata = &am335x_mmc0_platdata, +}; + +static const struct omap_hsmmc_plat am335x_mmc1_platdata = { + .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE, + .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT, + .cfg.f_min = 400000, + .cfg.f_max = 52000000, + .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, + .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + +U_BOOT_DEVICE(am335x_mmc1) = { + .name = "omap_hsmmc", + .platdata = &am335x_mmc1_platdata, +}; +#endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 2572029a25..f633e2f85d 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -49,8 +49,6 @@ void do_board_detect(void) #ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define NUM_OPPS 6 - const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { { /* 19.2 MHz */ {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ @@ -317,25 +315,6 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) return; } -/* - * get_sys_clk_index : returns the index of the sys_clk read from - * ctrl status register. This value is either - * read from efuse or sysboot pins. - */ -static u32 get_sys_clk_index(void) -{ - struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; - u32 ind = readl(&ctrl->statusreg), src; - - src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; - if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ - return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> - CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); - else /* Value read from SYS BOOT pins */ - return ((ind & CTRL_SYSBOOT_15_14_MASK) >> - CTRL_SYSBOOT_15_14_SHIFT); -} - const struct dpll_params *get_dpll_ddr_params(void) { int ind = get_sys_clk_index(); diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 09bebeb71b..45f1d5de39 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -564,53 +564,6 @@ static iomux_v3_cfg_t const rgb_pads[] = { MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB), }; -static iomux_v3_cfg_t const vga_pads[] = { -#ifdef FOR_DL_SOLO - /* DualLite/Solo doesn't have IPU2 */ - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, -#else - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, - MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU2_DI0_PIN02, - MX6_PAD_DI0_PIN3__IPU2_DI0_PIN03, - MX6_PAD_DISP0_DAT0__IPU2_DISP0_DATA00, - MX6_PAD_DISP0_DAT1__IPU2_DISP0_DATA01, - MX6_PAD_DISP0_DAT2__IPU2_DISP0_DATA02, - MX6_PAD_DISP0_DAT3__IPU2_DISP0_DATA03, - MX6_PAD_DISP0_DAT4__IPU2_DISP0_DATA04, - MX6_PAD_DISP0_DAT5__IPU2_DISP0_DATA05, - MX6_PAD_DISP0_DAT6__IPU2_DISP0_DATA06, - MX6_PAD_DISP0_DAT7__IPU2_DISP0_DATA07, - MX6_PAD_DISP0_DAT8__IPU2_DISP0_DATA08, - MX6_PAD_DISP0_DAT9__IPU2_DISP0_DATA09, - MX6_PAD_DISP0_DAT10__IPU2_DISP0_DATA10, - MX6_PAD_DISP0_DAT11__IPU2_DISP0_DATA11, - MX6_PAD_DISP0_DAT12__IPU2_DISP0_DATA12, - MX6_PAD_DISP0_DAT13__IPU2_DISP0_DATA13, - MX6_PAD_DISP0_DAT14__IPU2_DISP0_DATA14, - MX6_PAD_DISP0_DAT15__IPU2_DISP0_DATA15, -#endif -}; - static void do_enable_hdmi(struct display_info_t const *dev) { imx_enable_hdmi_phy(); diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index b2b12e4519..e54afa1952 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -111,22 +111,6 @@ static void setup_gpmi_nand(void) } #endif -static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { - MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - #ifdef CONFIG_VIDEO_MXS static iomux_v3_cfg_t const lcd_pads[] = { MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), |